JP2001156857A - Converter for lan - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a converter for LAN which can communicate large- capacity data independently of 1,514 bytes as a maximum frame length of an Ethernet (R). SOLUTION: A serial/parallel conversion part 4 writes data in a FIFO 6 and outputs this data to a frame detector 5. The frame detector 5 outputs a signal corresponding to the frame length of this data to a delay circuit 7. The delay circuit 7 delays this signal for a prescribed time and outputs it to a Read-enable signal generation part 9. The Read-enable signal generation part 9 generates a Read-enable 10 signal from an Empty Flag outputted from the FIFO 6 and the signal from the delay circuit 7 and outputs this generated signal to a parallel/serial conversion part 10. The parallel/serial conversion part 10 reads out data from the FIFO 6 on the basis of this signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a LAN converter used for long-distance data transfer between LAN devices via a LAN (Local Area Network) and for transmitting and receiving transmission data.

[0002]

2. Description of the Related Art FIG. 5 is a diagram showing a configuration of a conventional LAN converter. As shown in FIG.
The converter for MAC includes a MAC (Media Access Control) 31 and a PHY (Physical Protocol:
Physical protocol) 32, 33 and system clock 3
4, an O / E and E / O converter (optical / electrical and electric / optical converter) 35, and a cable 38 such as a twisted pair is connected to the PHY 32 by an O / E and E / O converter. An optical fiber (not shown) is connected to the container.

A conventional LA having such a configuration will be described below.
The operation of the N converter will be described. Twisted pair 38
Receives electrical serial data from
Output to HY32. This electrical data, which is serial data, is parallel-converted and code-converted by the PHY 32, and is converted into M based on a clock synchronized with the data.
Output to AC31.

The transmission destination of this data is read by the MAC 31, and the data is transmitted to the PHY 3 by the transmission destination.
2, or output to the PHY 33. If the data transmission destination is a terminal device connected to the end of the optical fiber 38, the MAC 31 outputs this data to the PHY 33 in synchronization with the clock output from the system clock 34.

[0005] The PHY 33 encodes and serializes input data based on a format suitable for transmission over an optical fiber, and converts the data into an O / E and an E / O converter 3.
5 is output. The O / E and E / O converter 35 converts the input electrical data into optical data and outputs the optical data to an optical fiber.

In the Ethernet standard to which the above-described conventional LAN converter is applied, the maximum frame length of transmission data is specified as 1514 bytes, and packets having a frame length exceeding this standard are transmitted to the conventional LAN converter. If it is input, the MAC 31 in the LAN converter cannot recognize this packet, recognizes it as an illegal packet, and discards it.

[0007] For example, one such as an ISL frame or a jumbo frame containing Vtag information of 1548 bytes is used.
When data having a frame length exceeding 514 bytes is received, there is a problem that communication becomes impossible. When MAC is used, CPU, DRA
Since an M, a ROM, and software for driving them are also required, there is a problem that the number of components is large and the cost is high despite the conversion of the medium.

[0008]

SUMMARY OF THE INVENTION The present invention has been made in view of such circumstances, and realizes a large-capacity data communication without depending on the maximum frame length of 1514 bytes of Ethernet. An object of the present invention is to provide an inexpensive LAN converter.

[0009]

In order to achieve the above object, according to the first aspect of the present invention, there is provided a storage means for temporarily storing received data, and a method for writing the received data to the storage means. Data writing means for outputting a data write signal at the time of starting data writing; delay means for receiving the data write signal and delaying and outputting the data write signal for a predetermined time;
Data reading means for starting reading data from the storage means based on the signal output from the delay means.

According to a second aspect of the present invention, in the LAN converter according to the first aspect, a receiving clock forming section for forming a receiving clock based on received data, and a transmitting clock forming section for outputting a transmitting clock. The delay unit includes an error between the reception clock and the transmission clock, and a delay time set according to a capacity of the storage unit. A signal is delayed and output to the data reading means.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 3 is a diagram showing a configuration of a network to which a LAN converter according to an embodiment of the present invention is applied. In FIG. 3, reference numeral 21 denotes a switching HUB (hub). This switching HU
A plurality of terminal devices (not shown) are connected to B21,
N has been constructed. Reference numeral 22 denotes UTP (Unshielded T
wist Pair) cable, for example, 100BASE-
TX and the like. Reference numeral 23 denotes a LAN converter, one end of which is connected to the switching hub 21 via a UTP cable 22, and the other end of which is connected to an opposing LAN converter 25 via a single mode optical fiber 24. Opposite LAN converter 2
The other end of the switching hub 5 is connected to a switching hub 27 via a UTP cable 26. Note that switching H
Similarly to the switching HUB 21, a plurality of devices such as terminal devices are connected to the UB 27 (not shown) to construct a LAN.

The LAN converters 23 and 25 in the above-described configuration convert 100BASE-TX, which is electrical data received from the switching hub 21 or 27 via the UTP cable 22 or 26, into 100BASE-FX which is optical data. Later, the optical data 100BASE-
FX is transmitted, and the optical data 100BASE-FX received via the single mode optical fiber is converted into the electrical data 100BASE-TX, and the converted data is transmitted to the other device via the UTP cable 22 or 26. Has functions. Note that the above-described switching HUB 21, 2
Instead of 7, it is also possible to use a router.

FIG. 1 shows an LA according to an embodiment of the present invention.
FIG. 3 is a block diagram illustrating a configuration of an N converter. In this figure, reference numeral 1 denotes a 100 BASE-FX receiver that receives 125 Mb / s data, reference numeral 2 denotes a decoder that decodes the received data by 5B4B, and reference numeral 3 denotes a decoder based on the 4-bit data output from the decoder 2. Reference numeral 4 denotes a serial / parallel conversion unit that converts serial data into a 4-bit parallel signal.

Reference numeral 5 denotes a frame detector, reference numeral 6 denotes a FIFO (First-In First-Out memory; buffer), and reference numeral 7 denotes a delay in rising of write data to the FIFO 6 output from the frame detector 5. Reference numeral 8 denotes a system clock forming unit that outputs a transmission clock to each block, and reference numeral 9 denotes R from the EmptyFlag output from the FIFO 6 and the signal from the delay circuit 7.
An ead-Enable signal is formed, and a new TX
A Read-Enable signal forming unit that forms -CLK and outputs it to the FIFO 6 and the parallel / serial conversion unit 10;

Reference numeral 10 denotes a parallel / serial conversion unit for converting 4-bit data output from the FIFO 6 into serial data, reference numeral 11 denotes an encoder for converting 4-bit data to 5 bits, and reference numeral 12 denotes 125 Mb to the UTP cable. / BA for transmitting / s data
SE-TX driver. Note that the above-mentioned 100 BAS
E-FX receiver is a LAN that faces via optical fiber
100BASE-
The TX driver is connected to the switching hub via 100BASE-TX.

The circuit having the above-described configuration is a circuit having only a function of receiving optical data and transmitting electric data. Therefore, the LAN converter of the present invention has almost the same internal configuration as the above-described circuit, and has a 100BASE-F
X receiver 1 to 100BASE-FX driver
0BASE-TX driver 12 to 100BASE-TX
Another circuit is provided for the receiver. The LAN converter of the present invention includes these two circuits, so that transmission and reception of optical and electrical data can be performed.

Next, in the above configuration, the operation of the LAN converter according to one embodiment of the present invention will be described with reference to FIGS.
This will be described with reference to the timing chart of FIG. First, 1
00BASE-FX receiver 1 is an optical fiber (not shown)
When 100BASE-FX optical data is received via
The 100BASE-FX receiver 1 outputs this data to the decoder 2. The decoder 2 decodes the 5-bit data into 4 bits, and outputs the 4-bit decoded data to the reception clock forming unit 3 and the serial / parallel conversion unit 4.

The receiving clock forming unit 3 receives 25M data based on the 4-bit data output from the decoder 2 and the transmission clock S-CLK from the system clock forming unit 8.
A reception clock R-CLK (refer to FIG. 2A) is formed, and the reception clock R-CLK is output to the FIFO 6. On the other hand, the serial / parallel converter 4 converts the input serial data into 4-bit parallel data, and synchronizes the 4-bit parallel data Data1 with the reception clock R-CLK (see (b) in FIG. 2). ) FI
Output to the FO 6 and output this data Data 1 to the frame detector 5.

When the frame detector 5 receives the data Data1 from the serial / parallel converter 4, it sets the FL1 signal to "1" in synchronization with the reception clock R-CLK, and the serial / parallel converter 4 outputs the data Data1. When the signal FL1 disappears, the FL1 signal is set to "0" in synchronization with the reception clock R-CLK and output to the FIFO 6 and the delay circuit 7 (see (c) in FIG. 2). Thereby, the delay circuit 7
And FIFO 6 are transmitted from serial / parallel converter 4 to FI
The frame length of data Data1 written to FO6 can be recognized.

Next, the delay circuit 7 delays the FL1 signal received from the frame detector 5 by a predetermined delay time (see FIG. 2E) to generate a system clock forming unit 8 Transmission clock S- received from
The signal is output to the FIFO 6 and the read-enable signal forming unit 9 in synchronization with CLK (see (d) of FIG. 2).

The Read-Enable signal forming unit 9
At the same time as receiving the FL2 signal of “1” from the delay circuit 7, it sets the Read-Enable 6 signal (see (f) of FIG. 2) to “1” and outputs the signal to the FIFO 6. FIFO6
When the Read-Enable 6 signal of “1” is received from the Read-Enable signal forming unit 9, it starts outputting the Data 2 to the parallel / serial converter 10 in synchronization with the transmission clock S-CLK (FIG. 2 (g)).

The FIFO 6 has a value of "1" for Rea.
Upon receiving the d-Enable6 signal from the Read-Enable signal forming unit 9, the
(Refer to (h) of FIG. 2) to “1” to make Read-Ena
output to the ble signal forming unit 9.

On the other hand, the Read-Enable signal forming section 9 transmits the transmission clock SC from the transmission clock forming section 8.
LK is adjusted in timing to form TX-CLK and FI
The signal is output to the FO 6 and the parallel / serial conversion unit 10 (see (i) in FIG. 2). Also, Read-Enable
After a predetermined time after outputting the Read-Enable6 signal, the signal forming unit 9 synchronizes with the TX-CLOCK and sets the Read-Enable signal.
-Set the Enable10 signal to "1" and output it to the parallel / serial converter 10. The parallel / serial converter 10 receives the Read-Enable 10 signal “1” (see (nu) in FIG. 2) and, at the same time,
The reading of the data Data-S / P output from is started (see (l) in FIG. 2).

Next, when the stored data Data2 becomes the remaining one bit, the FIFO6 sets EmptyFlag to "0" in synchronization with the transmission clock, and
The signal is output to the ad-Enable signal forming unit 9 (see (h) in FIG. 2). Read-Enable signal forming section 9
When the EmptyFlag which is “0” is received from the FIFO 6, the Read-E which has been “1” after a predetermined time has elapsed.
The signal “number10” is set to “0” in synchronization with TX-CLK and output to the parallel / serial converter 10. The parallel / serial conversion unit 10 reads “0” Read-
Upon receiving the Enable10 signal, the reading of the data Data-S / P from the FIFO 6 ends.

The time from when the parallel / serial converter 10 finishes reading data Data-S / P to when the next data is written to the FIFO 6 is set in advance. Therefore, the Read-Enable signal forming unit 9 outputs the Empty “0” from the FIFO 6.
After receiving the Flag and before writing of the next data is started, a Reset signal is output to the FIFO 6.
When this signal is input, the FIFO 6 resets the stored data and empties the memory.

The parallel / serial converter 10 is an FIF
The 4-bit data read from O6 is converted into serial data and output to the encoder 11. Encoder 11
Receives serial data of 4 bits and converts the code from 4 bits to 5 bits,
Output to 0BASE-TX driver. 100 BAS
Upon receiving the data, the E-TX driver transmits the data to the UTP cable. The transmitted data is 125 Mb / s data.

Next, the above-described delay circuit 7 will be described in detail. As described above, in the LAN converter, there is a maximum of 20 between the reception clock R-CLK (see FIG. 2A) and the transmission clock S-CLK (see FIG. 2D).
An error of 0 ppm occurs (error D in FIG. 2). Therefore, the data D from the serial / parallel converter 4 to the FIFO 6
If writing and data reading from the FIFO 6 to the parallel / serial conversion unit 10 are started at the same time, the reading may end before the writing ends.

Then, when writing to the FIFO 6 is started,
By providing a delay time between the start of reading and the start of reading, the above-described phenomenon can be avoided even when the maximum frame is transmitted. This delay time is given by the following equation (1). Delay time = Maximum frame transit time * Clock error (1) As described above, the delay time (see (e) in FIG. 2) is obtained by multiplying the transit time of the maximum frame by the error between the reception clock and the transmission clock. Become.

In this embodiment, the maximum frame length is 200
The delay time is set with 0 bytes and a clock error of 200 ppm. That is, the transit time of the maximum frame length of 2000 bytes is 2000 [bytes] * 8 * 10 ^-6 [S] = 160 [μS] (2), and the error between the transmission clock and the reception clock is 2
Since it was set to 00 ppm, 200 ppm and 16
Multiplying by 0 [μS] gives 200 [ppm] * 160 [μS] = 32 [nS] (3).

Therefore, the delay time should be set to 32 [ns] or more. In the present embodiment, a margin is set and the delay time is set to 40 [ns]. The delay time is set according to the memory capacity of the FIFO 6 and the maximum frame length that can be processed by the LAN converter, and can be set arbitrarily.

In this embodiment, a LAN converter for transmitting / receiving data by performing electrical / optical or optical / electrical conversion has been exemplified. However, the present invention is not limited to this. Alternatively, the present invention can be applied to a LAN converter for transmitting and receiving data by performing light / light conversion.

[0032]

FIG. 4 shows an embodiment of the present invention. In this figure, 41 is a router capable of transmitting an ISL frame including VLAN-Tag information, 42 is a switching HUB capable of handling the same frame as the router 41, 43
Is a LAN converter, 44 is a monitoring terminal device for monitoring the connection status of the router 41 and the switching hub 42, 45 is a UTP cable, and 46 is an optical fiber.
In such a network system, the ISL frame including the upper part of the VLAN-Tag having a frame length of 1548 bytes is transmitted from the router 41 to the LAN converter, and the frame length is 1 frame.
It was confirmed that communication of 548 bytes was possible.

[0033]

As described above, according to the LAN converter of the present invention, the storage means for temporarily storing the received data, the received data is written to the storage means, and the data writing is started when the data writing is started. A data writing unit for outputting a data writing signal, receiving the data writing signal, and transmitting the data writing signal for a predetermined time;
There is a signal delay unit that outputs the data with a delay, and a data read unit that starts reading data from the storage unit based on the signal output from the delay unit.

As described above, since the LAN converter of the present invention does not include the MAC which is a bridge controller as a component, a large-capacity data transmission can be performed without depending on the maximum frame length of 1541 bytes which is an Ethernet standard. You. Further, since the LAN converter of the present invention is configured as described above, the MAC is not used. Thus, the CPU required to use the MAC, D
A RAM, a ROM, software for driving the RAM, a ROM, and the like are not required, and the cost can be reduced.

According to the second aspect of the present invention, there is provided a receiving clock forming unit for forming a receiving clock based on received data, and a transmitting clock forming unit for outputting a transmitting clock, wherein the signal delay The means delays the write signal input from the data writing means based on an error between the reception clock and the transmission clock, and a delay time set according to a capacity of the storage means, Output to data reading means.

By providing a delay between the start of writing data to the storage unit and the start of reading data from the storage unit, the data writing caused by an error between the reception clock and the transmission clock can be reduced. Also, it is possible to avoid the phenomenon that the data reading ends first.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a LAN converter according to a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of each unit in the embodiment.

FIG. 3 is an example of a network using the LAN converter of the present invention.

FIG. 4 is a network configuration diagram for confirming the operation of the LAN converter of the present invention.

FIG. 5 is a block diagram illustrating a configuration of a conventional LAN converter.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 100BASE-FX receiver 2 Decoder 3 Receive clock formation part 4 Serial / parallel conversion part (data writing means) 5 Frame detector 6 FIFO (storage means) 7 Delay circuit (delay means) 8 System clock formation part 9 Read-Enable signal Forming unit 10 Parallel / serial conversion unit (data reading means) 11 Encoder 12 100 BASE-TX driver

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Hidenori Shigekuni 1-5-1 Kiba, Koto-ku, Tokyo Inside Fujikura Co., Ltd. (72) Inventor Nao Yamada 1-5-1, Kiba 1-chome, Koto-ku, Tokyo Stock Inside Fujikura (72) Inventor Katsuyuki Arai 1-5-1, Kiba, Koto-ku, Tokyo F-term inside Fujikura Corporation (reference) 5K030 GA04 HC14 HD07 JL03 KA02 5K032 AA04 DA07 DA18 DB19 5K034 AA10 DD03 EE01 HH23 HH42 5K047 AA15 BB02 BB12 GG52 LL04 LL05 MM26 MM36 9A001 BB03 BB04 CC08 EE02 JJ12 KK56

Claims (2)

[Claims] A storage unit for temporarily storing received data; and a storage unit for writing the received data to the storage unit.
Data writing means for outputting a data write signal at the time of starting the data writing; delay means for receiving the data write signal and delaying and outputting the data write signal for a predetermined time; and outputting from the delay means. And a data reading means for starting reading data from the storage means based on the received signal. 2. A receiving clock forming unit that forms a receiving clock based on received data, and a transmitting clock forming unit that outputs a transmitting clock, wherein the delay unit includes: a receiving clock; a transmitting clock; Error, and, based on a delay time set according to the capacity of the storage means, the write signal input from the data writing means is delayed and output to the data reading means. The converter for a LAN according to claim 1.