JP2001156062A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method

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Publication number
JP2001156062A
JP2001156062A JP33314799A JP33314799A JP2001156062A JP 2001156062 A JP2001156062 A JP 2001156062A JP 33314799 A JP33314799 A JP 33314799A JP 33314799 A JP33314799 A JP 33314799A JP 2001156062 A JP2001156062 A JP 2001156062A
Authority
JP
Japan
Prior art keywords
film
insulating film
semiconductor
forming
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP33314799A
Other languages
Japanese (ja)
Inventor
Kazuo Matsuzaki
一夫 松崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP33314799A priority Critical patent/JP2001156062A/en
Publication of JP2001156062A publication Critical patent/JP2001156062A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a surface protection film for semiconductor devices which is superior in water penetration resistance and etching resistance and not vulnerable to electric influences of impurity ions intruding from the outside. SOLUTION: A first oxide film is formed on an IC substrate 1, an SiO2 grain film having a high porosity is formed on the first oxide film, and a second oxide film and an NiO are formed on the SiO2 grain film. Owing to the SiO2 grain film, a surface protection film having a low permittivity is obtained.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】この発明は、高耐圧ICなど
の半導体装置に関し、特にその表面保護膜に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as a high withstand voltage IC, and more particularly to a surface protection film for the semiconductor device.

【0002】[0002]

【従来の技術】プレーナ型の半導体装置では、半導体表
面の不活性化処理が不可欠である。それは、半導体表面
が電界に晒されるプレーナ型の素子は、耐圧特性などの
電気的特性が表面電荷の影響を受けるためである。この
半導体表面を保護し、不活性化する方法としては、半導
体表面を、LOCOS、PSG、BPSGなどの酸化膜
やプラズマCVD窒化シリコン膜などで覆うことが一般
的に知られている。このように酸化膜や窒化シリコン膜
を被覆することで、パッケージ樹脂や、パッケージを通
して外界から侵入する不純物イオンを防止し、この不純
物イオンによる電気的特性への影響を防止することがで
きる。勿論、これらの膜の被覆は、機械的損傷を防ぐ目
的もある。
2. Description of the Related Art In a planar type semiconductor device, a passivation treatment of a semiconductor surface is indispensable. This is because a planar element whose semiconductor surface is exposed to an electric field has electrical characteristics such as withstand voltage characteristics affected by surface charges. As a method of protecting and inactivating the semiconductor surface, it is generally known that the semiconductor surface is covered with an oxide film such as LOCOS, PSG, BPSG, or a plasma CVD silicon nitride film. By covering the oxide film or the silicon nitride film in this manner, it is possible to prevent impurity ions from entering from outside through the package resin and the package, and to prevent the impurity ions from affecting the electrical characteristics. Of course, the coating of these films also has the purpose of preventing mechanical damage.

【0003】近年、これらの半導体装置の高性能化(例
えば、微細化、高耐圧化、低オン抵抗化、高集積化な
ど)と共に、パッケージの低コスト化に対する要求が強
い。この低コストのパッケージを使用した場合は、10
18〜1019charges/cm2 の表面電荷量の不純
物イオンが付着することもあり得る。高耐圧ICなどの
半導体装置の電気的特性に影響を与えないための表面電
荷量は、1×1012charges/cm2 程度との報
告(R.B.Comizzoli and J.W.O
senbach,Proc.Symp.on High
Voltage and Smart Power
Devices,Electrochem.Soc.,
Philadelphia,PA,pp232−24
0,1987)がある。ただし、表面保護膜に欠陥があ
れば、1×1010charges/cm2 の電荷量でも
電気的特性に重大な影響を与えると報告されている。ま
た欠陥がなければ1×1015charges/cm2
電荷量でも電気的特性に影響を与えないとの報告(J.
W.Osenbach et al.,Proc.24
th reliability Physics Sy
mp.,pp.239−246,1986)もある。
In recent years, there is a strong demand for higher performance (for example, miniaturization, higher breakdown voltage, lower on-resistance, higher integration, etc.) of these semiconductor devices and lower cost of the packages. With this low cost package, 10
Impurity ions having a surface charge amount of 18 to 10 19 charges / cm 2 may be attached. It has been reported that the amount of surface charge so as not to affect the electrical characteristics of a semiconductor device such as a high withstand voltage IC is about 1 × 10 12 charges / cm 2 (RB Comizoli and JWO).
Senbach, Proc. Symp. on High
Voltage and Smart Power
Devices, Electrochem. Soc. ,
Philadelphia, PA, pp 232-24
0, 1987). However, it is reported that if the surface protective film has a defect, even a charge amount of 1 × 10 10 charges / cm 2 has a significant effect on electrical characteristics. It is also reported that if there is no defect, even a charge amount of 1 × 10 15 charges / cm 2 does not affect the electrical characteristics (J.
W. Osenbach et al. Proc. 24
th reliability Physics Sy
mp. Pp. 239-246, 1986).

【0004】[0004]

【発明が解決しようとする課題】しかし、前記したよう
に、1018〜1019charges/cm2 の表面電荷
量でも、半導体装置の電気的特性に影響を与えないため
には、表面保護膜の欠陥を完全になくするための工夫が
必要であると同時に、表面電荷量に影響されにくい表面
保護膜とすることが重要である。
However, as described above, even if the surface charge amount is 10 18 to 10 19 charges / cm 2 , the electrical characteristics of the semiconductor device should not be affected. It is necessary to devise a device for completely eliminating defects, and at the same time, it is important to provide a surface protective film that is hardly affected by the amount of surface charge.

【0005】前者の欠陥をなくするには、プロセス設備
や工程管理で対応できたが、低コストのパッケージに起
因した後者の表面電荷量については、制御が困難であ
り、従来の誘電体材料では対応が困難である。この表面
電荷量の影響が受けにくい表面保護膜としては、比誘電
率の小さな誘電体材料で形成される表面保護膜を用いれ
ばよい。なぜなら、比誘電率が小さいということは、表
面保護膜の表面に不純物イオンが付着しにくいというこ
とである。この比誘電率の小さな誘電体材料の開発は、
高速駆動ICの遅延の原因となるRC(R:配線抵抗、
C:配線間を埋める層間絶縁膜の容量)を小さくすべ
く、層間絶縁膜の領域で盛んである。そこでは、シリコ
ン酸化膜(比誘電率が2.5〜4)よりも小さなFおよ
びC添加のシリコン酸化膜(比誘電率が2.5〜3)や
有機ポリマーが検討されつつある。
[0005] To eliminate the former defect, it was possible to cope with the process equipment and process control. However, it is difficult to control the latter surface charge caused by a low-cost package. It is difficult to respond. As the surface protective film that is not easily affected by the surface charge amount, a surface protective film formed of a dielectric material having a small relative dielectric constant may be used. This is because a small relative dielectric constant means that impurity ions are unlikely to adhere to the surface of the surface protective film. The development of a dielectric material with a small relative dielectric constant
RC (R: wiring resistance, which causes delay of the high-speed driving IC,
(C: capacity of the interlayer insulating film filling the space between the wirings) is increased in the region of the interlayer insulating film. Here, F and C-added silicon oxide films (relative permittivity of 2.5 to 3) and organic polymers smaller than silicon oxide films (relative permittivity of 2.5 to 4) are being studied.

【0006】この表面電荷量の影響が受けにくい表面保
護膜は、単に比誘電率が小さいということだけでなく、
表面保護膜の本来の機能である耐浸水性、耐腐食性に優
れる必要がある。しかし、比誘電率を小さくするため
に、膜の穿孔率を高める(低密度の膜とする)(国際公
開番号WO94/25149号およびC.Jin他:M
RS Bulletin Vol22、pp39、19
97年)と、表面保護膜の本来の機能である耐浸水性、
耐腐食性が悪化する。
The surface protective film which is hardly affected by the amount of surface charges not only has a small relative permittivity but also has a small dielectric constant.
It is necessary to be excellent in water resistance and corrosion resistance which are the original functions of the surface protective film. However, in order to reduce the relative dielectric constant, the porosity of the membrane is increased (making the membrane a low density membrane) (WO 94/25149 and C. Jin et al .: M.
RS Bulletin Vol22, pp39, 19
1997) and the original function of the surface protective film, water resistance,
Corrosion resistance deteriorates.

【0007】この発明の目的は、前記の課題を解決し
て、耐浸水性、耐腐食性に優れ、且つ、外界から侵入し
た不純物イオンによる電気的影響を受けにくい半導体装
置の表面保護膜を提供することにある。
An object of the present invention is to solve the above-mentioned problems and to provide a surface protective film of a semiconductor device which is excellent in water resistance and corrosion resistance and is hardly electrically affected by impurity ions penetrating from the outside. Is to do.

【0008】[0008]

【課題を解決するための手段】前記の目的を達成するた
めに、半導体素子が形成された半導体基板と、該半導体
基板上に形成された半導体素子の電極配線部と前記半導
体基板上に第1絶縁膜を介して形成され、且つ、前記電
極配線部を選択的に被覆した多孔質の誘電体膜と、該誘
電体膜上に形成された膜密度が少なくとも2g/cc以
上の緻密な第2絶縁膜とを有する構成とする。
In order to achieve the above object, a semiconductor substrate on which a semiconductor element is formed, an electrode wiring portion of the semiconductor element formed on the semiconductor substrate, and a first substrate on the semiconductor substrate are provided. A porous dielectric film formed through an insulating film and selectively covering the electrode wiring portion; and a dense second dielectric film formed on the dielectric film having a film density of at least 2 g / cc or more. A structure including an insulating film.

【0009】前記多孔質の誘電体膜が、酸化物の粒子で
形成されるとよい。前記緻密な第2絶縁膜が、酸化シリ
コン膜、窒化シリコン膜もしくはそれらを積層した膜の
いずれかであるとよい。半導体素子が形成された半導体
基板と、該半導体基板上に形成された半導体素子の電極
配線部とを保護する半導体装置の表面保護膜の形成方法
において、前記半導体基板上に第1絶縁膜を形成する工
程と、該第1絶縁膜上と前記電極配線部上に誘電体膜を
形成する工程と、前記電極配線部上の前記誘電体膜を選
択的に除去する工程と、前記誘電体膜上に膜密度が少な
くとも2g/cc以上の緻密な第2絶縁膜を形成する工
程とを含む製造方法とする。
It is preferable that the porous dielectric film is formed of oxide particles. The dense second insulating film may be any one of a silicon oxide film, a silicon nitride film, and a stacked film thereof. In a method of forming a surface protection film of a semiconductor device for protecting a semiconductor substrate on which a semiconductor element is formed and an electrode wiring portion of the semiconductor element formed on the semiconductor substrate, forming a first insulating film on the semiconductor substrate Performing a step of: forming a dielectric film on the first insulating film and the electrode wiring portion; selectively removing the dielectric film on the electrode wiring portion; Forming a dense second insulating film having a film density of at least 2 g / cc or more.

【0010】前記金属配線部上の第2絶縁膜を選択的に
除去する工程と、該除去部に、金属配線膜を形成する工
程とを含む工程とするとよい。一般に、表面保護膜上の
誘電層に単位面積当たりある電荷量の電荷が存在すれ
ば、その結果発生する電圧が保護膜上に印加されたこと
となる。その結果、その下部のシリコン表面に電荷Qが
誘起され、この誘起された電荷が素子表面(半導体装置
の表面のこと)での耐圧低下やリーク電流増加などの悪
影響を及ぼすことになる。いま、表面保護膜上に電荷Q
が被着して電圧Vが発生するとする。この電荷Qと電圧
Vの関係は、表面保護膜の容量をCとすると、Q=CV
となる。シリコン表面に誘起される電荷もQとなる。従
って、付着した電荷Qを小さくするためには、表面保護
膜の容量Cを小さくする必要がある。表面保護膜の容量
Cは保護膜の厚さd、表面積S、誘電率εを用いてC=
εS/dと表される。即ち、Cを小さくするためには、
Sとdが一定の場合は、誘電率εの小さな表面保護膜と
する。
Preferably, the method includes a step of selectively removing the second insulating film on the metal wiring portion and a step of forming a metal wiring film in the removed portion. In general, if a certain amount of electric charge per unit area exists in the dielectric layer on the surface protective film, a voltage generated as a result is applied to the protective film. As a result, electric charge Q is induced on the silicon surface underneath, and the induced electric charge adversely affects the element surface (the surface of the semiconductor device) such as a decrease in breakdown voltage and an increase in leak current. Now, the charge Q on the surface protective film
And a voltage V is generated. The relationship between the charge Q and the voltage V is as follows, where C is the capacitance of the surface protection film.
Becomes The charge induced on the silicon surface also becomes Q. Therefore, in order to reduce the attached charge Q, it is necessary to reduce the capacitance C of the surface protective film. The capacitance C of the surface protective film is calculated using the thickness d of the protective film, the surface area S, and the dielectric constant ε.
It is expressed as εS / d. That is, to reduce C,
When S and d are constant, a surface protective film having a small dielectric constant ε is used.

【0011】誘電率εを小さくするために、表面保護膜
として穿孔率の高い(ポーラスな)酸化膜として、外界
から侵入した不純物イオンによる電気的影響を受けにく
くし、この酸化膜上に、膜密度が少なくとも2g/cc
以上の酸化シリコン膜、窒化シリコン膜もしくはそれら
を積層した膜を形成することで、耐腐食性を高めること
ができる。
In order to reduce the dielectric constant ε, a high-porosity (porous) oxide film as a surface protective film is made less susceptible to electrical influence by impurity ions penetrating from the outside. Density of at least 2 g / cc
By forming the above-described silicon oxide film, silicon nitride film, or a film obtained by stacking them, corrosion resistance can be increased.

【0012】[0012]

【発明の実施の形態】図1は、この発明の一実施例の表
面保護膜の製造方法で、同図(a)〜同図(e)は工程
順に示した要部工程断面図である。まず、イソプロピル
アルコールに粒度分布の中心が20nmのSiO2 の粉
体を入れ、単分散液とした。この分散液4を、図示しな
いICチップが集積したウエハの外周1mmに設けたポ
リイミドのダム(高さ1.5μm)内に溜め、ウエハ表
面の凹凸が埋まり平坦となるようにした(同図
(a))。ICチップは、各種素子が形成されているI
C基板と、IC基板1上に1050℃のスチーム雰囲気
で水蒸気酸化により厚さ1μmに形成した第1酸化膜2
と、この第1酸化膜2にコンタクト孔を開口して形成さ
れるAl電極3で構成される。また前記の凹凸はSiO
2 の粉体の粒径程度である。
1A to 1E show a method for manufacturing a surface protective film according to an embodiment of the present invention. FIGS. 1A to 1E are sectional views showing main steps in the order of steps. First, a powder of SiO 2 having a particle size distribution center of 20 nm was placed in isopropyl alcohol to obtain a monodispersed liquid. This dispersion liquid 4 is stored in a polyimide dam (1.5 μm in height) provided on the outer periphery of the wafer 1 mm on which IC chips (not shown) are integrated, so that the irregularities on the wafer surface are buried and flattened (FIG. a)). An IC chip is an IC chip on which various elements are formed.
A first oxide film 2 formed on a C substrate and an IC substrate 1 to a thickness of 1 μm by steam oxidation in a steam atmosphere at 1050 ° C.
And an Al electrode 3 formed by opening a contact hole in the first oxide film 2. In addition, the irregularities are SiO
It is about the particle size of the powder of 2 .

【0013】つぎに真空中で、SiO2 の粉体の軟化点
付近の温度である300℃程度で、30分の焼成を行
い、溶媒を蒸発させると同時にSiO2 粒同士を凝縮・
溶接させ、膜厚1μmのSiO2 粒膜5とする。このS
iO2 粒膜5は、穿孔率の高い誘電体層とすることがで
きる。また、塗布時の膜厚よりも、溶媒が蒸発した分膜
厚が目減りするものの、配線電極上にはSiO2 粒が堆
積し、全体として平坦な面が得られる(同図(b))。
Next, baking is performed in vacuum at about 300 ° C., which is a temperature near the softening point of the SiO 2 powder, for 30 minutes to evaporate the solvent and condense the SiO 2 particles together.
By welding, a SiO 2 grain film 5 having a thickness of 1 μm is obtained. This S
The iO 2 grain film 5 can be a dielectric layer having a high perforation rate. Further, although the thickness of the solvent evaporated is smaller than the thickness at the time of application, SiO 2 particles are deposited on the wiring electrode, and a flat surface is obtained as a whole (FIG. 2B).

【0014】つぎに、この状態で、第2酸化膜6とし
て、プラズマCVD−SiO2 膜を0.1μm堆積させ
て平坦度を高める(同図(c))。その結果、図2に示
すような断面形状が得られ、SiO2 粒膜6は多数のS
iO2 粒子8で構成されるが、第2酸化膜6をその上に
被覆することで、これらの膜を貫通するピンホールなど
の欠陥を無くすことができる。
Next, in this state, a plasma CVD-SiO 2 film is deposited as the second oxide film 6 to a thickness of 0.1 μm to improve the flatness (FIG. 3C). As a result, obtained cross-sectional shape as shown in FIG. 2, SiO 2 Tsubumaku 6 a number of S
Although composed of iO 2 particles 8, by covering the second oxide film 6 thereon, defects such as pinholes penetrating these films can be eliminated.

【0015】つぎに、レジストパターニング、エッチン
グを行いAl電極3上の配線取り出し部分の窓開けを行
った(同図(d))。この場合のエッチングはCF4
2のプラズマエッチングである。エッチングされた側
面Aの上部は緻密なSiO2膜であるが、その下部は厚
いポーラスな層(SiO2 粒堆積層で、誘電率の小さい
誘電体層)であるため、この側面Aを露出させた状態で
は水分の侵入などある。
Next, resist patterning and etching were performed to open a window at a wiring take-out portion on the Al electrode 3 (FIG. 4D). The etching in this case is CF 4 /
It is a plasma etching of O 2. Although the upper part of the etched side A is a dense SiO 2 film, the lower part is a thick porous layer (a SiO 2 grain deposited layer and a dielectric layer having a small dielectric constant). In the wet state, there is intrusion of moisture.

【0016】つぎに、プラズマCVD法で、SiN膜7
を0.5μm堆積し、側面Aをこの膜で保護した後、こ
のAl電極3上のSiN膜7の窓開けを行う(同図
(e))。その後、窓開けされた箇所でAl電極3とS
iN膜7上に形成される図示しない配線とを接続する。
このSiN膜7はSix y Z 膜である。この実施例
では、表面保護膜の構成が、IC基板上の第1酸化膜2
と、SiO 2 粒膜5と、第2酸化膜6と、SiN膜7で
ある。これらの膜全体の等価的な比誘電率は2.0とな
り、低誘電率の表面保護膜が得られる。また、第2酸化
膜4とSiN膜7によって、パッケージを通して、外界
から侵入した不純物イオンによる電気的影響を受けにく
くすることができ、また、コンタクト孔のある箇所のS
iO2 粒膜5の側面Aおよび第2酸化膜6表面が、Si
N膜7の緻密な膜(膜密度が2g/cc以上)で被覆さ
れることにより、耐浸水性、耐腐食性を向上できる。
Next, the SiN film 7 is formed by a plasma CVD method.
0.5 μm, and after protecting the side surface A with this film,
A window is opened in the SiN film 7 on the Al electrode 3 of FIG.
(E)). Then, the Al electrode 3 and S
A wiring (not shown) formed on the iN film 7 is connected.
This SiN film 7 is made of SixNyHZIt is a membrane. This example
Then, the configuration of the surface protection film is the first oxide film 2 on the IC substrate.
And SiO TwoThe grain film 5, the second oxide film 6, and the SiN film 7
is there. The equivalent relative permittivity of these films as a whole is 2.0.
Thus, a surface protective film having a low dielectric constant can be obtained. In addition, the second oxidation
External environment through the package by the film 4 and the SiN film 7
To be electrically affected by impurity ions entering
In addition, the S at the portion where the contact hole is
iOTwoThe side surface A of the grain film 5 and the surface of the second oxide film 6
Covered with a dense film of N film 7 (film density of 2 g / cc or more)
By doing so, it is possible to improve water resistance and corrosion resistance.

【0017】上記のSiN膜7上に形成される図示しな
い配線のさらに上に配線総が形成される場合において
は、図示しない配線上にSiO2 粒膜5、第2酸化膜
6、SiN膜7を積層した上に配線を形成する。
In the case where the entire wiring is formed above the wiring (not shown) formed on the SiN film 7, the SiO 2 grain film 5, the second oxide film 6, and the SiN film 7 are formed on the wiring (not shown). Are formed on top of each other.

【0018】[0018]

【発明の効果】この発明によれば、シリコン表面上に高
穿孔度の酸化膜(低誘電率の誘電体膜:SiO2 粒膜
5)とその上に緻密なSix y z 膜(SiN膜)を
被覆することで、耐浸水性、耐腐食性に優れ、且つ、外
界から侵入した不純物イオンによる電気的影響を受けに
くくするし、耐圧特性などの電気的特性とその信頼性を
向上させることができる。
Effect of the Invention] The present invention, the oxide film of high perforation degree on the silicon surface (dielectric film having a low dielectric constant: SiO 2 Tsubumaku 5) a dense Si x N y H z film thereon ( (SiN film), excellent in water resistance and corrosion resistance, and less likely to be affected by impurity ions invading from the outside world, and improved electrical characteristics such as withstand voltage characteristics and its reliability Can be done.

【図面の簡単な説明】[Brief description of the drawings]

【図1】この発明の一実施例の表面保護膜の製造方法
で、(a)〜(e)は工程順に示した要部工程断面図で
ある。
FIGS. 1A to 1E are cross-sectional views showing a main part of a method of manufacturing a surface protective film according to an embodiment of the present invention, which are shown in the order of steps.

【図2】この発明の表面保護膜の要部断面図FIG. 2 is a sectional view of a main part of the surface protective film of the present invention.

【符号の説明】[Explanation of symbols]

1 IC基板 2 第1酸化膜 3 Al電極 4 分散液 5 SiO2 粒膜 6 第2酸化膜 7 SiN膜 8 SiO2 粒子1 IC substrate 2 first oxide film 3 Al electrode 4 Dispersion 5 SiO 2 Tsubumaku 6 second oxide film 7 SiN film 8 SiO 2 particles

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 FI テーマコート゛(参考) H01L 21/318 H01L 21/318 B 21/768 21/90 K Fターム(参考) 5F033 HH08 JJ01 JJ08 KK01 KK08 QQ12 QQ37 QQ74 QQ85 RR04 RR06 SS15 SS22 TT02 TT07 XX00 XX01 XX18 XX24 5F058 BA07 BA20 BD02 BD04 BD07 BD09 BD13 BF07 BF46 BJ01 BJ02 BJ03 ──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) H01L 21/318 H01L 21/318 B 21/768 21/90 K F Term (Reference) 5F033 HH08 JJ01 JJ08 KK01 KK08 QQ12 QQ37 QQ74 QQ85 RR04 RR06 SS15 SS22 TT02 TT07 XX00 XX01 XX18 XX24 5F058 BA07 BA20 BD02 BD04 BD07 BD09 BD13 BF07 BF46 BJ01 BJ02 BJ03

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】半導体素子が形成された半導体基板と、該
半導体基板上に形成された半導体素子の電極配線部と前
記半導体基板上に第1絶縁膜を介して形成され、且つ、
前記電極配線部を選択的に被覆した多孔質の誘電体膜
と、該誘電体膜上に形成された膜密度が少なくとも2g
/cc以上の緻密な第2絶縁膜とを有することを特徴と
する半導体装置。
A semiconductor substrate on which a semiconductor element is formed, an electrode wiring portion of the semiconductor element formed on the semiconductor substrate, and a first insulating film formed on the semiconductor substrate via a first insulating film;
A porous dielectric film selectively covering the electrode wiring portion, and a film density formed on the dielectric film is at least 2 g.
And a dense second insulating film of at least / cc.
【請求項2】前記多孔質の誘電体膜が、酸化物の粒子で
形成されることを特徴とする請求項1に記載の半導体装
置。
2. The semiconductor device according to claim 1, wherein said porous dielectric film is formed of oxide particles.
【請求項3】前記第2絶縁膜が、酸化シリコン膜、窒化
シリコン膜もしくはそれらを積層した膜のいずれかであ
ることを特徴とする請求項1に記載の半導体装置。
3. The semiconductor device according to claim 1, wherein said second insulating film is one of a silicon oxide film, a silicon nitride film, and a film obtained by laminating them.
【請求項4】半導体素子が形成された半導体基板と、該
半導体基板上に形成された半導体素子の電極配線部とを
保護する半導体装置の表面保護膜の形成方法において、
前記半導体基板上に第1絶縁膜を形成する工程と、該第
1絶縁膜上と前記電極配線部上に誘電体膜を形成する工
程と、前記電極配線部上の前記誘電体膜を選択的に除去
する工程と、前記誘電体膜上に膜密度が少なくとも2g
/cc以上の緻密な第2絶縁膜を形成する工程とを含む
ことを特徴とする半導体装置の製造方法。
4. A method for forming a surface protection film of a semiconductor device for protecting a semiconductor substrate having a semiconductor element formed thereon and an electrode wiring portion of the semiconductor element formed on the semiconductor substrate.
Forming a first insulating film on the semiconductor substrate, forming a dielectric film on the first insulating film and on the electrode wiring portion, selectively forming the dielectric film on the electrode wiring portion; And a film density of at least 2 g on the dielectric film.
Forming a dense second insulating film of at least / cc or more.
【請求項5】前記金属配線部上の前記第2絶縁膜を選択
的に除去する工程と、該除去部に、金属配線膜を形成す
る工程とを含むことを特徴とする請求項4に記載の半導
体装置の製造方法。
5. The method according to claim 4, further comprising the steps of: selectively removing the second insulating film on the metal wiring portion; and forming a metal wiring film on the removed portion. Of manufacturing a semiconductor device.
JP33314799A 1999-11-24 1999-11-24 Semiconductor device and its manufacturing method Pending JP2001156062A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP33314799A JP2001156062A (en) 1999-11-24 1999-11-24 Semiconductor device and its manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP33314799A JP2001156062A (en) 1999-11-24 1999-11-24 Semiconductor device and its manufacturing method

Publications (1)

Publication Number Publication Date
JP2001156062A true JP2001156062A (en) 2001-06-08

Family

ID=18262830

Family Applications (1)

Application Number Title Priority Date Filing Date
JP33314799A Pending JP2001156062A (en) 1999-11-24 1999-11-24 Semiconductor device and its manufacturing method

Country Status (1)

Country Link
JP (1) JP2001156062A (en)

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