JP2001152396A - Semiconductor manufacturing apparatus, and semiconductor manufacturing method - Google Patents

Semiconductor manufacturing apparatus, and semiconductor manufacturing method

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Publication number
JP2001152396A
JP2001152396A JP33383999A JP33383999A JP2001152396A JP 2001152396 A JP2001152396 A JP 2001152396A JP 33383999 A JP33383999 A JP 33383999A JP 33383999 A JP33383999 A JP 33383999A JP 2001152396 A JP2001152396 A JP 2001152396A
Authority
JP
Japan
Prior art keywords
power supply
wafer
semiconductor wafer
contact
outer peripheral
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP33383999A
Other languages
Japanese (ja)
Inventor
Akihiro Sano
彰洋 佐野
Kinya Kobayashi
金也 小林
Shinichi Fukada
晋一 深田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP33383999A priority Critical patent/JP2001152396A/en
Publication of JP2001152396A publication Critical patent/JP2001152396A/en
Pending legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor manufacturing apparatus, and a semiconductor manufacturing method in which the power is supplied from an outer peripheral part of a semiconductor wafer using an electroplating method to form a plating layer on the wafer, and the variance in film thickness caused by non-uniform contact of the semiconductor wafer with a power supply electrode can be reduced. SOLUTION: When the power is supplied onto the semiconductor wafer from the outer peripheral part of the wafer, the power is supplied to the semiconductor wafer 2 using a plurality of power supply electrodes 801-808 as shown in Fig. 1, and the current in the power supply electrodes 801-808 is kept at a preset value by constant current sources 901-908. Even when the contact of a contact surface of the power supply electrodes with the wafer is non-uniform, the current distribution along the peripheral direction of the wafer is kept uniform, and the distribution of the film thickness on the plating layer becomes uniform.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体ウェハへ電
気めっきにより配線を形成する半導体製造装置及び半導
体製造方法に関わり、特に均一なめっき膜を形成可能な
半導体製造装置及び半導体製造方法に関する。
The present invention relates to a semiconductor manufacturing apparatus and a semiconductor manufacturing method for forming wiring on a semiconductor wafer by electroplating, and more particularly to a semiconductor manufacturing apparatus and a semiconductor manufacturing method capable of forming a uniform plating film.

【0002】[0002]

【従来の技術】半導体ウェハ面を被めっき面とし、電気
めっきにより半導体ウェハ上に配線を形成する場合、ウ
ェハ上に堆積しためっき膜厚がウェハ上の部位によりば
らつくと、電気めっき後にめっき膜を化学機械研磨処理
する際、過剰研磨や削れ残りが生じたり、配線抵抗にば
らつきが生じウェハ上の部位により素子特性が異なって
しまう等の不具合が生じる。めっき膜厚を均一とするた
めには、被めっき面に流れ込む電流密度を極力均一とな
るようにする必要がある。半導体ウェハへの給電に適し
た部位はウェハ外周部などごく限られており、通常はウ
ェハ外周部に円環上の給電電極を接触させ給電を行う。
被めっき面である半導体ウェハ面上には、電気めっき前
にスパッタ等により導電性薄膜(シード層)が設けられ
ているが、シード層膜厚は0.1μm程度以下と薄く抵抗
が高いため給電電極と被めっき面の間の接触抵抗が大き
い。また、半導体ウェハへの給電電極からの不純物混入
を防ぐために給電用電極材料が制限されるので、半導体
ウェハとの平坦な接触面の形成が困難な給電電極用材料
を使用しなければならないことが多い。このため、半導
体ウェハへのめっきでは、被めっき面と給電電極の接触
が不均一となりやすい。
2. Description of the Related Art When wiring is formed on a semiconductor wafer by electroplating using a semiconductor wafer surface as a surface to be plated, if the plating film thickness deposited on the wafer varies depending on the portion on the wafer, the plating film is formed after the electroplating. During the chemical mechanical polishing process, there are problems such as excessive polishing and unremoved portions, variation in wiring resistance, and different element characteristics depending on the portion on the wafer. In order to make the plating film thickness uniform, it is necessary to make the current density flowing into the surface to be plated as uniform as possible. A portion suitable for supplying power to the semiconductor wafer is very limited, such as the outer peripheral portion of the wafer. Usually, a power supply electrode on a ring is brought into contact with the outer peripheral portion of the wafer to supply power.
A conductive thin film (seed layer) is provided on the surface of the semiconductor wafer to be plated by sputtering or the like before electroplating, but the thickness of the seed layer is as small as about 0.1 μm or less and the resistance is high. Contact resistance between the substrate and the surface to be plated is large. In addition, since the power supply electrode material is limited in order to prevent impurities from entering the semiconductor wafer from the power supply electrode, it is necessary to use a power supply electrode material in which it is difficult to form a flat contact surface with the semiconductor wafer. Many. For this reason, when plating a semiconductor wafer, the contact between the surface to be plated and the power supply electrode tends to be uneven.

【0003】被めっき面と給電電極の接触が不均一とな
ると、接触の良い部位に電流が流れ易くなるので、ウェ
ハ中心と接触の良い部位を結ぶ方向の膜厚は厚くなり、
接触の悪い部位への方向では逆に膜厚が薄くなる。こう
して接触不均一によって、ウェハの周方向により膜厚が
ばらつく。このような接触不均一による膜厚のばらつき
は、シード層及び給電電極の抵抗が大きいと更に顕著と
なる。
[0003] If the contact between the surface to be plated and the power supply electrode becomes non-uniform, a current easily flows to a portion having good contact, so that the film thickness in the direction connecting the center of the wafer and the portion having good contact increases.
Conversely, the film thickness becomes thinner in the direction toward poor contact. Thus, the film thickness varies in the circumferential direction of the wafer due to the uneven contact. Such variation in film thickness due to non-uniform contact becomes more remarkable when the resistance of the seed layer and the power supply electrode is large.

【0004】めっき膜厚を均一化するために以下のよう
な提案がされている。
The following proposals have been made to make the plating film thickness uniform.

【0005】特開平9−53198号では、複数の給電
電極を用いて給電を行い、給電電極を被めっき面中心を
挟んで対になるように配置する、もしくは外周部上で等
間隔に配置するか、または給電電極を外周部全体に環状
に連続配置し、均一なめっき膜を形成可能としている。
しかし、上記接触不均一な場合に関する対策は施されて
おらず、各給電電極と被めっき面の接触が不均一な場合
には、各給電電極での電流は不均一となり、膜厚はばら
つく。
In Japanese Patent Application Laid-Open No. 9-53198, power is supplied using a plurality of power supply electrodes, and the power supply electrodes are arranged so as to form a pair with the center of the surface to be plated interposed therebetween, or are arranged at equal intervals on the outer peripheral portion. Alternatively, the power supply electrodes are continuously arranged in a ring shape over the entire outer peripheral portion, so that a uniform plating film can be formed.
However, no countermeasures are taken against the case where the contact is non-uniform, and when the contact between each power supply electrode and the surface to be plated is non-uniform, the current at each power supply electrode becomes non-uniform and the film thickness varies.

【0006】特開平10−13089号では、被めっき
表面近傍に電流密度センサー及び複数の電流遮蔽板を設
置し、めっき液から被めっき面に流れる電流分布が一様
となるように遮蔽板穴径をオンライン制御することで、
均一な電気めっきを可能としている。しかし、半導体ウ
ェハ上に形成する膜厚は1〜2μm以下と薄く、かつ成
膜速度が100nm/min以上と高いため、最適な遮
蔽板穴径及び遮蔽板位置を探索し穴径及び位置を変化さ
せている時間内にめっき処理が終了してしまう。また、
電流遮蔽板の開口率、遮蔽板の位置を電流密度の計測結
果に従って自動的に変化させる装置が必要なため装置コ
ストが上昇する。
In Japanese Patent Application Laid-Open No. 10-13089, a current density sensor and a plurality of current shield plates are provided near the surface to be plated, and the hole diameter of the shield plate is adjusted so that the current flowing from the plating solution to the surface to be plated is uniform. By controlling online,
It enables uniform electroplating. However, since the film thickness formed on the semiconductor wafer is as thin as 1 to 2 μm or less, and the film formation rate is as high as 100 nm / min or more, the optimum shield plate hole diameter and shield plate position are searched and the hole diameter and position are changed. The plating process is completed within the time period. Also,
Since a device that automatically changes the aperture ratio of the current shielding plate and the position of the shielding plate according to the measurement result of the current density is required, the cost of the device increases.

【0007】[0007]

【発明が解決しようとする課題】本発明では、電気めっ
きによる半導体ウェハ上への配線形成において、半導体
ウェハ面と半導体ウェハへの給電電極の接触不均一によ
り生じるめっき膜厚のばらつきを少なくするすることが
できる半導体製造装置及び半導体製造方法を提供するこ
とを目的とする。
SUMMARY OF THE INVENTION According to the present invention, in forming wiring on a semiconductor wafer by electroplating, the variation in plating film thickness caused by uneven contact between the semiconductor wafer surface and the power supply electrode on the semiconductor wafer is reduced. It is an object of the present invention to provide a semiconductor manufacturing apparatus and a semiconductor manufacturing method that can perform the method.

【0008】[0008]

【課題を解決するための手段】上記課題を解決するた
め、本発明においては、半導体ウェハ外周部に複数の給
電電極を設け、かつ各給電電極の電流値が設定値となる
ように電流調節装置により調節を行うことで、半導体ウ
ェハ面と給電電極の接触不均一によるめっき膜厚ばらつ
きを少なくすることができる半導体製造装置が提供され
る。さらに、各給電電極とウェハとの接触抵抗の測定を
行い、ウェハを給電電極の接触が均一となるように配置
しなおすことによりより確実なめっきを行うことが可能
となる半導体製造装置が提供される。
In order to solve the above-mentioned problems, in the present invention, a plurality of power supply electrodes are provided on an outer peripheral portion of a semiconductor wafer, and a current adjusting device is provided so that a current value of each power supply electrode becomes a set value. Thus, there is provided a semiconductor manufacturing apparatus capable of reducing variations in plating film thickness due to uneven contact between the semiconductor wafer surface and the power supply electrode. Furthermore, there is provided a semiconductor manufacturing apparatus capable of measuring the contact resistance between each power supply electrode and a wafer, and arranging the wafer so that the contact of the power supply electrode is uniform, thereby performing more reliable plating. You.

【0009】また、電気めっき前にウェハ外周部の給電
電極との接触部分のシード層膜厚を厚くして給電電極と
ウェハの接触均一性を向上させ電気めっきを行うことに
より、均一なめっき膜厚を形成可能な半導体製造方法が
提供される。
In addition, before the electroplating, the seed layer thickness at the contact portion of the outer peripheral portion of the wafer with the power supply electrode is increased to improve the uniformity of contact between the power supply electrode and the wafer, thereby performing the electroplating. A semiconductor manufacturing method capable of forming a thickness is provided.

【0010】[0010]

【発明の実施の形態】図1に本実施例で用いる半導体製
造装置の概略図を示す。本装置は、電気めっきにより半
導体ウェハ上へめっき膜の成膜を行う。装置は、円筒型
の絶縁壁3に囲まれためっき槽5と、絶縁壁3の下口に
設けられたアノード電極1からなり、上口に給電電極固
定具4及び給電電極801〜808が設置されている。
電気めっきを行うとき、半導体ウェハ2は給電電極固定
具4及び給電電極801〜808上に取り付けられる。
定電流電源901〜909により、給電電極801〜8
08を通して半導体ウェハ2外周部に給電が行われ、め
っき膜が成膜される。絶縁壁3は、長さ150mm、内
径180mmの大きさである。めっき槽5はめっき液で
満たされている。円形のアノード電極1の中心にめっき
液入り口6が設置されている。めっき液はめっき液入り
口6、めっき槽5、めっき液出口7と循環し、十分に攪
拌される。図1の装置においての本発明の特徴は、半導
体ウェハ2への給電を複数の給電電極801〜808及
び定電流電源901〜909を用いて行うことである。
FIG. 1 is a schematic diagram of a semiconductor manufacturing apparatus used in this embodiment. This apparatus forms a plating film on a semiconductor wafer by electroplating. The apparatus includes a plating tank 5 surrounded by a cylindrical insulating wall 3 and an anode electrode 1 provided at a lower opening of the insulating wall 3, and a power supply electrode fixture 4 and power supply electrodes 801 to 808 are installed at an upper port. Have been.
When performing electroplating, the semiconductor wafer 2 is mounted on the power supply electrode fixture 4 and the power supply electrodes 801 to 808.
Power supply electrodes 801-8 are supplied by constant current power supplies 901-909.
08, power is supplied to the outer peripheral portion of the semiconductor wafer 2, and a plating film is formed. The insulating wall 3 has a length of 150 mm and an inner diameter of 180 mm. The plating tank 5 is filled with a plating solution. A plating solution inlet 6 is provided at the center of the circular anode electrode 1. The plating solution circulates through the plating solution inlet 6, the plating tank 5, and the plating solution outlet 7, and is sufficiently stirred. A feature of the present invention in the apparatus of FIG. 1 is that power is supplied to the semiconductor wafer 2 using a plurality of power supply electrodes 801 to 808 and constant current power supplies 901 to 909.

【0011】本発明の効果を説明するために、通常の半
導体ウェハへの給電方法と問題点について説明する。通
常の場合、半導体ウェハ2への給電は図2のように行
う。図2は、めっき装置上口側にあるウェハへの給電部
分のみが示されている。半導体ウェハ2への給電は円環
状給電電極8により行われる。
In order to explain the effects of the present invention, a method of supplying power to a normal semiconductor wafer and problems will be described. In a normal case, power is supplied to the semiconductor wafer 2 as shown in FIG. FIG. 2 shows only the power supply portion to the wafer on the upper side of the plating apparatus. The power supply to the semiconductor wafer 2 is performed by the annular power supply electrode 8.

【0012】図3(A)、(B)は、図2の円環状給電電極
8を用いて電気めっきを行い、銅を成膜させた場合のウ
ェハ中心から60mmにおける膜厚のウェハ周方向依存性
の実験結果である。図4(B)では、図4(A)の条件に比
べて、半導体ウェハ2を円環状給電電極8に強く押し付
けてあるので、半導体ウェハ2と円環状給電電極8の接
触均一性が向上している。電気めっきによる銅の成膜条
件は次の通りである。
FIGS. 3 (A) and 3 (B) show the dependence of the film thickness at 60 mm from the center of the wafer on the wafer circumferential direction when copper is formed by electroplating using the annular feeding electrode 8 of FIG. It is an experiment result of sex. In FIG. 4B, the semiconductor wafer 2 is strongly pressed against the annular power supply electrode 8 as compared with the condition of FIG. 4A, so that the contact uniformity between the semiconductor wafer 2 and the annular power supply electrode 8 is improved. ing. The conditions for forming copper by electroplating are as follows.

【0013】半導体ウェハ上には、電気めっき前にあら
かじめスパッタにより銅膜が0.1μm程度堆積されてシ
ード層が形成されている。硫酸銅めっき液を用い、平均
電流密度を100A/m2とした。電気めっきは3.0
min間行い、半導体ウェハ上に銅膜を1μm程度堆積
させる。また、半導体ウェハ2は半径が100mmで、
ウェハ中心から90mmの外側で円環状給電電極と接触
している。
Before the electroplating, a copper film is deposited to a thickness of about 0.1 μm on the semiconductor wafer by sputtering to form a seed layer. The average current density was set to 100 A / m 2 using a copper sulfate plating solution. Electroplating is 3.0
Then, a copper film is deposited on the semiconductor wafer by about 1 μm. The semiconductor wafer 2 has a radius of 100 mm,
It is in contact with the annular power supply electrode 90 mm outside the center of the wafer.

【0014】図3(A)、(B)から、ウェハと給電電極の
接触性が悪いと、膜厚の周方向のばらつきが大きくなる
ことが分かる。膜厚分布はウェハ上に電流密度分布によ
って決まる。すなわち、図2の円環状の給電電極を用い
た場合、ウェハ中心から円環状給電電極とウェハの接触
のよい点を結ぶ方向に電流が集中して膜厚が大きくな
り、接触の悪い方向の膜厚が薄くなる。接触性がよくな
ると膜厚分布は均一に近づく。
From FIGS. 3A and 3B, it can be seen that if the contact between the wafer and the power supply electrode is poor, the variation in the film thickness in the circumferential direction increases. The film thickness distribution is determined by the current density distribution on the wafer. That is, when the annular power supply electrode shown in FIG. 2 is used, current concentrates in a direction connecting the point of good contact between the annular power supply electrode and the wafer from the center of the wafer, and the film thickness increases. The thickness decreases. When the contact property is improved, the film thickness distribution approaches uniformity.

【0015】ウェハと給電電極の接触均一性を向上させ
るために、半導体ウェハを給電電極へ強制的に押し付け
る対策が考えられる。しかしこの方法ではウェハに過度
の応力がかかり、ウェハ上に形成された素子が破壊され
てしまう。そこで、図1で示したように、ウェハ(カソ
ード電極)2への給電を給電電極801〜808のよう
に分割して、各給電電極上の電流値を定電流電源901
〜908により設定値に固定する。これにより、ウェハ
の各周方向に流れる電流を均一とすることが可能とな
り、膜厚のばらつきが少なくなる。各給電電極に流す電
流値は、給電電極を外周部に等間隔で配置した場合に
は、(ウェハに流す平均電流密度×被めっき面の面積)
/給電電極数により決定する。給電電極及び電流調節装
置の数が多いことが望ましい。
In order to improve the uniformity of contact between the wafer and the power supply electrode, a measure for forcibly pressing the semiconductor wafer against the power supply electrode can be considered. However, in this method, excessive stress is applied to the wafer, and elements formed on the wafer are destroyed. Therefore, as shown in FIG. 1, the power supply to the wafer (cathode electrode) 2 is divided like the power supply electrodes 801 to 808, and the current value on each power supply electrode is
The value is fixed to the set value by 90908. Thus, it is possible to make the current flowing in each circumferential direction of the wafer uniform, and to reduce the variation in the film thickness. When the power supply electrodes are arranged at equal intervals in the outer peripheral portion, the current value flowing through each power supply electrode is (average current density flowing through the wafer × area of the surface to be plated).
/ Depends on the number of power supply electrodes. It is desirable that the number of power supply electrodes and current regulating devices be large.

【0016】更に、確実な接触均一性を確保するために
次に手段を発明した。半導体ウェハを給電部に設置する
とき、図4に示すように定電流電源10と電圧計11に
より隣り合う給電電極801〜808間の抵抗を測定す
る。上記抵抗測定から各給電電極とウェハ間の接触抵抗
の高低を知ることができる。接触抵抗の高い部位はウェ
ハに過度な応力が掛からない程度にウェハを給電電極へ
押さえつけ、接触抵抗の低い部位では押さえつけを弱く
し、接触抵抗が一様になるように半導体ウェハの設置を
行う。給電電極とウェハの接触抵抗を一様となること
で、膜厚分布は更に均一になりやすくなる。各給電電極
と半導体ウェハの接触抵抗が直接測定できることが望ま
しい。
Further, the following means have been invented in order to ensure reliable contact uniformity. When the semiconductor wafer is installed on the power supply unit, the resistance between the adjacent power supply electrodes 801 to 808 is measured by the constant current power supply 10 and the voltmeter 11 as shown in FIG. From the resistance measurement, the level of the contact resistance between each power supply electrode and the wafer can be known. The semiconductor wafer is placed in such a manner that the portion having a high contact resistance is pressed against the power supply electrode so that excessive stress is not applied to the wafer, and the portion where the contact resistance is low is weakened so that the contact resistance becomes uniform. By making the contact resistance between the power supply electrode and the wafer uniform, the film thickness distribution tends to be more uniform. It is desirable that the contact resistance between each power supply electrode and the semiconductor wafer can be directly measured.

【0017】小さな径のウェハに電気めっきするときに
は、給電電極のウェハ中心からの距離を短くする必要が
ある。しかし、給電電極にウェハ中心からの距離を可変
とする機構を付加すると、給電電極の固定具が装置本体
へ固定する際に、ぐらつく等のため安定し難い。従っ
て、ウェハと給電電極の接触均一性の確保がさらに難し
くなる。本実施例では、図5に示すように、給電電極固
定具及び給電電極をウェハの径にあったものに取り替え
ることで、小さな径のウェハへの電気めっきを行う。こ
れにより、固定具等のぐらつきによるウェハと給電電極
の接触不均一が更に大きくなっても、電流調節装置によ
り均一な電流分布を得ることができるので、膜厚のばら
つきは小さくなる。
When electroplating a wafer having a small diameter, it is necessary to shorten the distance between the power supply electrode and the center of the wafer. However, if a mechanism for changing the distance from the center of the wafer is added to the power supply electrode, it is difficult to stabilize the power supply electrode fixture because the fixture is unstable when fixed to the apparatus main body. Therefore, it becomes more difficult to ensure uniform contact between the wafer and the power supply electrode. In the present embodiment, as shown in FIG. 5, the power supply electrode fixture and the power supply electrode are replaced with ones that match the diameter of the wafer, thereby performing electroplating on a wafer having a small diameter. Thereby, even if the contact unevenness between the wafer and the power supply electrode due to the wobble of the fixture or the like is further increased, a uniform current distribution can be obtained by the current adjusting device, and the variation in the film thickness is reduced.

【0018】半導体ウェハへの電気めっきにおいては、
ウェハ外周部と給電電極の接触不均一による膜厚分布不
均一が問題となる。この問題を解決する手段の一つとし
て、図6に示す電気めっき法も有効である。図6は半導
体ウェハ断面を見た図である。半導体ウェハ2に堆積し
たシード層13上の給電電極と接する部分121、12
2以外にマスク14をして、スパッタ等により給電部分
に銅膜131、132を成膜させる。これにより、給電
部分の導電膜が特に厚くなり、給電電極とウェハの接触
性はよくなる。
In electroplating a semiconductor wafer,
There is a problem of non-uniform film thickness distribution due to non-uniform contact between the wafer outer peripheral portion and the power supply electrode. As one means for solving this problem, the electroplating method shown in FIG. 6 is also effective. FIG. 6 is a view of a cross section of a semiconductor wafer. Portions 121 and 12 in contact with power supply electrodes on seed layer 13 deposited on semiconductor wafer 2
The copper film 131, 132 is formed on the power supply part by sputtering or the like using the mask 14 other than the mask 2. Thereby, the conductive film in the power supply portion becomes particularly thick, and the contact between the power supply electrode and the wafer is improved.

【0019】[0019]

【発明の効果】本発明によれば、電気めっきにより半導
体ウェハ上にめっき膜を形成する際、ウェハ外周部と給
電電極の接触不均一による膜厚ばらつきがなくなり、均
一なめっき膜を得ることができる。
According to the present invention, when a plating film is formed on a semiconductor wafer by electroplating, there is no variation in film thickness due to uneven contact between the outer peripheral portion of the wafer and the power supply electrode, and a uniform plating film can be obtained. it can.

【図面の簡単な説明】[Brief description of the drawings]

【図1】めっき装置概略図。FIG. 1 is a schematic diagram of a plating apparatus.

【図2】円環状の給電電極を用いためっき装置の給電部
拡大図。
FIG. 2 is an enlarged view of a power supply unit of a plating apparatus using an annular power supply electrode.

【図3】図2の給電電極を用いた場合のウェハ半径方向
に沿った膜厚分布図で、(B)は(A)に比べて、半導体
ウェハを給電電極に強く押しつけている状態を示す図。
3 is a film thickness distribution diagram along a wafer radial direction when the power supply electrode of FIG. 2 is used, and FIG. 3B shows a state in which the semiconductor wafer is strongly pressed against the power supply electrode as compared with FIG. FIG.

【図4】図1のめっき装置における給電電極間の抵抗測
定装置を示す図。
FIG. 4 is a diagram showing a resistance measuring device between power supply electrodes in the plating apparatus of FIG. 1;

【図5】図6で、ウェハ中心から給電電極までの距離を
小さくしためっき装置の給電部拡大図。
FIG. 5 is an enlarged view of a power supply unit of the plating apparatus in FIG. 6 in which a distance from a center of the wafer to a power supply electrode is reduced.

【図6】ウェハ外周部にある給電電極との接触部の膜厚
が厚いシード層形成工程説明図。
FIG. 6 is an explanatory view of a seed layer forming process in which a contact portion with a power supply electrode on the outer peripheral portion of the wafer has a large film thickness.

【符号の説明】[Explanation of symbols]

1…アノード電極、2…半導体ウェハ、3…絶縁壁、4
…給電電極固定具、5…めっき槽、6…めっき液入口、
7…めっき液出口、8…円環状給電電極、801〜80
8…給電電極、9…定電流電源、901〜909…定電
流電源、10…定電流電源、11…電圧計、121・1
22…給電電極と接する部分、13・131・132…
電気めっき前に堆積させる導電性膜、14…マスク。
DESCRIPTION OF SYMBOLS 1 ... Anode electrode, 2 ... Semiconductor wafer, 3 ... Insulating wall, 4
... Power supply electrode fixture, 5 ... Plating tank, 6 ... Plating solution inlet,
7 ... plating solution outlet, 8 ... annular feeding electrode, 801-80
Reference numeral 8: power supply electrode, 9: constant current power supply, 901 to 909: constant current power supply, 10: constant current power supply, 11: voltmeter, 121.1
22 ... parts in contact with the power supply electrodes, 13, 131, 132 ...
Conductive film deposited before electroplating, 14 mask.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 深田 晋一 東京都青梅市新町六丁目16番地の3 株式 会社日立製作所デバイス開発センタ内 Fターム(参考) 4K024 BB12 CB04 CB08 CB26 GA16 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Shinichi Fukada 6-chome, Shinmachi 6-chome, Ome-shi, Tokyo F-term in the Device Development Center, Hitachi, Ltd. 4K024 BB12 CB04 CB08 CB26 GA16

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 半導体ウェハを被めっき面として、半導
体ウェハ外周部からの給電によりめっき膜の形成を行う
半導体製造装置において、複数の給電電極を外周部に設
け、かつ各給電電極上の電流値を調節可能な電流調節装
置による給電により電気めっき膜の形成を行うことを特
徴とする半導体製造装置。
In a semiconductor manufacturing apparatus for forming a plating film by supplying power from an outer peripheral portion of a semiconductor wafer using a semiconductor wafer as a surface to be plated, a plurality of power supply electrodes are provided on an outer peripheral portion, and a current value on each of the power supply electrodes is provided. A semiconductor manufacturing apparatus characterized in that an electroplating film is formed by power supply by a current adjusting device capable of adjusting a current.
【請求項2】 半導体ウェハを被めっき面として、半導
体ウェハ外周部からの給電により電気めっき膜の形成を
行う半導体製造装置において、複数の給電電極を外周部
に設け、各給電電極と半導体ウェハ間の接触抵抗測定装
置を有することを特徴とした半導体製造装置。
2. In a semiconductor manufacturing apparatus for forming an electroplating film by supplying power from an outer peripheral portion of a semiconductor wafer using a semiconductor wafer as a surface to be plated, a plurality of power supply electrodes are provided on an outer peripheral portion. And a contact resistance measuring device.
【請求項3】 半導体ウェハを被めっき面として、半導
体ウェハ外周部からの給電により電気めっき膜の形成を
行う半導体製造装置において、請求項1及び2記載の特
徴を有した半導体製造装置。
3. The semiconductor manufacturing apparatus according to claim 1, wherein the electroplating film is formed by supplying power from an outer peripheral portion of the semiconductor wafer using the semiconductor wafer as a surface to be plated.
【請求項4】 請求項1もしくは2もしくは3記載の半
導体製造装置において、外周部に設けた複数の給電電極
のウェハ中心からの距離を調節可能とする機構を有する
ことを特徴とする半導体製造装置。
4. The semiconductor manufacturing apparatus according to claim 1, further comprising a mechanism for adjusting a distance from a center of the wafer to a plurality of power supply electrodes provided on an outer peripheral portion. .
【請求項5】 半導体ウェハを被めっき面として、半導
体ウェハ外周部からの給電により電気めっき膜の形成を
行う半導体製造方法において、電気めっき前に導電性物
質層を半導体ウェハ上に堆積する際、半導体ウェハ外周
上の給電電極と接する部位において導電性物質層が厚く
なるように堆積を行う半導体製造方法。
5. In a semiconductor manufacturing method in which a semiconductor wafer is used as a surface to be plated and an electroplating film is formed by power supply from an outer peripheral portion of the semiconductor wafer, when a conductive material layer is deposited on the semiconductor wafer before electroplating, A semiconductor manufacturing method in which a conductive material layer is deposited so as to be thick at a portion on a periphery of a semiconductor wafer which is in contact with a power supply electrode.
JP33383999A 1999-11-25 1999-11-25 Semiconductor manufacturing apparatus, and semiconductor manufacturing method Pending JP2001152396A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP33383999A JP2001152396A (en) 1999-11-25 1999-11-25 Semiconductor manufacturing apparatus, and semiconductor manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP33383999A JP2001152396A (en) 1999-11-25 1999-11-25 Semiconductor manufacturing apparatus, and semiconductor manufacturing method

Publications (1)

Publication Number Publication Date
JP2001152396A true JP2001152396A (en) 2001-06-05

Family

ID=18270529

Family Applications (1)

Application Number Title Priority Date Filing Date
JP33383999A Pending JP2001152396A (en) 1999-11-25 1999-11-25 Semiconductor manufacturing apparatus, and semiconductor manufacturing method

Country Status (1)

Country Link
JP (1) JP2001152396A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007177277A (en) * 2005-12-27 2007-07-12 Alps Electric Co Ltd Electroplating apparatus
JP2015200017A (en) * 2014-03-31 2015-11-12 株式会社荏原製作所 Plating apparatus and method of determining electric resistance of electric contact of substrate holder
US9334578B2 (en) 2008-11-18 2016-05-10 Cypress Semiconductor Corporation Electroplating apparatus and method with uniformity improvement
US11037901B2 (en) 2019-01-23 2021-06-15 Toyota Jidosha Kabushiki Kaisha Semiconductor element bonding apparatus and semiconductor element bonding method

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007177277A (en) * 2005-12-27 2007-07-12 Alps Electric Co Ltd Electroplating apparatus
US9334578B2 (en) 2008-11-18 2016-05-10 Cypress Semiconductor Corporation Electroplating apparatus and method with uniformity improvement
JP2015200017A (en) * 2014-03-31 2015-11-12 株式会社荏原製作所 Plating apparatus and method of determining electric resistance of electric contact of substrate holder
US11037901B2 (en) 2019-01-23 2021-06-15 Toyota Jidosha Kabushiki Kaisha Semiconductor element bonding apparatus and semiconductor element bonding method

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