JP2001144709A - Device and method for transmission and recording medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To calculate a delay allowance. SOLUTION: This transmitter reads a DTS showing the decode start time of audio data and video data included in a PES packet A from the packet A (accurately from a prescribed TS packet A constructing the packet A and including a PES header) and detects the time when the packet A is assumed to reach a receiving side. The read DTS is defined as times the packet A is expected to arrive at the receiving side (hereafter limited time tL) (limited time tLa), and the delay allowance tR (delay allowance time tRa) is calculated according to the following expression with the detected time when the packet A is expected to reach the receiving side as a reception completion time tE (reception completion time tEa). Namely, the delay allowance TR is the difference between the time tL and the time tE and shows how earlier the reception is completed before the time tL. Delay allowanceTR =limited time tL-reception completion time tE.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transmitting apparatus, a transmitting method, and a recording medium, and more particularly, to a transmitting apparatus, a transmitting method, and a recording medium that can be remultiplexed.

[0002]

2. Description of the Related Art FIG. 1 shows a configuration example of a conventional satellite digital television broadcasting system 10. This satellite digital television broadcasting system 10 includes a transmitting device 1,
It comprises a transmitting antenna 2, a satellite 3, a receiving antenna 4, a receiving device 5, a receiving antenna 6, and a distribution device 7. The transmission device 1 is a transport stream in which a plurality of programs are multiplexed (hereinafter, abbreviated as TS).
Is transmitted to the satellite 3 via the transmission antenna 2. The receiving device 5 transmits the TS transmitted from the transmitting device 1 to the satellite 3
In addition, the received TS is received via the receiving antenna 4 and the received TS is reproduced to display, for example, an image on the TV (television) receiver 22 (FIG. 3). The distribution device 7
The TS transmitted from the transmitting apparatus 1 is received via the satellite 3 and the receiving antenna 6, and the received TS is re-multiplexed with another TS, for example, to another communication network such as CATV (Cable Television). Redistribute.

FIG. 2 shows a configuration example of the transmission device 1. The N encoding units 11-1 to 11-N (hereinafter, when there is no need to individually distinguish them, simply referred to as the encoding unit 11. The same applies to other devices). Video data or predetermined control data is input. The encoding unit 11 adds T-STD (Transport Str
In order to prevent VBV (Video Buffering Verifier) that simulates each buffer that composes the eam System Target Decoder) from failing, data with no meaning (hereinafter referred to as invalid data) was inserted and invalid data was inserted. This data is converted to MPEG (Moving Picture Experts Grou
p) Compression-encodes and outputs to the multiplexing unit 12 according to the standard of 2.

[0004] The multiplexing unit 12 multiplexes the signal input from each encoding unit 11 to generate a TS, and
Output to The TS generated by the multiplexing unit 12 includes a transport stream packet (hereinafter, referred to as a valid packet) obtained by dividing a PES packet including audio data, video data, or control data constituting a program.
In addition, transport stream packets (hereinafter, referred to as invalid packets) constituting invalid data inserted in the encoding unit 11 are multiplexed. In the following, when it is not necessary to distinguish between a valid packet and an invalid packet, these are collectively referred to as a TS packet.

[0005] The encoding unit 13 receives the TS from the multiplexing unit 12.
In addition, even if noise generated at the time of transmission is superimposed, predetermined encoding is performed on the receiving side (receiving device 5 and distribution device 7) so that the correction can be performed, and output to the satellite uplink unit 14.

[0006] The satellite uplink unit 14 includes an encoding unit 13.
From TS, for example, QPSK (Quadriphase Phase Shift
Keying) modulates and transmits to the satellite 3 via the transmitting antenna 2.

FIG. 3 shows a configuration example of the receiving device 5. The receiving unit 21 receives the TS transmitted from the transmitting device 1 via the receiving antenna 4 and receives the TS.
From the TS, a TS packet constituting a desired program is separated and decoded, and the resulting video data, audio data, and the like are output to the TV receiver 22. The TV receiver 22 displays the video data input from the receiving unit 21 on a display unit (not shown), and outputs audio data from a speaker (not shown).

FIG. 4 shows a configuration example of the distribution device 7. The receiving unit 31 receives and receives the TS transmitted from the transmitting device 1 via the receiving antenna 6.
From the TS, a TS packet constituting a desired program is separated and output to the remultiplexing unit 32.

The re-multiplexing unit 32 multiplexes (re-multiplexes) the TS packet input from the receiving unit 31 and another TS packet separately supplied, for example, stored in a storage medium. Generate a new TS and redistribute it to CATV, etc.

[0010]

By the way, the transmitting device 1
Or, in the distribution device 7, for example, the two
When multiplexing of TSA (FIG. 5 (A)) and TSB (FIG. 5 (B)) is performed, the TS packet A1 of TSA and the TS packet B1 of TSB, and the TS packet A4 of TSA and the TS packet B3 of TSB are As described above, when there is a packet to be multiplexed at the same time, one TS packet (TS packet A1 and TS packet A4) is multiplexed with priority over the other TS packet (TS packet B1 and TS packet B3). Be transformed into As a result, the TS packet B1 and the TS packet B3 are multiplexed later than the time to be multiplexed, and the TSA and the TSB are multiplexed.
Are multiplexed in the generated TSAB (FIG. 5 (C)).
That delay occurs.

[0011] Therefore, an encoding buffer provided in a transmitting device (for example, transmitting device 1 or distribution device 7) for transmitting a TS in which a delay has occurred as described above and a receiving device (receiving device) for receiving the encoding buffer. 5 or the distribution device 7) is provided with a margin corresponding to the magnitude of the delay so as not to fail due to the generated delay.

TSA has a fixed (fixed) bit rate because TS packet A has a period TA and TSB has a TS packet B arranged with a period TB.
For example, as in TSA of FIG. 6A and TSB of FIG. 6B, the TS packet A and the TS packet B are not arranged periodically, and their bit rates are not fixed (variable). In some cases, the TS packet A or the TS packet B may be arranged continuously, and as a result, they are multiplexed, so that the bit rate is fixed (see FIG. 5C). Large delays occur. In the example of FIG. 6, a delay corresponding to three TS packets occurs in the TS packet B3.

As described above, as the magnitude of the generated delay increases, a larger margin is required for the decoding buffer on the transmitting side and the encoding buffer on the receiving side. However, an increase in the size of the margin portion means that the actually used capacities of the encode buffer and the decode buffer are correspondingly reduced, and as a result, the coding efficiency is reduced.
That is, in the prior art, in particular, the variable bit rate
When multiplexing a TS, a large delay occurs in the generated TS. As a result, a large margin is required for the buffers on the encoding side and the decoding side, and there is a problem that the encoding efficiency is reduced.

The present invention has been made in view of such a situation, and it is an object of the present invention to enable multiplexing without causing a large delay.

[0015]

According to a first aspect of the present invention, there is provided a transmitting apparatus, comprising: detecting means for detecting a receiving completion time at which a data stream arrives at a receiving apparatus; , And associating means for associating the subtraction result with the data stream.
Transmitting means for transmitting the data stream associated by the associating means.

The data stream is PES packet data constituting a transport stream conforming to the MPEG2 standard, the reception completion time is the time when the last data of the PES packet data arrives at the receiving device, and the constraint time is DTS.
Alternatively, it can be the time indicated by the PTS.

According to a third aspect of the present invention, there is provided a transmission method, comprising: a detection step of detecting a reception completion time at which a data stream arrives at a receiving device; and a reception completion time detected by the detection step from a restriction time. It is characterized by including an associating step of associating the result with the data stream, and a transmitting step of transmitting the data stream associated with the processing of the associating step.

According to a fourth aspect of the present invention, in the recording medium, a detection step of detecting a reception completion time at which the data stream arrives at the receiving device, and a reception completion time detected by the detection step are subtracted from the constraint time, and the subtraction is performed. It is characterized by including an associating step of associating the result with the data stream, and a transmitting step of transmitting the data stream associated with the processing of the associating step.

In the transmitting apparatus according to the first aspect, the transmitting method according to the third aspect, and the recording medium according to the fourth aspect, the reception completion time at which the data stream arrives at the receiving apparatus is detected, and the restriction time is set. , The detected reception completion time is subtracted, the subtraction result is associated with the data stream, and the associated data stream is transmitted.

According to a fifth aspect of the present invention, the data stream arrives at the receiving apparatus from a restriction time at which the data stream is required to arrive at the receiving apparatus together with the data stream composed of a plurality of packets. Input means for inputting the delay margin time from which the reception completion time has been subtracted, and, based on the delay margin time input by the input means, change the arrangement of packets constituting the data stream so as to increase the delay margin time. And changing means.

The changing means changes the arrangement of the packets constituting the data stream so as to increase the delay time based on the restriction of the data stream compression method together with the delay time input by the input means. Can be.

[0022] According to the transmission method of the present invention, the data stream arrives at the receiving device from the restriction time at which the data stream is required to arrive at the receiving device together with the data stream composed of a plurality of packets. An input step of inputting the delay margin time from which the reception completion time has been subtracted, and, based on the delay margin time input in the processing of the input step, the arrangement of the packets constituting the data stream is increased so that the delay margin time increases. And a changing step of changing.

According to the recording medium of the present invention, the data stream arrives at the receiving device from the restriction time at which the data stream is required to arrive at the receiving device together with the data stream composed of a plurality of packets. An input step of inputting the delay margin time from which the reception completion time has been subtracted, and, based on the delay margin time input in the processing of the input step, the arrangement of the packets constituting the data stream is increased so that the delay margin time increases. And a changing step of changing.

In the transmitting apparatus according to the fifth aspect, the transmitting method according to the seventh aspect, and the recording medium according to the eighth aspect, the data stream including the data stream including a plurality of packets is transmitted to the receiving apparatus. A delay time obtained by subtracting the reception completion time at which the data stream arrives at the receiving device from the constraint time required to arrive is input, and the delay time increases based on the input delay time. As described above, the arrangement of the packets constituting the data stream is changed.

[0025]

FIG. 7 shows a configuration example of a satellite digital television broadcasting system 50 to which the present invention is applied. In this system, instead of the transmitting device 1 of FIG.
A transmission device 51 is provided.

FIG. 8 shows a configuration example of the transmission device 51. This transmitting device includes the multiplexing unit 1 of the transmitting device 1 of FIG.
A data conversion unit 52 is provided between the encoding unit 2 and the encoding unit 13.

The data converter 52 receives the data from the multiplexer 12
Detects the amount of delay that occurs on the TS and analyzes the T-STD, and based on the detected amount of delay and the analysis result of the T-STD, replaces the input TS packet and Is reduced and output to the encoding unit 13.

FIG. 9 shows an example of the configuration of the data converter 52. The TS from the multiplexing unit 12 is calculated by the spare time calculation unit 61.
Is input to The spare time calculation unit 61 calculates the input TS
The delay margin time TR (described later) is calculated for each PES packet, and the calculation result is output to the packet switching unit 62 in association with the TS packet.

The packet switching section 62 replaces the TS packet input from the margin time calculation section 61 based on an instruction from the control section 63 and outputs the packet to the encoding section 13.

The T-STD analysis section 63 analyzes the state of each buffer constituting the T-STD, and outputs an analysis result to the control section 63.

The control unit 63 determines whether or not to perform packet replacement based on the delay margin time TR from the margin time calculation unit 61 and the analysis result of the T-STD from the T-STD analysis unit 63. TS to be swapped if swapped
The packet is determined, and the packet switching unit 62 is controlled based on the determination result.

FIG. 10 shows the configuration of the margin time detecting section 61. Prior to the description of this configuration, the spare time detecting unit 6
The calculation method of the delay allowance time TR in FIG.

For example, when the PES packet A shown in FIG. 11A is input to the data conversion unit 52 (the spare time calculation unit 61), the PES packet A is formed from the PES packet A (more precisely, the PES packet A Predetermined TS packet A including PES header
), The DTS indicating the decoding start time of the audio data and the video data included in the PES packet A is read, and the time at which the PES packet A is assumed to arrive at the receiving side is detected.

The read DTS is the time at which the PES packet A must arrive at the receiving side (hereinafter, the constraint time tL) (the constraint time tLa), and the detected PES packet A
The time at which the packet A is assumed to arrive at the receiving side is defined as a reception completion time tE (reception completion time tEa) by using the equation (1).
, The delay margin time tR (delay margin time tRa) is calculated. That is, the delay margin time TR is a difference between the constraint time tL and the reception completion time tE, and indicates how long before the constraint time tL the reception has been completed.

Delay allowance time TR = constraint time tL−reception completion time tE (1) Note that a TS conforming to the MPEG2 standard has a PTS (PTS) indicating a start time of display processing of data included in a PES packet. Prese
ntation Time Stamp), but usually PTS
And DTS are shared, so in this example, D
Let TS be the constraint time tL.

When a PES packet B including audio data and video data of another program is input, the
The DTS indicating the decoding start time of the ES packet B is defined as a delay margin time tLb, the time at which the PES packet B is assumed to be received at the receiving side is defined as a reception completion time tEb, and the delay margin is calculated according to equation (1). The time TRb is calculated.

As shown in FIG. 12, even when a multiplexed PES packet A and PES packet B are input to data converter 52, constraint time tL and reception completion time tE are respectively determined. , The delay margin time TR is obtained. In this case, the delay margin time TR
Details of the calculation method will be described later.

Returning to FIG. 10, the configuration of the spare time calculating section 61 will be described.

The PSI analyzer 71 converts a TS packet input from the multiplexer 12 into a PAT (Program Association Tab).
le) and PSI (Program Map Table)
program time reference value required for decoding a PES packet while analyzing a TS packet (hereinafter, referred to as a PSI packet) including a PTS (Program Specific Information).
A PID of a TS packet having a Clock Reference (hereinafter, referred to as a PCR packet) is detected and output to the PCR reproducing unit 72.

The PCR reproducing section 72 detects a TS packet (PCR packet) having a PID input from the PSI analysis section 71 from the TS packet input from the multiplexing section 12, and detects the PC packet.
While reading R, a clock is generated by a built-in PLL circuit based on the read PCR, and the generated clock is output to the reception completion time calculation unit 75 and the control unit 63.

The TS header analyzing unit 73 analyzes the header of the TS packet input from the multiplexing unit 12, and as shown in FIG. 13, the payload unit start indicator of the header.
Is set to "1", and a flag (hereinafter referred to as a PES header flag) indicating that the TS packet has been detected is sent to the PES header analysis unit 74.
Output to In the case of a TS conforming to the MPEG2 standard, the payload unit start indicator of the TS packet header is set to “1”.
Is set, the TS packet includes a PES header as shown in FIG. In the PES header,
For example, the length of the PES packet (PES_packet_length
(16 bits), DTS, PTS, and the like. The TS packet including the PES header is arranged at the head of the PES packet.

The TS header analysis unit 73 also reads the pid value of the header of each TS packet, and outputs a TS packet flag corresponding to each pid value (each PES packet) to the reception completion time calculation unit 75.

The PES header analysis unit 74 is a TS packet from the multiplexing unit 12 specified by the PES header flag from the TS header analysis unit 73, that is, a TS packet including a PES header.
From the PES header of the packet, the length and DT of the PES packet
It reads S, outputs the read PES packet length to the reception completion time calculation unit 75, and outputs the read DTS to the margin time calculation unit.

The reception completion time calculation unit 75 includes the PCR reproduction unit 7
Clock input from 2 and PES header analysis unit 74
The reception completion time tE is calculated using the PES packet length input from the PES, and the calculation result is output to the margin time calculation unit 76.

The margin time calculation unit 76 sets the DTS from the PES header analysis unit 74 as the constraint time tL,
And the reception completion time tE from the reception completion time calculation unit 75, and calculates a delay allowance time TR, which is output to the control unit 63.

The multiplexing section 12 is stored in the TS packet memory 77.
From the TS, and the TS packet memory 71 stores the TS
Is temporarily held, and the TS is output to the packet switching unit 62 in accordance with the time required for the processing in the PSI analysis unit 71 to the spare time calculation unit 76.

Next, the PES packets A and P shown in FIG.
PES when TS multiplexed with ES packet B is input
The processing procedure of the reception completion time calculation unit 75 when calculating the reception completion time tEa of the packet A will be described with reference to the flowchart in FIG.

In step S 1, the reception completion time calculation unit 75 sends the PES_pac of the PES header contained in the predetermined TS packet A of the PES packet A from the PES header analysis unit 74.
Receives ket_length and stores it in memory X.

In step S2, the reception completion time calculation unit 75 sets the PES_packet_length received in step S1.
Is determined to be "0", and the value is determined to be "0".
If it is determined that it is not, the process proceeds to step S3. For example, when the data length cannot be indicated by 16 bits, such as a PES packet constituting video data,
As shown in FIG. 16, the PES_packet_length has "
0 "is set.

In step S3, the reception completion time calculation unit 75 waits until the TS packet flag corresponding to the PES packet A is input from the TS header analysis unit 73. When the TS packet flag is input, , PES
When the TS packet constituting the packet A is input, the process proceeds to step S4, in which the length of the TS packet (188 bytes) is subtracted from the value of the memory X (the value of PES_packet_length) stored in step S1. Update with the result of the subtraction. In addition, the reception completion time calculation unit 75 stores the count value of the clock from the PCR reproduction unit 72 at that time.

In step S5, the reception completion time calculation section 75 determines whether or not the result of the subtraction in step S4 is a value 0.
3 and the subsequent processing is executed. That is, until the result of the subtraction in step S4 becomes a value 0, step S3
Steps S5 to S5 are repeatedly executed.

If it is determined in step S5 that the result of the subtraction in step S4 is 0, the process proceeds to step S6.
The reception completion time calculation unit 75 calculates the transmission time on the stream from the count value stored in step S4, and outputs the transmission time to the margin time calculation unit 76. That is, the time calculated here is the reception completion time tEa.

On the other hand, in step S2, PES_packet_lengt
If it is determined that the value of h is “0”, step S7
The reception completion time calculation unit 75 proceeds to the TS header analysis unit 7
From 3, the process waits until a TS packet flag corresponding to the PES packet A is input. When the TS packet flag is input, the process proceeds to step S 8.

In step S8, the reception completion time calculation section 75 determines whether or not the PES header flag has been input from the PES header analysis section 74, and determines that the PES header flag has not been input, that is, Step S7
If the TS packet corresponding to the input TS packet flag is not the first TS packet of the PES packet, the process proceeds to step S9.

In step S9, the reception completion time calculation section 75 stores the count value of the clock input from the PCR reproduction section 73 at this time, returns to step S7, and executes the subsequent processing.

If it is determined in step S8 that the PES header flag has been input, the process proceeds to step S10, where the reception completion time calculation unit 75 determines the time on the transmission frame based on the clock value previously stored in step S9. Is calculated and output to the spare time calculation unit 76. That is,
The time calculated here is the reception completion time tEa.

When the reception completion time tEa is calculated in step S6 or step S10, the process ends.

FIG. 17 shows a delay margin time TR for each PES packet of a TS transmitted by CS digital television broadcasting. In this example, the delay margin time of the 83rd PES packet is 0.052 seconds, which is the minimum. In this case, if the generated delay is 0.052 seconds or less, the 83rd PES packet is received by the constraint time tL. The side can arrive and this TS is decoded properly.

FIG. 18 shows a configuration example of the packet switching unit 62 (FIG. 9). Packet switching unit 62
Are two FIFOs 81-1 and 81-2, and 4
It is composed of two switches 82-1 to 82-4.

One end of the switch 82-1 is always connected to the spare time calculation unit 61 (TS packet memory 77 (FIG. 10)), and one end of the switch 82-4 is connected to the encoding unit 13
Always connected to One ends of the switch 82-2 and the switch 82-3 are always connected to each other.

Switches 82-1 to 82-4
For example, as shown in FIG. 18, the switch 82-1 is connected to the FIFO 81-1 and the switch 82-2 is connected to the FI by a switching process based on a command from the control unit 63 (FIG. 9).
FO 81-2, switch 82-3, FIFO 81-1,
The switch 82-4 is connected to the FIFO 81-2 (hereinafter, such a connection state of each switch is referred to as a state 1). In this case, the TS packet input from the margin time calculation unit 61 via the switch 82-1 is
2-1, FIFO 81-1, switch 82-3, switch 8
The data is output to the encoding unit 13 via the 2-2, the FIFO 81-2, and the switch 82-4.

The switch 82-1 is connected to the FIFO 81-2.
The switch 82-2 is connected to the FIFO 81-1 by the switch 8
2-3 is in the FIFO 81-2 and the switch 82-4 is
It is also connected to the FIFO 81-1 (hereinafter, such a connection state of each switch is referred to as state 2). In this case, the TS packet input from the margin time calculation unit 61 via the switch 82-1 is transmitted to the switch 82-1, the FIFO 81-2, the switch 82-3, the switch 82-2, the FIFO 81-1 and the switch 82-1. -4 to the encoding unit 13.

Next, the operation of the packet switching section 62 will be described by taking as an example a case where TS packets 1 to 13 shown in FIG. Note that the connection state of the switches 82-1 to 82-4 is an initial state as shown in FIG.
State 1 shown in FIG. In addition, FIFO 81-1 and FIFO 81-1
81-2 does not hold any TS packet (it is assumed to be empty).

In such a state, the TS packet 1 shown in FIG.
When -1 is input, the FIFO 81-1 holds the TS packet 1. In this case, the FIFO 81-1 does not output anything.

Next, when the TS packet 2 is input via the switch 82-1, the FIFO 81-1 holds the TS packet 2 and outputs the TS packet 1 held earlier (FIG. 19). (B)). Output from FIFO 81-1
The TS packet 1 includes the switch 82-3 and the switch 82
-2, and is input to the FIFO 81-2. FIFO81-
2 holds the input TS packet 1. in this case,
The FIFO 81-2 does not output anything.

Next, when the TS packet 3 is input to the FIFO 81-1, the FIFO 81-1 holds it and
The previously held TS packet 2 is output. FIFO81-
The TS packet 2 output from 1 is input to the FIFO 81-2. The FIFO 81-2 holds the TS packet 2 and outputs the TS packet 1 held earlier (FIG. 1).
9 (C)). TS packet 1 output from FIFO 81-2
Is output to the encoding unit 13 via the switch 82-4 (FIG. 19D).

As described above, when the connection state of the switches 82-1 to 82-4 is state 1, the input TS
The packet is sequentially output to the encoding unit 13 via the switch 82-1, the FIFO 81-1, the switch 82-3, the switch 82-2, the FIFO 81-2, and the switch 82-4.

Next, the FIFO 81-1 outputs the TS packet 6 (FIG. 19 (B)).
Is held), and after the FIFO 81-2 outputs the TS packet 5 (FIG. 19C) (the FIFO 81-2 is
When the TS packet 6 is held), the connection state is state 1
The description will be continued assuming that the state has been changed to state 2.

In this state, when the TS packet 8 is input to the packet switching unit 62, this TS packet
The packet 8 is transmitted to the FIFO 81- via the switch 82-1.
2 is input. The FIFO 81-2 holds the TS packet 8 and outputs the held TS packet 6 (FIG. 19C). The TS packet 6 output from the FIFO 81-2 is input to the FIFO 81-1 via the switch 82-3 and the switch 82-2. The FIFO 81-1 holds the input TS packet 6 and outputs the held TS packet 7 (FIG. 19B). FIFO81
-1 output from the switch 82-4.
Are output to the encoding unit 13. (FIG. 19D).

Next, when the TS packet 9 is input to the FIFO 81-2, the FIFO 81-2 holds the input TS packet 9 and also transfers the held TS packet 8 to the FIFO 8-2.
Output to 1-1. The FIFO 81-1 holds the TS packet 8 from the FIFO 81-2 and outputs the held TS packet 6. The TS packet 6 output from the FIFO 81-1 is output to the encoding unit 13 via the switch 82-4. That is, thereby, the TS packet 6 and the TS packet 7 are exchanged (FIG. 19D).

As described above, the exchange of TS packets is performed.

FIG. 20 shows another example of the configuration of the packet switching unit 62.

The cross-type switch 91 comprises three FIFOs 81-1 to 81-3 and a crossbar switch 91.
The crossbar type switch 91 has 16 switches (i
(= 1, 2, 3, 4), j (= 1, 2, 3, 4)).

Next, the operation will be described. For example, the crossbar switch 91 is a switch (1,
4) When the switches (2, 3), (3, 2), and (4, 1) are turned on (the switches shown shaded in FIG. 20 are turned on) ), The TS packet input from the spare time calculation unit 61 is input to the FIFO 81-1 via the switch (1, 4), and the TS packet output from the FIFO 81-1 is input to the switch (2, 3). ) Is input to the FIFO 81-2.

The TS packet output from the FIFO 81-2 is input to the FIFO 81-3 via the switch (3, 2), and the TS packet output from the FIFO 81-3 is output via the switch (4, 1). And output to the encoding unit 13.

Therefore, the switch (i, j) shown in FIG.
21 is changed to the connection state shown in FIG. 21, the TS packet output from the FIFO 81-1 is input to the FIFO 81-3 via the switch (2, 2),
The TS packet output from 81-2 is the switch (3,
The data is input to the FIFO 81-1 via 4). That is,
FIFO 81-1 and FIFO 8 when the connection state is changed
The TS packet held in 1-2 is replaced.
The TS packet output from the FIFO 81-3 is sent to the encoding unit 13 via the switch (4, 1), as in the case of FIG.
Is output to

Also, from the connection state shown in FIG.
When the connection state is changed to the connection state shown in (1), the TS packet output from the FIFO 81-1 is output to the encoding unit 13 and
The TS packet output from 81-2 is input to FIFO 81-1 and the TS packet output from FIFO 81-3 is
81-2. That is, in this example, when the connection state is changed, the FIFO 81-1 and the FIFO 81-
The TS packet held in No. 3 is replaced.

When using the crossbar switch 91 to exchange TS packets, as shown in FIG. 23, it is necessary to exchange TS packets N TS packets ahead on the time axis. In some cases, as shown in FIG. 24, (N + 1) FIFOs 81-1 through FIFO 81-
(N + 1) and switches (N + 2, N + 2) are required.

Next, the operation of the control section 63 when controlling the packet switching section 62 will be described with reference to the flowcharts of FIGS. 25 and 26. First, the outline thereof will be described, and then FIG. 27 and FIG. This will be specifically described with reference to the TS packet sequence shown in FIG.

In step S21, the control section 63
The value 0 is initially set in the counter k and the memory A.

At step S22, the control unit 63
The value of the counter k is incremented by 1 and step S
23, the spare time calculation unit 61 (TS packet memory 77)
Is output to the packet switching unit 62.

Next, in step S24, the control unit 6
3 refers to the header of the TS packet input to the packet switching unit 62 via the packet switching unit 62,
It is determined whether or not the TS packet is a TS packet of a PES packet to be replaced with a TS packet. If it is determined that the TS packet is a TS packet of the PES packet, the process proceeds to step S25. Meanwhile, the TES of the PES packet
If it is determined that the packet is not an S packet, for example, if it is an invalid packet, the process returns to step S22.

In step S25, the control unit 63
By referring to the payload unit start indicator in the header of the TS packet, it is determined whether or not the TS packet input to the packet switching unit 62 is the first TS packet (TS packet including the PES header) of the PES packet. If it is determined that this is the first TS packet of
Proceed to 6.

Next, in step S26, the control unit 6
3 increments the value of the memory A by one. In step S 27, prior to the head TS packet of the PES packet being input to the packet switching unit 62, the control unit 63 uses the delay margin time TR supplied from the margin time calculation unit 61 to determine The time TRC is subtracted, and in step S28, the number M of TS packets that can be transmitted based on the subtraction result (time) is calculated.

In step S29, the control unit 63
The value of the counter k is set in the memory B, and the process returns to step S22.

In step S25, the T of the beginning of the PES packet
If it is determined that the packet is not an S packet, step S30
The control unit 63 determines whether or not the result of the subtraction in step S27 (= delay margin time TR−reference time TRC) is a negative value. Proceeding to S31, a replacement TS packet is determined. Details of the replacement TS packet determination processing are shown in the flowchart of FIG.

In step S41, the control section 63
The number M of TS packets calculated in step S28 is subtracted from the value of the counter k, and the result of the subtraction is set in the memory C.
Then, the value of the memory B is set in the memory D.

Next, in step S42, the control unit 6
3 judges whether the value of the memory B is smaller than the value of the memory C, and when it is judged that the value is not smaller (larger), the process proceeds to step S43, and the value of the memory D is incremented by one.

In step S44, the control section 63
It is determined whether or not the value of the memory D is smaller than the value of the counter k. If it is determined that the value is not smaller (larger), the process proceeds to step S45, and the value of the counter k is set in the memory A.
That is, in this case, when the value of the counter k is equal to the value of the memory A, the TS input to the packet
When the value of the packet and the value of the counter k become the current value, the TS packet input to the packet switching unit 62 is determined as the TS packet to be replaced.

If it is determined in step S44 that the value of the memory D is smaller than the value of the counter k, the process proceeds to step S46.
When the value of the counter k is equal to the value of the memory D, the control unit 63 inputs the value to the packet switching unit 62.
Judge whether the TS packet is an invalid packet,
If it is determined that the TS packet is an invalid packet, the process proceeds to step S47, and the value of the memory D is set in the memory A. If it is determined in step S46 that the packet is not an invalid packet, the process returns to step S43.

If it is determined in step S42 that the value of the memory B is smaller than the value of the memory C, the process proceeds to step S48, and when the value of the counter k is equal to the value of the memory C, the control unit 63 TS entered in
Determines whether the packet is an invalid packet and determines the TS
If it is determined that the packet is an invalid packet, the process proceeds to step S49, and the value of the memory C is set in the memory A.

In step S48, when the value of the counter k is equal to the value of the memory C, if it is determined that the TS packet input to the packet switching unit 62 is not an invalid packet, the process proceeds to step S50, where the control unit 63 Decrements the value of the memory C by 1 and increments the value of the memory D by 1, and then returns to step S42.

After the processing in step S45, step S47, or step S49, step S32 in FIG.
When the value of the counter k reaches the current value, the control unit 63 determines whether the TS input to the packet
When the value of the packet and the value of the counter k are equal to the value of the memory A, the order of the TS packets input to the packet switching unit 62 is switched.

In step S33, the control unit 63
The value of the memory A is set in the memory B, and the process returns to the step S22.

Next, the above-described processing will be described in detail by taking, as an example, a case where the TS packets of the TS packet sequence in FIG. 27A are stored in the TS packet memory 77 of the margin time calculation unit 61. The TS packets 1, 2, 3, 6, 8, 9, 11, 12, and 13 in the TS packet sequence in FIG.
T of PES packet A where TS packet exchange is performed this time
This is an S packet. The TS packet 1 is a TS packet including a PES header, that is, the first TS packet of the PES packet A. The TS packets 5, 7, and 10 are invalid packets.

In step S21, a counter k = 0 and a memory A = 0 are initialized.

In step S22, the value of the counter k is incremented by 1, and the TS packet 1 (FIG. 27A)
From the spare time calculation unit 61 to the packet exchange unit 62
Is input to

At step S24, the TS packet 1
It is determined that the packet is the TS packet of the packet A, and in step S25, it is determined that the packet is the first TS packet of the PES packet A.
Is incremented by one, and the memory A = 1.

In step S27, the reference time TRC is subtracted from the delay margin time TR supplied to the control unit 63 prior to the TS packet 1 being input to the packet switching unit 62. In step S28, the result of the subtraction is obtained. , The number M of TS packets is calculated. In this example, the number of TS packets M
Is M = 2, as shown in FIG.

In step S29, the counter k = 1 is set in the memory B, and thereafter, the process returns to step S22, where the counter k = 1 is incremented by 1 to make the counter k = 2. TS packet 2
Is input from the spare time calculation unit 61 to the packet exchange unit 62.

Next, the processing after step S24 when the counter k is set to 2 will be described. Note that the counter k = 1
FIG. 27 shows the respective values of the memories A to D set in this processing when k = 8 (when TS packets 1 to 8 are input).

At step S24, the TS packet 2
It is determined that the packet is the TS packet of the packet A, and it is determined in step S25 that it is not the first TS packet of the PES packet A, and the process proceeds to step S30.

In step S30, it is determined whether or not the subtraction result of the delay margin time TR-reference time TRC is a negative value. In the case of this example, as shown in FIG. 27A, the reference time TRCx is longer than the delay margin time TRx, and the subtraction result is a negative value. That is, in this case, the process proceeds to step S31, and the TS packet to be replaced is determined.

At step S41, the counter k = 2,
The number M = 2 is subtracted, the subtraction result = 0 is input to the memory C, and the memory B = 1 is set to the memory D.

At step S42, it is determined that memory B (= 1)> memory C (= 0), and at step S43, memory D = 1 is incremented by 1 and memory D = 2.

In step S44, it is determined that memory D (= 2) = counter k (= 2), and the flow advances to step S45.
The counter k = 2 is set in the memory A.

Thereafter, the flow advances to step S32, and when the counter k = 2, the TS packet 2 input to the packet exchange section 62 and the value of the counter k are stored in the memory A = 2
, The input TS packet 2 is replaced. That is, in this case, the arrangement of the TS packets 2 is not changed because the exchanges between themselves are performed.

In step S33, the memory A = 2 is set in the memory B, and thereafter, the process returns to step S22, where the counter k = 2 is incremented by 1, and the counter k =
In step S23, the next TS packet 3 is input.

Next, the processing after step S24 when the TS packet 3 is input (when the counter k = 3) will be described.

At step S24, the TS packet 3
It is determined that the packet is the TS packet of the packet A, and in step S25, it is determined that the packet is not the first TS packet of the PES packet A.
It is determined that the subtraction result at step 7 is a negative value, and at step S31, the TS packet to be replaced is determined.

In step S41, from counter k = 3,
The value M = 2 is subtracted, the subtraction result = 1 is input to the memory C, and the memory B = 2 is set to the memory D.

At step S42, it is determined that memory B (= 2)> memory C (= 1), and at step S43, memory D = 2 is incremented by 1 and memory D = 3.

In step S44, it is determined that memory D (= 3) = counter k (= 3), and the flow advances to step S45.
The counter k = 3 is set in the memory A.

Thereafter, the process proceeds to step S32, where when the counter k = 3, the TS packet 3 input to the packet switching unit 62 and when the counter k value becomes 3 (= memory A), the input The replaced TS packet 3 is replaced. That is, also in this case, the arrangement of the TS packets 3 is not changed because the exchanges between themselves are performed.

In step S33, the memory A = 3 is set in the memory B, and thereafter, the process returns to step S22, where the counter k = 3 is incremented by 1, and the counter k =
In step S23, the next TS packet 4 is input.

When the TS packet 4 is inputted (when the counter k = 4), the processing after step S24 is the same as the case where the TS packet 2 or the TS packet 3 is inputted, and therefore the description thereof is omitted. By this processing, 4 is stored in the memory A (step S45) and 4 is stored in the memory B.
(Step S33), 2 is stored in the memory C (Step S4
1), and 4 (step S43) is set in the memory D.

Next, the processing after step S24 when the TS packet 5 is input will be described. In this case, since the TS packet 5 is an invalid packet in step S24, the TS It is determined that the packet is not a packet, the process returns to step S22, the counter k = 5 is incremented by 1, the counter k is set to 6, and in step S23, the next TS packet 6 is replaced by the packet switching unit 6
2 is input. That is, in this example, the memories A to D are not updated.

Next, the processing after step S24 when the TS packet 6 is input (when the counter k = 6) will be described.

In step S24, the TS packet 6
It is determined that the packet is the TS packet of the packet A, and in step S25, it is determined that the packet is not the first TS packet of the PES packet A, and the process proceeds to step S30 and proceeds to step S2.
7, it is determined that the subtraction result is a negative value, and step S
At 31, a TS packet to be replaced is determined.

That is, in step S41, the counter k
= 6, the value M = 2 is subtracted, the subtraction result = 4 is set in the memory C, and the memory B = 4 is set in the memory D.

At step S42, it is determined that memory B (= 4) = memory C (= 4), and at step S43, memory D = 4 is incremented by 1 and memory D = 5.

In step S44, it is determined that memory D (= 5) <counter k (= 6). In step S46, when the value of counter k is memory D = 5, the value is input to packet switching unit 62. The determined TS packet 5 is determined to be an invalid packet, and in step S47, the memory D = 5
Is set in the memory A, and the process proceeds to step S32.

In step S32, when the counter k = 6, the TS packet 6 input to the packet switching unit 62 and when the value of the counter k reaches 5 (= memory A), the packet switching unit 62 Are switched as shown in FIG. 25 (B).

Thereafter, the process returns to step S22, where the counter k = 6 is incremented by one, and the process proceeds to step S23.
Then, the next TS packet 7 is input to the packet switching unit 62.

When the TS packet 7 (invalid packet) is input (when the counter k = 7), the processing after step S24 is the same as the case where the TS packet 5 is input, and the description thereof will be omitted. .

Next, the processing after step S24 when the TS packet 8 is input (when the counter k = 8) will be described.

In step S24, the TS packet 8 is
It is determined that the packet is the TS packet of the packet A, and in step S25, it is determined that the packet is not the first TS packet of the PES packet A.
7, it is determined that the subtraction result is a negative value, and step S
At 31, a TS packet to be replaced is determined.

In step S41, from the counter k = 8,
The value M = 2 is subtracted, the subtraction result = 6 is set in the memory C, and the memory B = 4 is set in the memory D.

In step S42, it is determined that memory B (= 4) <memory C (= 6). In step S48, when the value of the counter k is 6 (= memory C), the value is input from the packet switching unit 61. The assumed TS packet 5 (TS packet 5 and TS packet 6 have been replaced in the process of counter k = 6) is determined to be an invalid packet,
Proceed to step S49.

In step S49, memory C = 6 is set in memory A, and the flow advances to step S32. Step S3
2, when the counter k = 8, the TS packet 8 input to the packet switching unit 62 and when the value of the counter k reaches 6 (= memory A), the TS packet 8 is input to the packet switching unit 61. TS packet 5 is
The replacement is performed as shown in FIG.

In step S33, memory A = 6 is set in memory B, and the flow returns to step S22.

In this way, the packet exchange processing is executed. When the counter k = 9 (FIG. 25 (D)), when the counter k = 11 (FIG. 25 (D)), and when the counter k = 12, (FIG. 25E), packet exchange is performed.

As a result, the reception completion time t E of the PES packet is earlier by two TS packets than the reception completion time t E (FIG. 25A) before the replacement of the TS packets, and the delay margin time TR is large. And becomes equal to the reference time TRC.

In the above description, the case where TS packets are exchanged by using invalid packets has been described as an example. However, audio data or video data are exchanged with each other or the packet transmission interval is specified so that the transmission order is not disrupted. TS using PCI packets to avoid violation of
Packets can be exchanged.

The above-described series of processing can be realized by hardware, but can also be realized by software. When a series of processing is realized by software, a program constituting the software is installed in a computer, and the program is executed by the computer, so that the above-described retransmission device 51 is functionally realized. .

FIG. 30 is a block diagram showing the configuration of an embodiment of the computer 201 functioning as the transmitting device 51 as described above. CPU (Central Processing Uni
t) An input / output interface 216 is connected to 211 via a bus 215, and the CPU 211 receives a keyboard,
When a command is input from an input unit 218 composed of a mouse or the like, for example, a magnetic disk 231, an optical disk 232, or a magneto-optical disk 2 mounted on a ROM (Read Only Memory) 212, a hard disk 214, or a drive 220.
33 or a program stored in a recording medium such as the semiconductor memory 234 is stored in a RAM (Random Access Memory).
y) Load to 213 and execute. Thus, the various processes described above (for example, the processes shown by the flowcharts in FIGS. 15 and 25) are performed. In addition, CPU
An LCD (Liquid Crystal Display) 211 transmits the processing result to, for example, an input / output interface 216.
The information is output as necessary to a display unit 217 composed of, for example,. The program is stored in the hard disk 214 or the ROM 212
In advance, and can be provided to the user integrally with the computer 201, or can be stored in the magnetic disk 231 and the optical disk 2
32, a magneto-optical disk 233, a semiconductor memory 234, etc., or a hard disk 214 via a communication unit 219 from a satellite, a network, or the like.
Can be provided.

In this specification, the steps of describing a program provided by a medium are not limited to processing performed in chronological order in the order described, but are not necessarily performed in chronological order. It also includes processes that are executed individually or individually.

In this specification, a system is
It represents the entire device composed of a plurality of devices.

[0139]

According to the transmission device of the first aspect, the transmission method of the third aspect, and the recording medium of the fourth aspect, the reception completion time at which the data stream arrives at the reception device is detected. Since the detected reception completion time is subtracted from the constraint time and the subtraction result is transmitted in correspondence with the data stream, it is possible to reduce the delay occurring on the data stream.

According to the transmitting apparatus of the fifth aspect, the transmitting method of the seventh aspect, and the recording medium of the eighth aspect, the data stream is composed of a plurality of packets together with the data stream. A delay time obtained by subtracting the reception completion time at which the data stream arrives at the receiving device from the constraint time required to arrive at the receiver is input, and the delay time is increased based on the input delay time. Since the arrangement of the packets constituting the data stream is changed, it is possible to reduce the delay occurring on the data stream.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration example of a conventional satellite digital television broadcasting system.

FIG. 2 is a block diagram illustrating a configuration example of a transmission device 1 of FIG.

FIG. 3 is a block diagram illustrating a configuration example of a receiving device 5 of FIG. 1;

FIG. 4 is a block diagram illustrating a configuration example of a distribution device 7 of FIG. 1;

FIG. 5 is a diagram showing an example of the arrangement of TS packets.

FIG. 6 is a diagram showing an example of arrangement of another TS packet.

FIG. 7 is a diagram illustrating a configuration example of a satellite digital television broadcasting system to which the present invention has been applied.

8 is a block diagram illustrating a configuration example of a transmission device 51. FIG.

9 is a block diagram illustrating a configuration example of a data conversion unit 52. FIG.

FIG. 10 is a block diagram illustrating a configuration example of a margin time calculation unit 61.

FIG. 11 is a diagram illustrating a delay margin time.

FIG. 12 is another diagram for explaining the delay margin time.

FIG. 13 is a diagram illustrating a header of a TS packet.

FIG. 14 is a diagram illustrating a header of a PES packet.

FIG. 15 is a flowchart illustrating a reception completion time calculation process.

FIG. 16 is another diagram illustrating a header of a PES packet.

FIG. 17 is a diagram illustrating an example of a delay margin time.

FIG. 18 is a block diagram illustrating a configuration example of a packet switching unit 62.

FIG. 19 is a diagram illustrating packet replacement.

20 is a block diagram illustrating another configuration example of the packet switching unit 62. FIG.

21 is a block diagram illustrating another configuration example of the packet switching unit 62. FIG.

FIG. 22 is a block diagram illustrating another configuration example of the packet switching unit 62.

FIG. 23 is another diagram illustrating packet replacement.

FIG. 24 is a block diagram illustrating another configuration example of the packet switching unit 62.

FIG. 25 is a flowchart illustrating the operation of the control unit 63.

FIG. 26 is a flowchart illustrating a process in step S31.

FIG. 27 is another diagram illustrating packet replacement.

FIG. 28 is another diagram illustrating packet replacement.

FIG. 29 is another diagram illustrating packet replacement.

FIG. 30 is a block diagram illustrating a configuration example of a computer 101.

[Explanation of symbols]

1 transmitter, 52 data converter, 61 spare time calculator, 62 packet switcher, 63 controller, 64 T-STD analyzer, 71 PSI analyzer, 72
PCR playback section, 73 TS header analysis section, 74 PES header analysis section, 75 reception completion time calculation section, 76 delay margin time calculation section, 77 TS packet memory, 81
FIFO, 82 switches, 91 crossbar type switch 2

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5C059 MA00 RB02 RB10 RB16 SS02 TA71 TC50 5K028 AA11 BB05 CC02 CC05 EE03 EE05 HH01 KK01 KK32 LL14 MM04 MM05 MM08 SS05 SS15 5K030 GA02 HA02 HB28 JA01 KA19 CC07 EE03 5 HH01 HH02 HH16 KK12 KK13 LL07 MM06 NN15 NN32 9A001 BB04 CC05 CC06 DD10 EE02 JJ18 JJ19 KK60 KK62

Claims (8)

[Claims] 1. A transmitting device for transmitting a data stream in which a constraint time required to arrive at a receiving device is defined, wherein detecting means for detecting a reception completion time at which the data stream arrives at the receiving device. Subtracting the reception completion time detected by the detection means from the constraint time, and associating means for associating the subtraction result with the data stream; and the data associated by the association means A transmitting unit for transmitting a stream. 2. The data stream is PES packet data constituting a transport stream conforming to the MPEG2 standard, and the reception completion time is a time when the last data of the PES packet data arrives at the receiving device. The transmission device according to claim 1, wherein the constraint time is a time indicated by DTS or PTS. 3. A transmitting method of a transmitting apparatus for transmitting a data stream in which a constraint time required to arrive at a receiving apparatus is defined, wherein a receiving completion time at which the data stream arrives at the receiving apparatus is detected. A detection step of subtracting the reception completion time detected by the detection step from the constraint time, and associating the subtraction result with the data stream. Transmitting the attached data stream. 4. A transmission program for transmitting a data stream in which a constraint time required to arrive at a receiving device is defined, wherein a reception completion of the data stream arriving at the receiving device is provided. A detecting step of detecting a time, subtracting the reception completion time detected by the detecting step from the constraint time, and associating the subtraction result with the data stream; A transmission step of transmitting the data stream associated with the processing, the recording medium storing a program for causing a computer to execute the processing. 5. A reception completion time at which the data stream arrives at the receiving device is subtracted from a constraint time at which the data stream is required to arrive at the receiving device together with a data stream composed of a plurality of packets. Input means for inputting the set delay time, and changing the arrangement of the packets constituting the data stream based on the delay time input by the input means so as to increase the delay time. A transmitting device comprising: a changing unit. 6. The data stream is configured to increase the delay margin based on a restriction on a compression scheme of the data stream together with the delay margin input by the input unit. The transmitting apparatus according to claim 5, wherein the arrangement of the packets to be performed is changed. 7. A reception completion time at which the data stream arrives at the receiving device is subtracted from a constraint time at which the data stream is required to arrive at the receiving device together with a data stream composed of a plurality of packets. An input step of inputting the obtained delay margin time, based on the delay margin time input in the processing of the input step, the arrangement of the packets constituting the data stream so that the delay margin time increases. And a changing step of changing. 8. A reception completion time at which the data stream arrives at the receiving device is subtracted from a restriction time at which the data stream is required to arrive at the receiving device together with a data stream composed of a plurality of packets. An input step of inputting the obtained delay margin time, based on the delay margin time input in the processing of the input step, the arrangement of the packets constituting the data stream so that the delay margin time increases. A recording medium storing a program for causing a computer to execute a process characterized by including a changing step of changing.