JP2001143490A - Data read-in auxiliary circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To dissolve the problems that when a selector 3 finishes to select a bit line, it charges up a potential of the selected bit line, but since potential of a non-selection bit line positioned at both sides of the selection bit line is fixed to a ground potential, the potential difference between the selection bit line and the non-selection bit line is enlarged, and interwiring capacitance is increased, and consequently, boosting speed of a potential of the selection bit line is made to be slow, high speed read-out is made to be hard. SOLUTION: Before read-out of data from a ROM is started, a read-out potential Vcc is applied to a selection bit line and a non-selection bit line, while when read-out of the data is started after application of the read-out potential Vcc is finished, the non-selection bit line is grounded.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data reading assist circuit for assisting reading data from a memory.

[0002]

2. Description of the Related Art FIG. 7 is a block diagram showing a conventional data reading auxiliary circuit. In FIG. 7, when data is read from a ROM which is a memory, a data read address is output and the data read address is read. Upon receiving a data read address from the CPU 1, the CPU 2 that outputs a sense signal indicating a timing outputs to the selector 3 a selection signal of a bit line for reading data from the ROM among a plurality of bit lines connected to the ROM. On the other hand, the sense amplifier 3 applies the read potential Vcc to the bit line in accordance with the sense signal output from the CPU 1, and the sense amplifier 3
Is a selector that selects a bit line corresponding to the selection signal and connects the bit line to the sense amplifier 2.

Next, the operation will be described. CPU1 is R
When data is read from the OM, a read address of the data and a sense signal indicating the timing of reading the data are output to the sense amplifier 2.

When receiving a data read address from the CPU 1, the sense amplifier 2 analyzes a bit line of the ROM corresponding to the read address, and outputs a select signal of the bit line to the selector 3. The selector 3 is connected to the sense amplifier 2
When a selection signal is received from, a bit line corresponding to the selection signal is selected, and the bit line is connected to the sense amplifier 2.

When the selector 3 completes selection of a bit line, the sense amplifier 2 applies a read potential Vcc to the bit line in accordance with a sense signal output from the CPU 1.
That is, in order to read data from the ROM, R
Since it is necessary to charge up the drain potential of OM, as shown in FIG. 8, the read potential Vcc is applied to the bit line selected by the selector 3 while the sense signal is at the L level.
Is applied.

Next, the sense amplifier 2 outputs the sense signal H
When the level becomes the level, the potential of the bit line is set in a floating state, and IDS, which is a memory current of the ROM, is input from the bit line. The sense amplifier 2 compares the IDS with a predetermined reference value (the reference value is set so as to correspond to the threshold potential of the ROM), and if the IDS is smaller than the reference value, the IDS is stored in the ROM. Is output to the CPU 1, and if the IDS is greater than the reference value, the data indicating that the data stored in the ROM is "0" is output to the CPU 1.
Output to U1.

When the potential of a bit line selected by the selector 3 is in a floating state and the potentials of unselected bit lines located on both sides of the bit line change from H level to L level, the selector 3 The potential of the bit line selected by the selector 3 decreases due to the capacitive coupling between the selected bit line and the unselected bit line. As a result, the margin of the IDS with respect to the reference value is reduced, which may cause a data read error.
Is to fix the non-selected bit lines to the ground level potential through the selector 3 before sensing data in advance. Incidentally, a technique similar to the above-mentioned conventional example is disclosed in Japanese Patent Application Laid-Open No. Hei 4-276393.

[0008]

Since the conventional data reading auxiliary circuit is configured as described above, when the selector 3 completes selection of a bit line, the potential of the selected bit line is charged up. Since the potentials of the non-selected bit lines located on both sides of the selected bit line are fixed at the ground level, the potential difference between the selected bit line and the non-selected bit line becomes large, and the capacitance between wirings increases. as a result,
There has been a problem that the rising speed of the potential of the selected bit line becomes slow, making it difficult to read data at high speed. When data is continuously read from the memory through the selected bit line, if the previous data is “0”, the potential of the selected bit line falls below the threshold potential, and the potential of the selected bit line is charged. However, in this case, as in the case where the selection of the bit line is completed, the speed at which the potential of the selected bit line rises becomes slow, and there is a problem that high-speed reading of data becomes difficult.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide a data reading auxiliary circuit capable of increasing the data reading speed.

[0010]

A data reading auxiliary circuit according to the present invention comprises a bit line selected by a selecting means and a bit line located on both sides of the bit line before the data reading from the memory is started. When the application of the read potential is completed and the reading of the data is started, the bit lines located on both sides of the bit line selected by the selection means are grounded to the ground. It was done.

In the data reading auxiliary circuit according to the present invention, when reading of data from the memory is started, the potential of the bit line selected by the selecting means is lowered.

The data reading auxiliary circuit according to the present invention discharges the electric charge charged in the capacitor to the bit line selected by the selecting means and the bit lines located on both sides of the bit line. is there.

The data reading auxiliary circuit according to the present invention applies a read potential to all bit lines connected to the memory, and when data reading from the memory is started, the data of the bit line selected by the selecting means is selected. The bit lines located on both sides are grounded to the ground.

In the data reading auxiliary circuit according to the present invention, when data reading from the memory is started, the bit lines located on both sides of the bit line selected by the selection means are grounded. .

The data reading auxiliary circuit according to the present invention is configured to discharge the electric charge charged in the capacitor to all the bit lines connected to the memory.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. FIG. 1 is a configuration diagram showing a data reading auxiliary circuit according to Embodiment 1 of the present invention.
When reading data from a ROM, which is a memory, a CPU outputs a read address of the data and outputs a sense signal indicating a read timing of the data;
12, a sense amplifier for reading data from the ROM;
When receiving the data read address from the CPU 11,
It is a bit selection unit that outputs a selection signal of a bit line for reading data from the ROM among a plurality of bit lines connected to the OM.

Reference numeral 14 denotes a bit line (hereinafter referred to as a selected bit line) and a bit line (hereinafter referred to as a selected bit line) located on both sides of the bit line in accordance with a sense signal output from the CPU 11 before data reading from the ROM is started. , Non-selected bit lines), the read potential Vcc is applied.
When data reading is started from M, a potential setting unit (reading potential applying means, grounding means) for setting an unselected bit line to the ground-level potential Vss, and 15 selects IDS, which is a memory current of ROM, and selects the bit line Input from ROM
Is a data sense unit that determines data stored in the data sensing unit. 16 receives the selection signal from the sense amplifier 12,
The selector selects a bit line corresponding to the selection signal and connects the selected bit line to the sense amplifier 12.
The selector 16 and the bit selection unit 13 constitute a selection unit.

Next, the operation will be described. When the CPU 11 reads data from the ROM, the CPU 11 outputs to the sense amplifier 12 a read address of the data and a sense signal indicating the read timing of the data.

The bit selection section 13 of the sense amplifier 12
When receiving a data read address from the CPU 11, the CPU 11 analyzes a bit line of the ROM corresponding to the read address, and outputs a select signal of the bit line to the selector 16. Upon receiving the selection signal from the sense amplifier 12, the selector 16 selects a bit line corresponding to the selection signal, and connects the selected bit line to the sense amplifier 12.

When the selector 16 completes the selection of the bit line, the potential setting section 14 of the sense amplifier 12
Applies the read potential Vcc to the selected bit line in accordance with the sense signal output from. That is, in order to read data from the ROM, it is necessary to charge up the drain potential of the ROM in advance. Therefore, as shown in FIG. 2, while the sense signal is at the L level, the read potential Vc is applied to the selected bit line.
Apply c.

The potential setting section 14 of the sense amplifier 12
In order to reduce the capacitance between the selected bit line and the non-selected bit line and increase the potential rise rate of the selected bit line,
As shown in FIG. 2, while the sense signal is at the L level, the read potential Vcc is also applied to the unselected bit lines. here,
FIG. 3 is a conceptual diagram showing that the capacitance C between the selected bit line and the non-selected bit line becomes substantially zero by setting the potentials of the selected bit line and the non-selected bit line to the same potential (read potential Vcc). It is.

Next, the potential setting section 14 of the sense amplifier 12
When the sense signal goes to H level, the charging of the potentials of the selected bit line and the non-selected bit line ends, the potential of the selected bit line is brought into a floating state, and the data sense section 15 of the sense amplifier 12 IDS, which is a memory current, is input from a selected bit line. The data sense unit 15 of the sense amplifier 12 compares the IDS with a predetermined reference value (the reference value is set so as to correspond to the threshold potential of the ROM). , Outputs data indicating that the data stored in the ROM is “1” to the CPU 11,
If S is greater than the reference value, CPU 11 outputs data indicating that the data stored in the ROM is "0".
(Here, when the data is “1”, the ID is
Although the case where S is smaller than the reference value is shown,
If the IDS is greater than the reference value when the data is "1", data indicating that the data stored in the ROM is "1" is output when the IDS is greater than the reference value. ).

Here, when the data stored in the ROM is "1", the potential of the selected bit line in the floating state is changed from the selected bit line by the data sense section 15 as shown in FIG. Even if the IDS is input, it hardly changes, but if the data stored in the ROM is “0”, the data sense unit 15 inputs the IDS from the selected bit line, and the threshold potential of the ROM is changed. Lower. In other words, when the data stored in the ROM is “1”, the potential of the selected bit line becomes V
When the IDS in the cc state is input and the data stored in the ROM is “0”, the IDS in the state where the potential of the selected bit line is lower than the threshold potential can be input, and the data is stored in the ROM. Data that is being processed can be determined.

Therefore, when the data stored in the ROM is "0", if the potential of the selected bit line quickly falls below the threshold potential, high-speed data reading becomes possible. Therefore, in the first embodiment, in order to enable high-speed reading when the data stored in the ROM is “0”, that is, by lowering the potential of the non-selected bit line, In order to reduce the capacitance between the selected bit lines, the potential setting unit 14 of the sense amplifier 12
Sets the non-selected bit line to the ground level potential Vss through the selector 16.

Specifically, for example, when the read potential Vcc is 5
If the potential of the selected bit line when V and data are "0" is reduced to 1.5 V, the potential difference between the selected bit line and the non-selected bit is 3. It becomes 5V. However, if the unselected bit lines are set to the ground level potential Vss,
The potential difference between the selected bit line and the non-selected bit becomes 1.5V.

As a result, the potential difference between the selected bit line and the non-selected bit line becomes smaller, and accordingly, the capacitance between the selected bit line and the non-selected bit line becomes smaller, and the data stored in the ROM becomes "0". "", The potential drop speed of the selected bit line is increased, and high-speed reading of data becomes possible. Here, FIG. 4 is a conceptual diagram showing that the capacitance C between the selected bit line and the non-selected bit line is reduced by setting the potential of the non-selected bit line to the ground level potential Vss.

As is apparent from the above, the first embodiment
According to the method, before the reading of data from the ROM is started, the read potential Vcc is applied to the selected bit line and the unselected bit line, and the application of the read potential Vcc is completed.
When the reading of the data is started, the unselected bit lines are grounded to the ground, so that there is an effect that the data reading speed can be increased.

Embodiment 2 In the first embodiment, R
Although the case where the threshold potential of the OM is set to 2.5 V has been described, when the threshold potential of the ROM is set to a lower voltage (for example, 2 V), the data stored in the ROM is “ The margin of the potential of the selected bit line with respect to the threshold potential in the case of “0” is reduced, which may cause a data reading error.

Therefore, in the second embodiment, when the threshold potential of the ROM is set to a low value, the potential of the selected bit line when the data stored in the ROM is "0" In order to make the potential lower than that in the first embodiment, that is, to increase the margin of the potential of the selected bit line with respect to the threshold potential when the data stored in the ROM is “0”, When the sense signal output from the CPU 11 becomes H level, the potential setting unit 14 lowers the potential of the selected bit line by, for example, about 1 V as shown in FIG. This allows RO
Even when the threshold potential of M is set to a low value, RO
There is an effect that the data stored in M can be accurately determined.

Embodiment 3 In the first and second embodiments, the case where the potential setting unit 14 of the sense amplifier 12 sets the potential of the bit line has been described.
Is usually composed of a transistor that connects or disconnects the power supply and the bit line, and controls the voltage applied to the bit line by controlling the connection time between the power supply and the bit line. However, the voltage applied to the bit line is determined by the capability of the transistor (for example, the switching speed of the transistor, the internal resistance, and the like).
It is difficult to make settings with a sudden change in the applied voltage.

Therefore, in the third embodiment, the potential setting section 14 of the sense amplifier 12 is constituted by using a capacitor in order to enable a setting involving a sudden change in the applied voltage, and the capacitor is charged. Charge is discharged to the bit line. Thereby, the data reading speed can be further increased.

Embodiment 4 FIG. In the first to third embodiments, the sense amplifier 12 has a built-in potential setting unit 14. However, as shown in FIG.
May be provided for each bit line, and the same effects as those in the first to third embodiments can be obtained.

Embodiment 5 FIG. In the first to third embodiments, the case where the potential setting unit 14 or the charge circuits 21 and 22 apply the read potential Vcc to the selected bit line and the non-selected bit line has been described, but all the bit lines connected to the ROM May be applied with the read potential Vcc. Thus, when charging up the potential of the selected bit line, it is also prevented that the selected bit line is capacitively coupled to non-selected bit lines other than the non-selected bit lines located on both sides. Therefore, the speed at which the potential of the selected bit line rises is further increased, and the effect of being able to further increase the data reading speed is achieved.

[0034]

As described above, according to the present invention, before the data reading from the memory is started, the read potential is applied to the bit line selected by the selecting means and the bit lines located on both sides of the bit line. On the other hand, when the application of the read potential is completed and the reading of the data is started, the bit lines located on both sides of the bit line selected by the selection means are grounded to the ground. ,
There is an effect that the data reading speed can be increased.

According to the present invention, when reading of data from the memory is started, the potential of the bit line selected by the selecting means is lowered, so that the threshold potential of the memory is set to a low value. Even in this case, there is an effect that data stored in the memory can be accurately determined.

According to the present invention, the electric charge charged in the capacitor is discharged to the bit line selected by the selecting means and the bit lines located on both sides of the bit line. There is an effect that the reading speed can be increased.

According to the present invention, the read potential is applied to all the bit lines connected to the memory, and when the reading of data from the memory is started, the bit line is located on both sides of the bit line selected by the selection means. Since the bit line is configured to be grounded to the ground, there is an effect that the data reading speed can be increased.

According to the present invention, when the reading of data from the memory is started, the potential of the bit line selected by the selecting means is lowered, so that the threshold potential of the memory is set to a low value. Even in this case, there is an effect that data stored in the memory can be accurately determined.

According to the present invention, since the electric charge charged in the capacitor is discharged to all the bit lines connected to the memory, the data reading speed can be further increased. .

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a data reading auxiliary circuit according to a first embodiment of the present invention;

FIG. 2 is a waveform diagram showing waveforms of various signals.

FIG. 3 is a conceptual diagram showing that an inter-wire capacitance C between a selected bit line and an unselected bit line becomes substantially zero.

FIG. 4 is a conceptual diagram showing that the inter-wiring capacitance C between a selected bit line and an unselected bit line decreases.

FIG. 5 is a waveform diagram showing waveforms of various signals.

FIG. 6 is a configuration diagram showing a data reading auxiliary circuit according to a fourth embodiment of the present invention.

FIG. 7 is a configuration diagram showing a conventional data reading auxiliary circuit.

FIG. 8 is a waveform chart showing waveforms of various signals.

[Explanation of symbols]

11 CPU, 12 sense amplifier, 13 bit selection unit (selection means), 14 potential setting unit (read potential application means,
Grounding means), 15 data sensing section, 16 selector (selecting means), 21 and 22 charging circuit (reading potential applying means, grounding means).

Claims (6)

[Claims] 1. A selecting means for selecting a bit line for reading data from the memory among a plurality of bit lines connected to the memory, and a selecting means for selecting data before starting reading data from the memory. Read potential applying means for applying a read potential to the selected bit line and bit lines located on both sides of the selected bit line; and application of the read potential by the read potential applying means is completed, and data is read from the memory. And a grounding means for grounding the bit lines located on both sides of the bit line selected by the selecting means to ground. 2. The data reading auxiliary circuit according to claim 1, wherein the grounding means lowers the potential of the bit line selected by the selecting means when data reading from the memory is started. 3. The read potential applying means discharges a charge stored in a capacitor to a bit line selected by a selection means and a bit line located on both sides of the bit line. A data reading auxiliary circuit according to claim 1 or 2. 4. A selecting means for selecting a bit line from which data is read from the memory among a plurality of bit lines connected to the memory, and a reading means for applying a read potential to all bit lines connected to the memory. A data reading auxiliary circuit comprising: potential applying means; and ground means for grounding bit lines located on both sides of the bit line selected by the selecting means to ground when data reading from the memory is started. 5. The data reading auxiliary circuit according to claim 4, wherein the grounding means lowers the potential of the bit line selected by the selecting means when data reading from the memory is started. 6. The read potential applying means discharges a charge charged in a capacitor to all bit lines connected to a memory.
Data reading auxiliary circuit described.