JP2001143472A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce current consumption by providing precharge operation inhibition control applicable to a memory for display. SOLUTION: This semiconductor memory is provided with a control cell 1, with which each of display RAM columns holds precharge control information for inhibiting or permitting the operation of precharge and outputs an inhibit signal NE corresponding to this precharge control information, an OR gate 4 for outputting a precharge signal CP by invalidating or validating a precharge control signal HPC from the outside on the basis of the value of the read inhibit signal NE, and a PMOS transistor P1 for precharging an output bit line 6, in response to the supply of the precharge signal CP. Based on the precharge control information, the precharge operation of a nonuse display RAM column is inhibited.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory, and more particularly, to a semiconductor memory used as a display memory of a liquid crystal controller driver used in portable equipment.

[0002]

2. Description of the Related Art A liquid crystal controller driver, which is used in portable equipment such as a portable telephone in recent years and is a liquid crystal display for performing various control and control function display of the portable equipment, has a multifunctional display and a multi-gradation display. There is a demand for a large screen. This type of liquid crystal controller driver incorporates a RAM (random access memory) as a display memory, and stores commands and data to be controlled, for example, a telephone number of a destination, a speed dial, in a display RAM (hereinafter referred to as a display RAM). The number is stored, and the information is displayed on a liquid crystal display.

[0003] With such multi-functionality, built-in display R
Although the capacity of the AM has been increasing, depending on the actual use condition of the portable device, not all of the mounted functions are necessarily used. Therefore, in the actual function mode, unused bit portions may be formed in the built-in display RAM.

For example, when a liquid crystal controller driver corresponding to display of four gradations is used in a monochrome mode (two gradations), 50% of the display RAM is unused. Further, the display RAM in the non-display portion may be unused regardless of the function mode, and there is no need to precharge the RAM in that portion.

However, in the structure of the RAM used as a general conventional display memory, precharge control is not performed for each bit. As a result, the precharge current for the unused RAM part is wasted.

FIG. 8 is a circuit diagram showing a conventional first semiconductor memory used as a display memory in a general liquid crystal controller driver. Referring to FIG. 8, this conventional first semiconductor memory has a display RAM cell column. (Here, three for convenience of explanation) are arranged in an array, and each row and column has an address decoder. The display RAM cell columns 100A, 200A, and 300A have the same configuration, and two types described later. , Word line WL2, WL3, display row decoder 7, column address decoder 8, and row address decoder 9A.

The conventional first semiconductor memory has a write 1-port and read 2-port RAM having one port for normal data read / write and another read port for driving output of the liquid crystal panel. The cell has a cell configuration, and each read port operates completely asynchronously.

Display RAM cell rows 100A, 200A, 3
Each of 00A has a plurality of main cells 2 for storing display data, but in this figure, only two are shown for convenience of explanation.

An individual display RAM cell column, here, a display RAM cell column 100A is a main cell 2 for storing display data for a liquid crystal display control drive.
A two-input NAND gate 3A for inputting an output control signal HDO and an output signal of the output bit line 6 to each of the input terminals and outputting a display output OUT from the output terminal, and a display output bit line to be precharged An output bit line 6, a PMOS transistor P1 having a source connected to the power supply VDD1, a drain connected to the output bit line 6, and receiving a precharge control signal HPC at the gate, and word lines WL1, WL2, WL3 to be described later. A display row decoder 7 that receives a supply of a row address and a control signal HLAS, takes a logical product (AND) of the row address and the control signal HLAS, activates the word line WL3, and selects the word line WL3. , A column address decoder 8 for decoding a column address and activating the selected complementary bit lines D and DB, and a control signal L And a row address decoder 9 for selecting the word line WL2 by activating the word line WL2 ANDs (AND) receiving the supply of S and row address these row address and control signals LAS.

The main cell 2 includes inverters 21 and 22 each having a data storage cell by connecting one input terminal of the two inverters to the other output terminal (cross connection or ring connection), and a source. And an NMOS transistor N11 having a drain connected to the bit line D and a gate connected to the word line WL2 at a common connection point between the input terminal of the inverter 21 and the output terminal of the inverter 22, and a source connected to the input terminal of the inverter 22 and the input terminal of the inverter 21. The drain is connected to the common connection point of the output terminal, the gate is connected to the complementary bit line DB, and the word line is connected to the word line W.
NMOS transistors N2 connected to L2 respectively
2, an NMOS transistor N23 having a source connected to the ground GND, a gate connected to a common connection point between the input terminal of the inverter 21 and the output terminal of the inverter 22, and a word line for displaying the source at the drain of the transistor N23 and the gate. WL3 includes an NMOS transistor N24 whose drain is connected to the output bit line 6, respectively.

The operation of the first conventional semiconductor memory will be described with reference to FIG. 8 and FIG. 9 showing a time chart of operation waveforms of each section.
Read and write data to and from the address specified by the row and column addresses.
Since the operation is the same as that of the AM and there is no particular change, the detailed operation is omitted.

Next, the operation of the output port for driving the liquid crystal panel will be described.

The display row decoder 7 is provided with ports corresponding to each address, and by supplying a control signal HLAS to these ports, the ports are opened so that the word line WL3 can be selected by the row address. Similarly, the row decoder 9 also has ports corresponding to each address, and by supplying a control signal LAS to these ports, opens the ports to select the word line WL2 based on the row address. Here, in the following description of the operation, the port is a two-input AND gate for convenience of description.

First, when a row address is input, the port of the word line WL3 corresponding to the address specified by the row address is opened by the control signal HLAS, the selected word line WL3 becomes "1", and the word line WL3 All connected display RAM cell columns 100A, 200A, 30
Each transistor N24 of 0A turns on. Accordingly, data of each main cell 2 of the display RAM cell columns 100A, 200A, 300A connected to the selected word line WL3 is output to the output bit line 6 as an output signal BO, and all data is output via the NAND gate 3A. Output OUT at the same time
Is output as

Referring to FIG. 9, first, in a period of time T1, the precharge control signal HPC becomes "0",
Each display RAM cell row 100A, 20
The transistors P1 of the precharge switches of 0A and 300A are simultaneously turned on, and at the same time, the electric charge is charged to the output bit line 6 from the power supply VDD1.

Next, in the period of time T2, the precharge control signal HPC becomes "1" and the transistor P1 is turned off. At this time, the charge of the output bit line 6 is still in a charged state without a discharge path.

Next, in the section of time T3, the control signal HL
AS becomes "1", and all the transistors N24 connected to the word line WL3 selected for address are turned on. Here, if the data of the main cell 2 is "0", the output bit line 6 is still in a charged state with no charge discharging path, and the output signal BO corresponding to this charged state is "1".
Becomes If the data of the main cell 2 is "1", the charge stored in the output bit line 6 is discharged through the ground GND, and the output signal BO becomes "0".

Next, during the period of time T4, the output control signal H
When DO becomes "0" and the output signal BO is "1" (that is, the main cell 2 is "0"), the output OUT becomes "0". Conversely, the output signal BO is "0" (that is, the main cell 2 is "1").
Then, the output OUT becomes "1".

Next, during the period of time T5, the output control signal HDO becomes "1", and the output OUT becomes "0" regardless of the previous data.

Next, in the section of time T6, the control signal H
LAS becomes "0" and the address line is closed.

Next, in the period of time T7, the precharge control signal HPC becomes "0", and the precharge operation of each output bit line 6 is performed.

This is the same operation as in the section of the time T1, and thereafter, the times T8, T9,.
The same operation as in 3... Is repeated.

As described above, the conventional first semiconductor memory does not control the precharge for each bit. As a result, the precharge current for the unused RAM part is wasted.

Therefore, there is a demand for a control circuit for eliminating unnecessary current consumption due to unnecessary precharge in order to realize low power consumption.

Japanese Patent Laid-Open No. 8-2733 has proposed a precharge control method for suppressing such wasteful current consumption.
The semiconductor memory described in Japanese Patent Publication No. 58 (Reference 1) is provided with logic means for controlling a precharge operation by a bit line precharge means based on a control signal (enable signal).
The control of the logic means prohibits the precharge of the bit line which does not need to be precharged.

Referring to FIG. 10, which shows a block diagram of a conventional second semiconductor memory described in Document 1, this conventional second semiconductor memory internally has a pair of CMOS inverters whose outputs are cross-connected. A plurality of RAs, which are memory cells in a semiconductor memory device holding written data,
M cells 101 and 102 and these RAM cells 101 and 1
02 connected to the bit line BL, respectively, NMOS transistors 103 and 104, the bit line BL, word lines WL1 and WL2 connected to the respective gates of the NMOS transistors 103 and 104, and the input sides of the word lines WL1 and WL2. Are provided between the AND gates 5 and 6 for transmitting the address level of each word line selection signal when the precharge signal φ is "0", and the bit line BL, and the precharge for charging up the bit line is provided. A PMOS transistor 107 as a means, and a two-input NAND gate 11 which receives a supply of a precharge signal φ and an enable signal RAME and has an output connected to the gate of the PMOS transistor 107 to control a charge-up operation.
0.

Referring to FIG. 10, the operation of the second conventional semiconductor memory will be described. First, when the level of externally applied enable signal RAME is one,
When the precharge signal φ becomes "1", the PMOS transistor 107 is turned on, and the bit line BL is precharged.

If the word line WL1 is selected, the data "0" held in the RAM cell 1 connected to the word line WL1 is read out to the bit line BL, and the bit line BL is discharged.

However, when the enable signal RAME is "0"
In the case of, even if the precharge signal φ becomes “1”, P
MOS transistor 107 does not turn on, and word line WL1
Does not discharge even if is selected.

As described above, unnecessary current consumption on the bit line BL can be reduced by setting the enable signal RAME to "0" except when necessary.

However, in the conventional second semiconductor memory,
There is no specific circuit definition for the entire RAM to which the enable signal RAME is applied. That is, there is no description as to whether the semiconductor memory is used as a display memory of the liquid crystal controller driver to which the present invention is applied.

The display RAM, which is a display semiconductor memory built in the liquid crystal controller driver, has
The same number of display RAM cell arrays as the number of driver outputs to be used is required. Each of these display RAM cell columns is further composed of two sets for the number of display gray scales (the number of display gray scale bits) expressed in a binary system, for example, in the case of 4 gray scales, each of which has an individual bit line. Therefore, when the precharge control is performed for each display RAM cell column using the same method as the conventional semiconductor memory, the enable signal RAME becomes
The same number of RAM cells as the number of columns × the number of display gradation bits, that is, the number of bit lines is required. For example, when the number of driver outputs is 160 and the gradation of the output signal is 4 gradations,
320 enable signals RAME are required.

Therefore, when the conventional second semiconductor memory is used for such a display memory, there is a problem that the area required for the wiring routed from the outside increases, which is not practical.

[0034]

In the above-mentioned conventional first semiconductor memory, the precharge control is not performed for each bit, so that a precharge current for an unused RAM portion is wasted. was there.

In addition, the second conventional technique for solving the above-mentioned disadvantages has been proposed.
In the semiconductor memory of the present invention, logic means for controlling a precharge operation by a bit line precharge means based on an external control signal (enable signal) is provided, and control of the logic means inhibits precharge of a bit line which does not require precharge. Therefore, when used as a display memory built in the liquid crystal controller driver, the number of enable signal lines is the same as the number of display RAM cell rows × the number of display gradation bits as many as the number of driver outputs. However, there is a disadvantage that the feasibility is poor because the area required for wiring arranged from the outside becomes very large.

It is an object of the present invention to provide a semiconductor memory which solves the above-mentioned drawbacks and realizes low current consumption by realizing a precharge operation prohibition control applicable to a display memory.

[0037]

According to a first aspect of the present invention, there is provided a semiconductor memory in which a plurality of memory cell columns in which a plurality of memory cells are arranged in a column direction are arranged in a row direction, and each of the plurality of memory columns is precharged. A semiconductor memory comprising: a target output bit line; and a precharge means for precharging the output bit line based on a supply of a precharge control signal from outside each time the memory cell is accessed. A control information storage means for holding precharge control information for inhibiting or permitting the precharge operation of the precharge means, and the precharge control signal based on the precharge control information read from the control information storage means. And a precharge control signal control means for invalidating or validating the data, and the control information storage means It is characterized in prohibiting the precharge operation of the memory cell columns not used in accordance with the recharge control information.

Further, the precharge control information comprises a first value for inhibiting the precharge operation and a second value for permitting the precharge operation. A control cell that is a memory cell that holds the control information of one of the written first and second values may be provided.

The precharge means includes a first conductivity type first MOS transistor having a source connected to a power supply, a drain connected to the output bit line, and a gate receiving a precharge signal for controlling precharge. The precharge control signal control means inputs the precharge control information consisting of first and second values to one input terminal and an external precharge control signal to the other input terminal, and A two-input logic gate for invalidating / enabling the precharge control signal at the other input terminal according to the value of the control information and outputting the precharge signal from the output terminal may be provided.

The precharge means includes a first conductivity type first MOS transistor having a source connected to a power supply, a drain connected to the output bit line, and a gate supplied with a precharge signal for controlling precharge. Wherein the precharge control signal control means has one input terminal for the precharge control information comprising first and second values, and the other input terminal for enabling or disabling the precharge control information from outside. , And a two-input first logic gate for outputting a precharge inhibition signal, which is precharge control information for which inhibition control is performed, and the precharge inhibition signal is supplied to one input terminal of the other input terminal. An external precharge control signal is input to the input terminal, and the precharge control signal of the other input terminal is determined by the value of the precharge inhibit signal. May be those from the disable / enable to output the control information comprises a logic gate having two inputs for outputting the pre-charge signal.

Further, the control cell includes first and second inverters each having one input terminal of two inverters connected to the other output terminal to form a cell for storing data, and a source connected to the first inverter. The drain is connected to the common connection point between the input terminal of the inverter and the output terminal of the second inverter, and the gate is connected to the positive-phase bit line which is one of the complementary bit lines for column selection, and the gate is connected to the word line for row selection. A second MOS transistor of a second conductivity type, a source having a common connection point between an input terminal of the second inverter and an output terminal of the first inverter, and a drain having a complementary bit line which is one of the complementary bit lines. And a third MOS transistor of a second conductivity type having a gate connected to the word line.

In a semiconductor memory according to a second aspect of the present invention, a plurality of memory cell columns in which a plurality of memory cells are arranged in a column direction are arranged in a row direction, and an output bit line to be precharged is provided in each of the plurality of memory columns. A semiconductor memory having precharge means for precharging the output bit line based on a supply of a precharge control signal from the outside each time the memory cell is accessed, wherein each of the memory cell columns has a complementary bit line. A first memory cell, which is a RAM cell for holding precharge control data for inhibiting or permitting the precharge operation of the precharge means, and a liquid crystal display control drive connected to the complementary bit line. Memory cell, which is a RAM cell for storing display data for display, and an externally supplied output control signal A three-input first logic gate configured to input the precharge control data from the first memory cell and the output signal of the output bit line to each of input terminals and output a display output from the output terminal; A precharge control signal which receives the precharge control data supplied from the outside to the other input terminal is input to the input terminal, and the value of the precharge control data invalidates / enables the precharge control signal at the other input terminal. A two-input second logic gate for outputting a precharge signal from an output terminal; a first conductive source having a source connected to the first power supply and a drain connected to the output bit line, and a gate receiving the supply of the precharge signal; Type first MOS transistor, a first word line for selecting a row of the first memory cell, and a second word for selecting a row of the second memory cell If a third word line for display row selection of the second memory cell, said first
And a complementary bit line for selecting a column of a second memory cell, wherein a precharge operation of an unused memory cell column is inhibited based on a value of the precharge control data written in the first memory cell. It is characterized by doing.

In a semiconductor memory according to a third aspect of the present invention, a plurality of memory cell columns in which a plurality of memory cells are arranged in a column direction are arranged in a row direction, and an output bit line to be precharged is provided in each of the plurality of memory columns. A semiconductor memory having precharge means for precharging the output bit line based on a supply of a precharge control signal from the outside each time the memory cell is accessed, wherein each of the memory cell columns has a complementary bit line. A first memory cell, which is a RAM cell for holding precharge control data for inhibiting or permitting the precharge operation of the precharge means, and a liquid crystal display control drive connected to the complementary bit line. A second memory cell which is a RAM cell for storing display data for The control data is input to the other input terminal of a prohibition control signal for setting validity or invalidation of the precharge control data from the outside, and a precharge prohibition signal, which is precharge control data subjected to prohibition control, is output. A first input having a first logic gate, an externally supplied output control signal, the precharge inhibition signal, and an output signal of the output bit line input to each of the input terminals and output a display output from the output terminal. And a precharge control signal that receives an external supply from one input terminal and the other input terminal receives the precharge inhibit signal at one input terminal, and the other input terminal receives the precharge inhibit signal according to the value of the precharge inhibit signal. A two-input third logic gate for disabling / enabling a precharge control signal and outputting a precharge signal from an output terminal, and a source connected to a first power supply. A first MOS transistor of a first conductivity type, each of which is connected to the output bit line and receives a supply of the precharge signal at a gate; a first word line for selecting a row of the first memory cell; A second word line for selecting a row of the second memory cell, a third word line for selecting a display row of the second memory cell, and a column for selecting a column of the first and second memory cells; The precharge control data written to the first memory cell based on the setting of the prohibition control signal, to enable or disable the precharge control data. In this case, a precharge operation of the unused memory cell column is prohibited based on a value of the precharge control data.

In the second or third aspect of the present invention, the first and second memory cells may be configured such that one input terminal of two inverters is connected to the other output terminal to form a data storage cell. A second inverter and a source having a drain connected to a common connection point between an input terminal of the first inverter and an output terminal of the second inverter, and a gate connected to a positive-phase bit line which is one of complementary bit lines for column selection. A second MOS transistor of a second conductivity type connected to the first word line, and a source connected to an input terminal of the second inverter and a first MOS transistor.
The third of the second conductivity type has a drain connected to a common connection point at the output terminal of the inverter of the second type and a gate connected to the complementary bit line which is one of the complementary bit lines, and a gate connected to the first word line.
A third transistor and a fourth inverter, wherein the second memory cell comprises a data storage cell by connecting one input terminal of the two inverters to the other output terminal thereof; A source of a second conductivity type having a source connected to a common connection point between an input terminal of the third inverter and an output terminal of the fourth inverter, a drain connected to the positive-phase bit line, and a gate connected to the second word line. And a fourth MOS transistor having a source connected to a common connection point between the input terminal of the fourth inverter and the output terminal of the third inverter, a drain connected to the complementary bit line, and a gate connected to the second word line. A fifth MOS transistor having a second conductivity type, a source connected to a second power supply, and a gate connected to a common connection point between an input terminal of the third inverter and an output terminal of the fourth inverter. And a seventh MOS transistor of a second conductivity type having a source connected to the drain of the sixth transistor, a gate connected to the third word line, and a drain connected to the output bit line, respectively. A transistor may be provided.

[0045]

Next, an embodiment of the present invention will be described in detail with reference to the drawings. The semiconductor memory according to the present embodiment has a storage element (memory cell or the like) for storing precharge control information for each bit line in a cell block, thereby minimizing the addition of peripheral circuits and not using the memory. The cell precharge prohibition control can be performed to reduce current consumption.

Next, referring to FIG. 1 in which a part of a display RAM cell column for one column is shown as a block as a basic part of the semiconductor memory according to the embodiment of the present invention, FIG. The memory is connected to complementary bit lines D and DB and is used for storing data for precharge control.
A control cell 1 which is an M cell; a main cell 2 connected to complementary bit lines D and DB for storing display data for a liquid crystal display control drive; an output control signal HDO and a prohibition signal NE from the control cell 1 And the output signal BO of the output bit line 6 are input to each of the input terminals, and the display output O is output from the output terminal.
A three-input NAND gate 3 for outputting a UT, a prohibition signal NE at one input terminal and a precharge control signal HPC at another input terminal, and a precharge control signal at the other input terminal according to the value of the prohibition signal NE. Disable / enable HPC and output precharge signal CP from output terminal 2
An input OR gate 4, an output bit line 6, which is a display output bit line to be precharged, and a source connected to a power supply VD
A PMOS transistor P1 having a drain connected to the output bit line 6 and a gate connected to the output terminal of the OR gate 4, and word lines WL1, WL2, W
L3.

The control cell 1 includes inverters 11 and 12 each having one input terminal of the two inverters connected to the other output terminal (cross connection or ring connection) to form a data storage cell, and a source. Is connected to a common connection point between the input terminal of the inverter 11 and the output terminal of the inverter 12, an NMOS transistor N 11 having a drain connected to the positive-phase bit line D and a gate connected to the word line WL 1, and a source connected to the input terminal of the inverter 12 and the inverter. An NMOS transistor N12 having a drain connected to the complementary bit line DB and a gate connected to the word line WL1 is provided at a common connection point of the output terminals of the eleventh and eleventh.

The main cell 2 includes inverters 21 and 22 each having a data storage cell by connecting one input terminal of the two inverters to the other output terminal (cross connection or ring connection), and a source. Is connected to a common connection point between the input terminal of the inverter 21 and the output terminal of the inverter 22, an NMOS transistor N 11 having a drain connected to the positive-phase bit line D and a gate connected to the word line WL 2, and a source connected to the input terminal of the inverter 22 and the inverter An NMOS transistor N22 having a drain connected to the complementary bit line DB and a gate connected to the word line WL2 at a common connection point of the output terminal of the output terminal 21;
An NMOS transistor N23 connected to the common connection point of the input terminal of the inverter 1 and the output terminal of the inverter 22, and the source is connected to the drain of the transistor N23, the gate is connected to the display word line WL3, and the drain is connected to the output bit line 6, respectively. NMOS transistor N24.

Next, the operation of this embodiment will be described with reference to FIG.
2, the precharge control information is written. This precharge control information is stored in the inverter 11, that is,
When the output of the control RAM 1 is “1”, the precharge is prohibited,
When "0", precharge is permitted. Therefore, the inverter 11 outputs "1" as the inhibition signal NE when precharging is unnecessary, and outputs "0" as the inhibition signal NE when precharging is performed.

For convenience of explanation, it is assumed that precharge is unnecessary because the target display RAM cell row is not used. Therefore, it is assumed that control cell 1 stores "1" indicating prohibition of precharge. In this case, the inverter 11 outputs the inhibition signal NE
Is output to the NAND gate 3 and the OR gate 4. The OR gate 4 outputs “1” of the inhibition signal NE.
, The other input terminal is invalidated, and a precharge signal CP of “1” is always output irrespective of the level of the precharge control signal HPC input to the other input terminal, and supplied to the precharge transistor P1. I do. The transistor P1 is turned off in response to "1" of the precharge signal CP, and does not perform the precharge operation of the output bit line 6. As a result, current consumption can be reduced.

Next, since the target display RAM cell column is used, precharging is required.
It is assumed that “0” indicating precharge execution is stored. In this case, the inverter 11 outputs “0” as the prohibition signal NE and supplies it to the NAND gate 3 and the OR gate 4. The OR gate 4 activates the other input terminal by inputting "0" of the inhibition signal NE, and changes the level of the precharge signal CP according to the level of the precharge control signal HPC input to the other input terminal. For example, when the precharge control signal HPC is “0”, the recharge signal CP output from the OR gate 4 becomes “0”, and this “0” is supplied to the precharge transistor P1. The transistor P1 outputs "0" of the precharge signal CP.
In response to this, the output bit line 6 is precharged.

Next, a first example of the present embodiment, which is an example used in a liquid crystal display circuit, will be described. The semiconductor memory of this embodiment has a write 1 port having one port for normal data read / write and another one read port for driving output of the liquid crystal panel, similarly to the conventional first semiconductor memory. , A read two-port RAM cell configuration, and each read port operates completely asynchronously.

Referring to FIG. 2, which is a block diagram showing a first embodiment of the present embodiment, the semiconductor memory of this embodiment shown in FIG. 2 has a plurality of display RAM cell columns having the basic configuration shown in FIG. (Here, three for convenience of explanation) are arranged in an array, and each row and column has an address decoder, and the display RAM cell columns 100 and 2 having the same configuration as described above.
00, 300, and the row address and control signal H common to those of the related art.
The row address and the control signal HL are supplied from the LAS.
A logical product (AND) with AS is activated to activate the word line WL3 to select the word line WL3, and a column address is decoded to activate the selected complementary bit lines D and DB. Column address decoder 8
And the supply of the control signal LAS and the row address, the logical product (AND) of the row address and the control signal LAS is obtained, and the word line WL2 is activated to activate the word line WL2.
A row address decoder 9 for selecting L2.

Display RAM cell rows 100, 200, 300
Have a plurality of main cells 2, but in this figure, only two are shown for convenience of explanation.

In this embodiment, the display RAM cell row 100,
One control cell 1 is arranged for each of 200 and 300, that is, for one output bit line 6 for display output, which is a wiring to be precharged, and each output bit line 6 is independently precharged. Can be controlled. Therefore, the difference from the conventional first semiconductor memory shown in FIG. 8 is that the display RAM cell rows 100, 200, and 300 are different.
Add a control cell 1 for precharge control, a NOR gate 4 for controlling a precharge control signal with a precharge inhibit signal output from the control cell 1, and a two-input NAND gate 3A. Instead, a three-input NA is used so that the output is controlled by the precharge inhibit signal.
The ND gate 3 is provided.

Next, the operation of this embodiment will be described with reference to FIGS. 1 and 2 and FIG. 3 which shows the operation waveforms of the respective parts in a time chart. First, a method of writing data to the main cell 2 is a conventional technique. This is the same as the conventional first semiconductor memory described above. The method of writing data to the newly provided control cell 1 is the same as that of the conventional first semiconductor memory.

First, referring to FIG. 3A showing the operation waveforms of the respective parts in a time chart in this case, when the data of the control cell 1 is "0", the output inhibition signal NE is "0". Since the value of the precharge signal CP output from the NOR gate 4 is the same as the value of the precharge control signal HPC from the outside, the circuit operation of the conventional first semiconductor memory is exactly the same.

First, when a row address is input, the port of the word line WL3 corresponding to the address specified by the row address is opened by the control signal HLAS, the selected word line WL3 becomes "1", and the word line WL3 is connected to the selected word line WL3. The transistors N24 of all the connected display RAM cell columns 100, 200, 300 are turned on. Accordingly, the display RAM cell column 1 connected to the selected word line WL3
The data of the main cells 2 of 00, 200, and 300 are all simultaneously output to OUT via the output bit line 6 and the NAND gate 3A.

In the period of time T1, the precharge control signal HPC becomes "0", and the transistors P1 of the precharge switches of the display RAM cell rows 100, 200, and 300 connected to the precharge control signal simultaneously turn on. At the same time, charge is charged from the power supply VDD1 to the output bit line 6.

Next, in the period of time T2, the precharge control signal HPC becomes "1", whereby the precharge signal CP also becomes "1", so that the transistor P1 is turned off. At this time, the charge of the output bit line 6 is still in a charged state without a discharge path.

Next, in the section of time T3, the control signal HL
AS becomes "1", and all the transistors N24 connected to the word line WL3 selected for address are turned on. Here, if the data of the main cell 2 is "0", the output bit line 6 is still in the charged state without the discharge path of the electric charge, and the output signal BO corresponding to this charged state.
Becomes "1". If the data of the main cell 2 is "1", the electric charge stored in the output bit line 6 is equal to the ground GND.
And the output signal BO becomes “0”.

Next, in the section of time T4, the output control signal H
When DO becomes "0" and the output signal BO is "1" (that is, the main cell 2 is "0"), the output OUT becomes "0". Conversely, the output signal BO is "0" (that is, the main cell 2 is "1").
Then, the output OUT becomes "1".

Next, in the section of time T5, the output control signal HDO becomes "1", and the output OUT becomes "0" regardless of the previous data.

Next, in the section of time T6, the control signal H
LAS becomes "0" and the address line is closed.

Next, in the period of time T7, the precharge control signal HPC becomes "0", and the precharge operation of each output bit line 6 is performed.

This is the same operation as in the section of the time T1, and thereafter, the times T8, T9,.
The same operation as in 3... Is repeated.

Next, the circuit operation in this case will be described in order with reference to FIG. 3B showing a time chart of each part when the data of the control cell 1 is "1".

First, in the section of the time T1, the control cell 1
Is "1", the inhibit signal NE output from the control cell 1 becomes "1", whereby the precharge signal CP of the transistor P1 becomes "1" irrespective of the precharge control signal HPC. , The precharge switch transistor P1 is turned off. At this time,
The display output OUT becomes "0" irrespective of the state of the output bit line 6, that is, the value of the output signal BO. After that (time T2, 3 ...), this state does not change until "0" is written to the control cell 1.

Next, when "0" is written to the control cell 1,
Thereafter, as described above, the operation returns to the normal precharge operation, and the precharge operation and the liquid crystal drive output operation are performed.

For example, with respect to the column address X1, the main cell 2
When it is not necessary to read the data of the address X1, that is, when it is not necessary to precharge the output bit line 6 of the address X1, the data "1" is written into the control cell 1 of the display RAM cell row 100 corresponding to the address X1. Thereafter, the precharge operation of the output bit line 6 of the display RAM cell column 100 is stopped, and the current consumption can be reduced.

By writing data "0" to the control cell 1 of the display RAM cell row 100 as required to read data, the output bit line 6 is precharged and data can be read.

That is, by writing data "1" to the control cell 1 of the display RAM cell column which does not need to be read and therefore does not need to be precharged, the precharge of the output bit line 6 of the display RAM cell column is stopped and consumed. The current can be reduced.

The first effect of this embodiment is that the unused R
The point is that the precharge current of the AM cell can be eliminated.

As described in the background art, the display RAM incorporated in the liquid crystal controller driver requires the same number of display RAM cell arrays as the number of driver outputs to be used. Each two more
The number of display gray scales (display gray scale bit number) expressed in a binary system, for example, two sets for four gray scales. As an example, when the number of driver outputs of the liquid crystal controller driver is 160 (the number of cells in the X direction), the number of main cell bits (the number of cells in the Y direction) is 160 (hereinafter 160 × 160), and the gradation of the output signal is 4 gradations, The number of built-in display RAM cell columns is 320. That is, the number of RAM cells is 320 × 160.

When this liquid crystal controller driver is used in the monochrome mode, the number of display RAM cell columns is halved to 160, and the number of RAM cells is halved (320/2 ×
160) only.

Therefore, the remaining 160 columns of display RAM cells are not used, and by applying this embodiment, the current consumption of the RAM during display in the monochrome mode is reduced by 5%.
0% reduction.

The current consumption I of the RAM during display at this time is
Is roughly calculated as follows. I = C × V × f = (0.8 pF * 320/2) * 3V *
(75 Hz * 160) = 4.5 μA Here, C is a capacitance value for charging the charge of the precharge current, and is equivalent to (the wiring capacitance of the output bit line 6) × (number).

The wiring capacity of the output bit line 6 is the actual RAM capacity.
Is calculated to be about 0.8 pF.

The number of output bit lines 6 is 320/2 since only half of the total number of output bit lines 6 in the X direction of the RAM is required.

V is a voltage value, which is 3 V of the operating voltage of the RAM.
It is.

F is a frequency for charging and discharging C. In this example, the frame frequency of the liquid crystal controller driver is set to a general 75 Hz for convenience of explanation. Therefore, 1/7
At a time of 5 Hz, the precharge operation is performed for the number of bits (cells) in the Y direction of the RAM (160 times for 160 cells in this case). That is, the frequency of the precharge operation is 75 Hz × 160.

In general, the current consumption of one chip of the display RAM during display is mainly determined by the clock oscillator, the controller unit,
Consumed in RAM.

Each of these current consumptions is represented by a clock oscillator:
About 15 μA, controller: about 5 μA, RAM: about 1
This is 0 μA, which means that about 30 μA is consumed in one chip.

Therefore, if this embodiment is applied in the monochrome mode, the current consumption during the display of one chip is 25.5 μA.
This means that the current consumption is reduced by about 15%.

As the ratio of the current consumption of the RAM increases as the display size (RAM size) increases in the future, a great effect can be expected from the present invention.

When precharge control is performed for each column using the method of the second conventional semiconductor memory, an extra wiring area is required as described in the prior art. Taking a display RAM of 320 × 160 cells as an example similarly to the present embodiment, it is necessary to route 320 wirings from the outside, and a wiring area of that part is required.

Further, when an external storage element such as a register is provided, a control circuit such as an address decoder for writing data is additionally required.

On the other hand, in this embodiment, the control circuit is a RAM.
Can be placed in the vicinity. Therefore, not only the area increase due to the wiring layout is reduced, but also the address decoder is RA
M, and the area can be reduced as compared with the case of using the second conventional semiconductor memory technology.

In the method of the first embodiment, a rewriting process for rewriting the data of the control cell 1 every time by executing / stopping the precharge is required.

In the second embodiment described below,
This eliminates the need for each rewriting process.

Referring to FIG. 4, which shows the second embodiment of the present invention in the same manner as in FIG. 1 and designates constituent elements common to those in FIG. The display RAM cell array 100B according to the second embodiment is different from the display RAM cell array 100 according to the first embodiment in that the output of the control cell 1 is set to enable / disable an external inhibition signal NE. An AND gate 5 is provided to take the logical product of the signal A and the inhibition signal NE and output the inhibition signal NEA.

Display RAM cell array 100B of the present embodiment
FIG. 5 is a block diagram showing a second embodiment including display RAM cell columns 200B and 300B having the same configuration as that of the display RAM cell column 100B. With reference to FIG. 7, the portions of the display RAM cell rows 100B, 200B, and 300B other than the addition of the AND gate 5 are the same as those in the first embodiment, and thus detailed description is omitted.

AND gate 5 receives supply of inhibition signal NE output from inverter 12 and external inhibition control signal A, and outputs inhibition signal NEA. This inhibition signal NEO is output from NOR gate 3 and OR gate 5. Feeding input.

The NOR gate 3 outputs the output control signal H
The display output OUT is output in response to the supply of DO, the inhibition signal NEA, and the output of the output bit line 6 for display output.

The OR gate 5 has a precharge control signal H
In response to the supply of PC and the inhibition signal NEA, the precharge signal CP is supplied to the gate of the transistor P1.

Next, the operation of this embodiment will be described with reference to FIG. 5 and FIG. 6 which shows the waveforms of the respective parts in a time chart. First, in the section of time T1, the external prohibition control signal A
Is "0", and AND is independent of the state of each control cell 1.
The inhibit signal NEO of the output of the gate 5 is always "0".
Therefore, in this state, all the display RAM cell columns 100B, 2B
No precharge control is performed for 00B and 300B. That is, the operation is the same as the operation of the conventional first semiconductor memory in which the control cell 1 does not exist.

Next, looking at the section of time T2, the external prohibition control signal A becomes "1". At this time, the value of the prohibition signal NE which is the output of each control cell 1 becomes the value of the prohibition signal NEO for the first time. That is, this state is the same as the operation of the first embodiment, and the precharge operation is stopped for the column in which the value of the control cell 1 is "1".

As described above, by writing data in the control cell 1 in advance, all the display RAM cell rows 100B, 200B, 300 can be controlled only by the external inhibition control signal A.
It is possible to control whether or not precharge control can be performed on B.

Referring to FIG. 7, which shows a display image for the data of the control cell 1, FIG. 7A shows an image of data stored in the RAM, and FIG. 7B shows a display image for the data. In this example, the data 201 of the control cell 1 is placed at the top and the data 2 of the main cell 2 is placed at the second and subsequent rows.
02 from the left side of the data 201 of the control cell 1
The case where the eighth and 24th to 33rd cell data (portion surrounded by a dotted line) is “1” and the 9th to 23rd cell data is “0” is shown. Accordingly, the data corresponding to the 1st to 8th and 24th to 33rd cell data from the left side of the data 202 of the main cell 2 are not displayed, and the data corresponding to the 9th to 23rd cell data are displayed.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and various modifications can be made. For example, in the embodiment, all the display RAM cell columns are provided with the control cells 1 respectively.
When it is not necessary to independently perform precharge control on the cell columns, the data of the control cell 1 can be shared by a plurality of display RAM cell columns, and the display RAM cell columns that always need to be displayed can be used. It is needless to say that the control cell 1 need not be provided and that the present invention can be applied without departing from the gist of the present invention.

The control cell 1 for precharge control need not be a RAM cell as long as it is a storage element, and a latch, a register, a ROM or the like may be used as long as it does not depart from the gist of the present invention. Of course, it can be applied.

[0102]

As described above, in the semiconductor memory of the present invention, each of the memory cell columns has control information storage means for holding precharge control information for inhibiting or permitting the precharge operation of the precharge means. A precharge control signal control means for invalidating or validating a precharge control signal based on the read precharge control information, and prohibiting a precharge operation of an unused memory cell column based on the precharge control information. Therefore, there is an effect that current consumption can be reduced by reducing the precharge current of the unused RAM cells.

Further, as compared with the conventional second semiconductor memory which performs precharge control for each column, a circuit area required for arranging external control wiring and arranging peripheral circuits is not required. This has the effect of greatly reducing the circuit area.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a semiconductor memory of the present invention.

FIG. 2 is a block diagram showing a first example of the semiconductor memory according to the present embodiment;

FIG. 3 is a time chart illustrating an example of an operation in the semiconductor memory of the present embodiment.

FIG. 4 is a block diagram showing a second embodiment of the semiconductor memory of the present invention.

FIG. 5 is a block diagram showing a second example of the semiconductor memory according to the present embodiment;

FIG. 6 is a time chart illustrating an example of an operation in the semiconductor memory of the present embodiment.

FIG. 7 is an image diagram showing a display image for control cell data in the semiconductor memory of the present embodiment.

FIG. 8 is a block diagram showing an example of a conventional first semiconductor memory.

FIG. 9 is a time chart showing an example of an operation in a conventional first semiconductor memory.

FIG. 10 is a block diagram showing an example of a second conventional semiconductor memory.

[Explanation of symbols]

Reference Signs List 1 control cell 2 main cell 3, 3A NAND gate 4 NOR gate 5 AND gate 6 output bit line 7 display row decoder 8 column address decoder 9, 9A row address decoder 11, 12, 21, 22 inverter 100, 200, 300, 100A , 200A, 300
A display RAM cell column D, DB bit line P1, N11, N12, N21, N22, N23, N2
4 transistors WL1, WL2, WL3 Word line

Claims (8)

[Claims] 1. A plurality of memory cell columns in which a plurality of memory cells are arranged in a column direction are arranged in a row direction, and each of the plurality of memory columns is provided with an output bit line to be precharged. In a semiconductor memory having a precharge unit for precharging the output bit line based on a supply of a precharge control signal from outside for each access, each of the memory cell columns performs the precharge operation of the precharge unit. Control information storage means for holding prohibition or permission precharge control information; and precharge control signal control means for disabling or enabling the precharge control signal based on the precharge control information read from the control information storage means. And the unused memory based on the precharge control information held in the control information storage means. A semiconductor memory for inhibiting a precharge operation of a memory cell column. 2. The precharge control information comprises a first value for inhibiting the precharge operation and a second value for permitting the precharge operation. Said first written
2. The semiconductor memory according to claim 1, further comprising a control cell that is a memory cell that holds the control information of one of a first value and a second value. 3. The first conductivity type first MOS transistor having a source connected to a power supply, a drain connected to the output bit line, and a gate supplied with a precharge signal for controlling precharge. The precharge control signal control means inputs the precharge control information comprising first and second values to one input terminal and an external precharge control signal to the other input terminal, and 2. The semiconductor memory according to claim 1, further comprising a two-input logic gate for invalidating / enabling a precharge control signal at the other input terminal according to a value of the control information and outputting the precharge signal from an output terminal. . 4. A first conductivity type first MOS transistor having a source connected to a power supply, a drain connected to the output bit line, and a gate receiving a precharge signal for controlling precharge. Wherein the precharge control signal control means has one input terminal having the precharge control information composed of the first and second values and the other input terminal having the precharge control information externally validated or invalidated. And a two-input first logic gate for inputting a prohibition control signal for setting a precharge control signal and outputting a precharge prohibition signal, which is precharge control information for which prohibition control has been performed. An external precharge control signal is input to an input terminal, and the precharge control signal of the other input terminal is determined by the value of the precharge inhibition signal. The semiconductor memory according to claim 1, characterized in that it comprises a two-input logic gate for outputting the pre-charge signal from the disable / enable to output the information. 5. The control cell includes first and second inverters each having one input terminal of two inverters connected to the other output terminal to form a data storage cell, and a source connected to the first inverter. The drain is connected to the common connection point between the input terminal of the inverter and the output terminal of the second inverter, and the gate is connected to the positive-phase bit line which is one of the complementary bit lines for column selection, and the gate is connected to the word line for row selection. A second MOS transistor of a second conductivity type; a source having a common connection point between an input terminal of the second inverter and an output terminal of the first inverter; and a drain having a drain connected to one of the complementary bit lines. 3. A semiconductor memory according to claim 2, further comprising a third MOS transistor of a second conductivity type having a gate connected to said word line. 6. A plurality of memory cell columns in which a plurality of memory cells are arranged in a column direction are arranged in a row direction, and each of the plurality of memory columns is provided with an output bit line to be precharged. In a semiconductor memory having precharge means for precharging the output bit line based on a supply of a precharge control signal from outside for each access, each of the memory cell columns is connected to a complementary bit line, and A first memory cell which is a RAM cell for holding precharge control data for inhibiting or permitting the precharge operation, and storing display data for a liquid crystal display control drive connected to the complementary bit line. A second memory cell, which is a RAM cell for storing the output control signal supplied from the outside and the first memory cell. A three-input first logic gate for inputting the precharge control data and the output signal of the output bit line to each of input terminals and outputting a display output from the output terminal; A precharge control signal for receiving data from the outside is supplied to the other input terminal, and the value of the precharge control data invalidates / enables the precharge control signal at the other input terminal. The second of the two inputs that output
A first MOS transistor of a first conductivity type having a source connected to a first power supply, a drain connected to the output bit line, and a gate supplied with the precharge signal; and a first memory cell. A first word line for selecting a row of the second memory cell; a second word line for selecting a row of the second memory cell; a third word line for selecting a display row of the second memory cell; A complementary bit line for selecting a column of first and second memory cells, and a precharge operation of the memory cell column that is not used based on a value of the precharge control data written in the first memory cell. Semiconductor memory characterized in that prohibition is made. 7. A plurality of memory cell columns in which a plurality of memory cells are arranged in a column direction are arranged in a row direction. Each of the plurality of memory columns is provided with an output bit line to be precharged. In a semiconductor memory having precharge means for precharging the output bit line based on a supply of a precharge control signal from outside for each access, each of the memory cell columns is connected to a complementary bit line, and A first memory cell which is a RAM cell for holding precharge control data for inhibiting or permitting the precharge operation, and storing display data for a liquid crystal display control drive connected to the complementary bit line. A second memory cell, which is a RAM cell for storing the precharge control data at one input terminal. A two-input first logic gate for inputting a prohibition control signal for setting validity or invalidity of the precharge control data from the outside and outputting a precharge prohibition signal which is precharge control data for which prohibition control is performed; A three-input second logic gate for receiving an externally supplied output control signal, the precharge inhibition signal, and an output signal of the output bit line into each of the input terminals and outputting a display output from the output terminal; One of the input terminals receives the precharge inhibit signal and the other input terminal receives a precharge control signal supplied from outside, and the value of the precharge inhibit signal invalidates the precharge control signal at the other input terminal. A two-input third logic gate for enabling and outputting a precharge signal from an output terminal; a source connected to a first power supply; and a drain connected to the output bit line. A first MOS transistor of a first conductivity type that is connected to each other and receives the precharge signal at its gate; a first word line for selecting a row of the first memory cell; A second word line for selecting a row, a third word line for selecting a display row of the second memory cell, and a complementary bit line for selecting a column of the first and second memory cells. The precharge control data written to the first memory cell is validated or invalidated based on the setting of the prohibition control signal, and the precharge control data is validated when the precharge control data is in an activated state. A semiconductor memory, wherein a precharge operation of an unused memory cell column is prohibited based on a value. 8. The first memory cell comprises: first and second inverters each having one input terminal of two inverters connected to the other output terminal to form a data storage cell; A drain is connected to a common connection point between an input terminal of the first inverter and an output terminal of the second inverter, and a gate is connected to the positive-phase bit line, which is one of complementary bit lines for column selection, to the first word line, respectively. A second MOS transistor of a second conductivity type connected to the source; a source connected to a common connection point between the input terminal of the second inverter and the output terminal of the first inverter; and a drain connected to one of the complementary bit lines. A third MOS transistor of a second conductivity type having a gate connected to the phase bit line and a gate connected to the first word line, respectively;
And a third inverter comprising a transistor, wherein the second memory cell comprises a third inverter and a fourth inverter each of which connects one input terminal of the two inverters to the other output terminal to form a data storage cell; A fourth terminal of a second conductivity type having a drain connected to a common connection point between the input terminal of the third inverter and the output terminal of the fourth inverter, the gate connected to the positive-phase bit line, and the gate connected to the second word line, respectively. A second MOS transistor having a source connected to a common connection point between an input terminal of the fourth inverter and an output terminal of the third inverter, a drain connected to the complementary bit line, and a gate connected to the second word line; A fifth MOS transistor of a conductive type, a second MOS transistor having a source connected to the second power supply and a gate connected to a common connection point between the input terminal of the third inverter and the output terminal of the fourth inverter. A sixth MOS transistor of a second conductivity type, a source connected to the drain of the sixth transistor, a gate connected to the third word line, and a drain connected to the output bit line, respectively. The semiconductor memory according to claim 6, comprising: