JP2001142861A - Multiprocessor system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the load on a bus transfer required for a processor to acquire a semaphore bit concerning exclusive control, for which the semaphore bit is used, in a multiprocessor system for accessing shared resources. SOLUTION: A semaphore register 1 has plural semaphore bits and a processor part 21 reads the plural semaphore bits from the semaphore register 1, transits an open semaphore bit, which corresponds to a shared device not to be accessed, among semaphore bits transited to occupancy into non-occupancy, accesses the shared device corresponding to the occupied acquired semaphore bit and transits that acquired semaphore bit into non-occupancy later.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a shared resource (shared memory, shared I / O) in a multiprocessor system.
This is to reduce the frequency of use of the bus with respect to the acquisition of devices.

[0002]

2. Description of the Related Art In a multiprocessor system,
Resources (shared resources) such as memories and I / O devices are shared by a plurality of processors. When a plurality of processors simultaneously access a certain resource, data inconsistency occurs. To prevent this mismatch,
An exclusive control function for limiting the number of processors accessing the shared resource to one is required.

In a multiprocessor system, as a method of realizing an exclusive control function, a lock transaction function of a bus, a read-modify-write function of a memory bus, a semaphore register, and the like have conventionally been used. The method of using a semaphore register is a method that makes it possible to implement exclusive control relatively easily even when the lock transaction function is not supported by the system bus.

As a prior art, an exclusive control method using a semaphore register shown in FIG.
7.

[0005] According to this example, a method of acquiring exclusive resources by using the semaphore register 1 is described. The semaphore register 1 has a function of performing a write operation in the same manner as a normal register operation and changing a register value to a predetermined value (a value indicating resource occupation) immediately after outputting read data. Is a register with In this example, one semaphore register 1 per byte in a 16-bit data bus system.
Is assigned.

[0006]

When the occupation rate of the shared resource by a plurality of processors increases, semaphore bit acquisition failure / reacquisition frequently occurs, and the overhead for processing increases. In the above example (JP-A-5-89057), FIG.
As shown in FIG. 3, two semaphore bits (101, 102) are provided for each 16 bits of the data bus. These semaphore bits are allocated in units of byte addresses, and a plurality of semaphores are simultaneously accessed by one register access. Bits cannot be acquired. Therefore, one register access is required to acquire one semaphore, and when acquiring a plurality of semaphores, the frequency of use of the bus increases.

[0007] Further, when the processor that has acquired the semaphore hangs due to some abnormality, there is a disadvantage that the shared resource remains occupied.

The present invention provides a system in which a semaphore register is constituted by a plurality of semaphore bits and a plurality of semaphore bits can be obtained simultaneously by one access. This reduces the semaphore bit acquisition process.

Further, the present invention provides a method which has a processor ID bit field and provides information effective for failure analysis when an abnormality occurs.

Further, the present invention provides a method having a function of notifying occurrence of abnormality by having a timer function.

[0011]

A multiprocessor system according to the present invention has a plurality of processor units capable of accessing a plurality of shared access targets, and further includes any one of the plurality of shared access targets. A semaphore bit that is associated with a target and manages the occupation and non-occupation of the corresponding shared access target is stored, and when the semaphore bit is read, the read semaphore bit is operated to shift to the occupation. Further, a multiprocessor system having a semaphore register that operates to shift the semaphore bit from occupation to non-occupation when instructed from the outside, wherein the semaphore register has a plurality of the semaphore bits, The processor reads a plurality of the semaphore bits from the semaphore register. The semaphore register causes the read plurality of semaphore bits to be occupied, and the processor unit is an unoccupied semaphore bit among the read semaphore bits and corresponds to a shared access target that is not accessed. Instructing an open semaphore bit to be unoccupied,
The semaphore register shifts the designated open semaphore bit to non-occupied by an instruction from the processor unit, and the processor unit is an unoccupied semaphore bit among the plurality of read semaphore bits, The shared semaphore bit other than the open semaphore bit is accessed, and the shared semaphore bit is accessed.In addition, after the access, the acquired semaphore bit is instructed to be unoccupied. According to an instruction from the processor unit, the designated acquisition semaphore bit is shifted to non-occupation.

The processor section has a program section for storing a program that defines the operation of the processor section, and an operation section. The operation section reads the program from the program section and operates according to the program. It is characterized by the following.

[0013] The plurality of shared access targets are a plurality of storage areas included in one storage device.

When reading the plurality of semaphore bits from the semaphore register, the processor specifies the semaphore bits to be read.

The multiprocessor system has a bus, and the processor unit, when reading the semaphore bit from the semaphore register via the bus, stores the address of the semaphore register output to the bus. The information includes information for identifying the specified semaphore bit.

The multiprocessor system has a control unit for controlling the semaphore register. The processor unit specifies a required number of semaphore bits when reading a plurality of semaphore bits from the semaphore register. The control unit selects, from the plurality of semaphore bits stored in the semaphore register, semaphore bits that are not occupied by the number of requested semaphore bits, outputs the selected semaphore bits, and outputs the selected semaphore bits. And reading the semaphore bit output by the control unit.

The multiprocessor system has a bus, and the processor unit, when reading the semaphore bit from the semaphore register via the bus, stores an address of the semaphore register output to the bus. Is characterized by including the number of requested semaphore bits.

The multiprocessor system has a plurality of processor ID registers associated with the semaphore bits, and the processor unit identifies the processor unit itself in the processor ID registers corresponding to the acquired semaphore bits. It is characterized by storing an ID.

The multiprocessor system has a control unit for controlling the semaphore register, and a bus. The processor unit reads the semaphore bit from the semaphore register via the bus. The control unit stores the processor ID included in the address in the processor ID register corresponding to the acquired semaphore bit, including the processor ID in the address of the semaphore register output to the bus. It is characterized by doing.

The multiprocessor system has a bus, and the processor unit, when reading the semaphore bit from the semaphore register via the bus, stores an address of the semaphore register output to the bus. The number of requested semaphore bits and a processor ID for identifying the processor unit itself are included in the above.

[0021] The multiprocessor system is characterized in that it has a warning unit for outputting a warning when the semaphore bit is occupied for a limited period or more.

The warning section uses a different restriction period for each semaphore bit.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 Hereinafter, the present invention will be described based on embodiments shown in the drawings. FIG. 1 is a diagram showing an example of using an 8-bit semaphore register. The semaphore register 1 includes semaphore bits 100 to 107. Each of the semaphore bits 100 to 107 has a read set / write clear function described below. That is, in the case of read access, the bit value is set to “1” immediately after the output of the read value (read set). In the case of a write access, the writing of “0” to the corresponding bit is ignored, and the writing of “1” clears the bit value set to 1 to “0” (write clear). The semaphore bit cannot be set to "1" by write access.

In this example, the semaphore bit indicates that the resource is occupied by "1" and that the resource is not occupied by "0". Also, FIG.
FIG. 3 is a diagram illustrating a correspondence between a shared resource and each semaphore bit.

FIG. 2 shows a configuration example of a multiprocessor system. The processor 27 and the shared memory 23, the shared I / O devices 24 and 25, and the exclusive control circuit 26 are connected to the bus 27. The processor unit 21 has a program unit 211 and a calculation unit 212. Arithmetic unit 2
12 reads the program stored in the program unit 211 and operates according to it. The same applies to the processor unit 22.

FIG. 4 is a diagram showing an operation flow of the first embodiment. Here, it is assumed that semaphore bits 3 and 4 are occupied by another processor. In this example, a certain processor unit has a memory size of 0x2000.
A case of using a shared memory having a capacity of will be described.

The processor unit executes reading of the semaphore register to acquire a semaphore (S401).
Since it is assumed that the semaphore bits 3 and 4 are occupied by other processor units, the register read value of the processor unit is 0x0018. When the register read is completed, all semaphore bits are set to "1".

The processor unit recognizes that if the bits 0 (100) and 1 (101) not occupied by other processor units are secured, the required memory capacity 0x2000 is satisfied.

At this time, since all the bits of the semaphore register 1 are in a read-set state, it is necessary to release the semaphore bits that do not need to be occupied. Bit 0 (100), 1 (101) in the register reading (0x0018)
The bit inverted value (0xFFE2) of the value (0x001B) in which is set to “1” is written back to the semaphore register (S402, S403). By this operation, unnecessary bits can be released, and the risk of erroneously clearing bits already occupied by another processor can be prevented.

At this time, since the shared memory has been exclusively acquired, the shared memory area (0x
00000000-0x00001FFF) (S404).

When the process for the shared memory is completed and the occupation of the memory is released, the semaphore register is write-cleared (S405). Write data is 0x
As 0003, the bits 0 and 1 are write-cleared.

Embodiment 2 FIG. In the second embodiment, a method of using a semaphore register for designating a bit to be read will be described. FIG. 5 is a diagram showing a semaphore register and an access address configuration according to the second embodiment. FIG. 6 is a diagram showing an operation flow of the second embodiment. The correspondence between the shared resource and each semaphore bit is as shown in FIG. Here, an example will be described in which a certain processor uses addresses 0x00001000 to 0x00002FFF of the shared memory. This memory area corresponds to semaphore bits 1 (101) and 2 (102).

The bit designation information is notified by read access, and an arbitrary bit among a plurality of semaphore bits is selected, designated and accessed to complete the semaphore acquisition by the semaphore register by a single read access. be able to. As shown in FIG. 5, the upper field (device decode field) 530 of the access address 5 output to the bus at the time of read access
Is required to select a device on the system bus (for example, the exclusive control circuit 26). The lower fields (redundancy field 520 and register record field 510) are used for selecting registers and the like in the device. Here, a redundant field 520 that is substantially unnecessary for selecting a register or the like is provided in the lower field.
Using this redundant field 520, it is possible to notify additional information by a single read access.

In this embodiment, the access address 5
, The same number of redundant fields 520 as the number of semaphore bits are provided, and semaphore bit selection information is notified in this field.

The processor unit is a shared memory of 0x000
In order to request the use of addresses 01000 to 0x00002FFF, semaphore registers 1 and 2 are selected and the semaphore register 1 is read. The processor sets the value of the read address redundancy field 520 to 0x06, and notifies the semaphore register 1 that bits 1 (101) and 2 (102) are to be selected (S601).

The processor unit confirms that the semaphore bits 1 and 2 are "0" (unoccupied) based on the read value of the semaphore register 1 (S602). Bit 1 (10
If either 1) or 2 (102) or both bits are "1", the acquisition operation is continued until "0" is read (S603).

When a semaphore can be acquired for bits (101) and 2 (102), 0x00001 of the shared memory is obtained.
It becomes possible to access the addresses from 000 to 0x00002FFF (S604).

When the processing for the shared memory is completed and the occupation of the memory is released, the semaphore register is write-cleared. The write data is set to 0x06, and the bits (101) and 2 (102) are write-cleared (S
605).

In the present embodiment, the semaphore bit is designated and acquired, so that the acquisition may fail. However, there is an advantage that the unnecessary bit release processing in the first embodiment can be omitted.

Embodiment 3 In the third embodiment, a method of specifying the number of request semaphores and accessing a semaphore register will be described. FIG. 7 is a diagram showing a configuration of a semaphore register and an access address, and a correspondence between a shared resource and each semaphore bit. FIG. 8 is a diagram showing an operation flow of the third embodiment. When the semaphore register has an 8-bit configuration, three bits are reserved in the redundant field to specify the number of bits. If the value of the redundant field is 0x0, all bits (8 bits) are specified.

Semaphore bits 0 (100), 1 (10
The case where the processor requests the use of the size of the shared memory capacity 0x3000 in the state where 1) is already in the occupied state will be described as an example.

The processor unit sets the required semaphore bit number to 3 bits to acquire the semaphore and sets the semaphore register 1
Lead. The processor sets the value of the address redundancy field 520 to 0x3, and notifies that the semaphore number is required to be 3 bits (S801).

The semaphore register 1 stores bits 0 (10
Since bits 0) and 1 (101) are already in the occupied state, the bits 2 (102), 3 (103) and 4 (104) are obtained by the processor unit (S802). As a result, the semaphore register 1 outputs 0x1C as a read value (S8).
03). If the semaphore bit is already occupied and the required number of bits cannot be secured, the semaphore register outputs a reading of 0x00 to notify the processor unit that the acquisition has failed.

Since the read value of the semaphore register 1 is 0x1C, the processor unit confirms that the semaphore has been obtained as requested, and checks the 0x2000 to 0x3F of the shared memory.
An access is made to the FF address (corresponding to bits 2, 3, and 4) (S804). If the read value of the semaphore register 1 is 0x00, the acquisition operation is repeated because the acquisition of the semaphore bit has failed.

When the processing on the shared memory is completed and the occupation of the memory is released, the semaphore register is write-cleared. As the write data, bits 2 (102), 3 (103), and 4 (104) are written and cleared as 0x1C (S805).

Embodiment 4 FIG. In the fourth embodiment, a case will be described in which a processor ID register corresponding to a semaphore is provided. FIG. 9 is a diagram illustrating a configuration of a semaphore and a processor ID according to the fourth embodiment. In this embodiment,
The semaphore register 1 has an 8-bit configuration (100 to 10
7), and the processor ID register 60 to
67 are assigned. Processor ID registers 60 to 6
7 stores the processor ID of the processor unit that has acquired the semaphore bits (100 to 107).

The semaphore bits 100 to 107 have the same read set / write clear function as in the first embodiment. The processor ID registers 60 to 67 can be accessed as ordinary readable / writable registers.

A certain processor unit performs read access to the semaphore register 1 to acquire a semaphore bit. The semaphore register 1 outputs the current semaphore bit value by read access and sets the bit value to “1” (indicating occupancy) at the same time. The operation of the semaphore register 1 is the same as in the first embodiment.

Since the bit values of the semaphore register are all set by read access for acquiring the semaphore, unnecessary semaphore bits need to be written and cleared. The write clear operation is the same as in the first embodiment.

The processor unit stores its own processor ID in the processor ID registers 60 to 67 corresponding to the bits that have acquired the semaphore. At this point, the processor unit can access the shared resource corresponding to the acquired semaphore.

When the processing using the shared resource is completed, the processor unit performs a write clear on the semaphore register 1 to release the shared resource. In addition, the contents of the corresponding processor ID registers 60 to 67 are also cleared by writing "0".

Embodiment 5 FIG. In the fifth embodiment, processor ID registers 60 to 67 corresponding to semaphores are provided.
Will be described. FIG. 10 is a diagram showing a configuration of a semaphore, a processor ID register, and an access address according to the fifth embodiment. In this example, the semaphore register 1 has an 8-bit configuration (100 to 107), and processor ID registers 60 to 67 are assigned to each bit. The processor IDs of the processor units that have acquired the semaphore bits 100 to 107 are stored in the processor ID registers 60 to 67.

The semaphore bits 100 to 107 have the same read set / write clear function as in the first embodiment. The processor ID registers 60 to 67 can read the contents of the registers as ordinary read-only registers.

A certain processor (processor ID = 0x0)
A) performs a read access to the semaphore register 1 to acquire a semaphore bit. At this time, its own processor ID: 0x0A is stored in the redundant field 520 as the read address.

The semaphore register 1 outputs the current semaphore bit value by read access and sets the bit value to "1" (indicating occupancy). If the original semaphore bit value is “0” (indicating non-occupancy), the processor ID registers 60 to 67 corresponding to the semaphore bits 100 to 107 are stored in the address redundancy field 520 (here, 0x0A). Change to

When the original semaphore bit value is "1", the processor ID registers 60 to 67 corresponding to the semaphore bits 100 to 107 are not changed.

Since the bit values of the semaphore register 1 are all set by read access for acquiring the semaphore, unnecessary semaphore bits 100 to 1 are set.
07 needs to be write-cleared. The procedure for write clear is the same as in the first embodiment. By this write clear, the unnecessary semaphore bits 100 to 107 are cleared, and the contents of the corresponding unnecessary processor ID registers 60 to 67 are also cleared.

When the processing using the shared memories 74 and 75 is completed, the processor unit performs a write clear on the semaphore register 1 to release the shared memory. When the semaphore register 1 performs the write clear, the contents of the processor ID registers 60 to 67 corresponding to the corresponding semaphore bits 100 to 107 are also cleared.

Embodiment 6 FIG. In the sixth embodiment, a method will be described in which a processor ID register is provided and the number of semaphore bits to be acquired is specified and used. FIG. 11 shows a configuration of a semaphore, a processor ID register, and an access address according to the sixth embodiment. The functions of the semaphore register 1 and the processor ID registers 60 to 67 are the same as described above. The redundant field 520 of the access address 5 is composed of fields for designating a processor ID and the number of requested semaphores. The method of specifying the number of semaphores in the redundant field is the same as described above.

The processor requesting a semaphore stores its own processor ID and the number of requested semaphores in the redundant field 520 of the access address. If the semaphore register 1 has an 8-bit configuration, the required semaphore field in the access address 5 needs only 3 bits. In the case of a system supporting a maximum of 16 processors, for example, a 4-bit configuration is sufficient for the processor ID field. With these bit numbers, it is practically possible to have the information of the processor ID and the number of semaphores in the redundant field of the address, and a semaphore system having an effective function can be configured.

Embodiment 7 FIG. In the seventh embodiment, a method in which a counter corresponding to a semaphore bit is provided will be described. FIG. 12 is a diagram showing a configuration of a semaphore register and a counter according to the seventh embodiment. Counters 70-7 corresponding to each semaphore bit 100-107
7 to monitor the occupied time of the semaphore bit. Semaphore bits 100 to 1 depending on a processor
When 07 becomes occupied, the counters 70 to 77 corresponding to the semaphore bit start counting up. When the semaphore bits 100 to 107 are released, the counter stops counting and resets to the initial value.

Even if the processor section that has acquired the semaphore hangs due to some abnormality and the semaphore bit remains set, the counters 70 to 77 continue to time out when a predetermined time period has elapsed. To detect.

When the counters 70 to 77 detect a timeout, the semaphore bit is forcibly reset. In addition, a warning signal is output from the warning unit 80 to the system (for example, the processor unit) to the effect that a timeout has occurred.

Embodiment 8 FIG. In the eighth embodiment, a method will be described in which the semaphore bits 100 to 107 include the above-described counter, and the timeout value differs for each semaphore bit. The semaphore register configuration is shown in FIG.
Same as 2.

The semaphore bits 100 to 107 are provided with priorities in advance. The counter 70 corresponding to each bit
As the timeout value of 77, different values are set depending on the priority set for each bit. For example, a small timeout value is set for a high-priority bit, and a large timeout value is set for a low-priority bit.

Even if the processor that acquired the semaphore hangs due to some abnormality and the semaphore bit remains set, if the semaphore bit has a high priority, the timeout value is small, so the warning is issued. The signal is notified early, and the semaphore is released to other processors early.

[0067]

The fact that the semaphore register is composed of a plurality of bits makes it possible to acquire a plurality of semaphore bits at the same time. If you need to occupy a large shared memory area across multiple semaphore bits,
An effective acquisition method can be realized without increasing the load on the bus. In addition, there is almost no case where acquisition of the semaphore bit fails.

In the case of a multiple semaphore bit configuration,
If an enable function is provided for each semaphore bit, unnecessary semaphores are not obtained. This reduces contention for semaphore acquisition by a plurality of processors.

Further, the processor specifies only the number of semaphores requested, and the exclusive control circuit including the semaphore register determines which bits can be acquired. Disappears.

By providing the exclusive control circuit including the semaphore register with the processor ID information, it becomes possible to identify the processor section occupying the semaphore.
If the processor occupying the semaphore hangs for some reason, it is possible to determine which processor has occupied the semaphore.

Also, if the semaphore register has the processor ID
In the case where information is provided, if a function of notifying the processor ID in the redundant field of the address is provided, the processor unit does not need to access the processor ID register, and the processor ID to the processor ID register is obtained at the same time when the semaphore is acquired. Storage becomes possible.

Further, by notifying the number of requested semaphores to the semaphore register in addition to the processor ID, it is possible to provide a function of identifying an occupied processor and reduce the number of semaphore acquisition failure cases.

By equipping the exclusive control circuit including the semaphore bit with a counter, the semaphore occupancy can be monitored by the processor. If the processor that has acquired the semaphore hangs for some reason, a warning signal is output when the semaphore bit has passed the specified time while the semaphore bit is occupied, thereby making it possible to avoid infinite occupancy of the semaphore.

By changing the set value of the timeout counter based on the priority of the semaphore bit, for example, for a semaphore bit with many acquisition requests, the timeout value counter value is reduced and released to other processors as soon as possible. Becomes possible.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an example of using an 8-bit semaphore register.

FIG. 2 is a diagram illustrating a configuration example of a multiprocessor system.

FIG. 3 is a diagram showing a correspondence between a shared resource and each semaphore bit.

FIG. 4 is a diagram showing an operation flow according to the first embodiment.

FIG. 5 is a diagram showing a semaphore register and an access address configuration according to a second embodiment.

FIG. 6 is a diagram illustrating an operation flow according to the second embodiment.

FIG. 7 is a diagram showing a configuration of a semaphore register and an access address, and a correspondence between a shared resource and each semaphore bit.

FIG. 8 is a diagram showing an operation flow according to the third embodiment.

FIG. 9 is a diagram illustrating a configuration of a semaphore and a processor ID according to the fourth embodiment.

FIG. 10 is a diagram showing a configuration of a semaphore, a processor ID, and an access address according to the fifth embodiment.

FIG. 11 is a diagram showing a configuration of a semaphore, a processor ID register, and an access address according to the sixth embodiment.

FIG. 12 is a diagram illustrating a configuration of a semaphore register and a counter according to a seventh embodiment.

FIG. 13 is a diagram showing a conventional exclusive control method using a semaphore register.

[Explanation of symbols]

1 semaphore register, 5 access address, 21
22 processor unit, 23 shared memory, 24, 25
Shared I / O device, 26 exclusive control circuit, 60 to 67
Processor ID register, 70-77 counter, 8
0 Warning part, 100-107 Semaphore bit, 211
Program section, 212 arithmetic section, 510 register decode field, 520 redundant field, 530
Device decode field.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5B014 HA02 5B045 EE01 EE03 EE08 EE19 JJ05 JJ07 JJ48 5B060 AA02 AA06 AA13 AB12 AC11 CD15 CD17 KA02 KA05

Claims (12)

[Claims] A plurality of processor units that can access a plurality of shared access targets; and a plurality of processor units that are associated with any one of the plurality of shared access targets, and A semaphore bit for managing occupancy and non-occupancy is stored, and when the semaphore bit is read, the semaphore bit is operated to shift to occupancy. A semaphore register that operates to shift from occupied to unoccupied, wherein the semaphore register has a plurality of the semaphore bits, and the processor unit has a plurality of the semaphore bits from the semaphore register. The semaphore register reads the plurality of semaphores read. The processor shifts the bit to occupied, and the processor unit unoccupies the open semaphore bit, which is a non-occupied semaphore bit among the plurality of read semaphore bits and is a semaphore bit corresponding to a shared access target that is not accessed. The semaphore register instructs to shift, and the semaphore register shifts the designated open semaphore bit to non-occupied by an instruction from the processor unit, and the processor unit unoccupies among the plurality of read semaphore bits. The shared semaphore bit is accessed, and the shared semaphore bit other than the open semaphore bit is accessed, and the shared access target corresponding to the acquired semaphore bit is accessed.After the access, the acquired semaphore bit is instructed to shift to the non-occupied state. , The semaphore register is an instruction from the processor unit. Thus, the multiprocessor system, characterized in that shifting the acquired semaphore bit instructed unoccupied. 2. A program unit for storing a program defining an operation of the processor unit,
2. The multiprocessor system according to claim 1, further comprising an operation unit, wherein the operation unit reads the program from the program unit and operates according to the program. 3. 3. The multiprocessor system according to claim 1, wherein the plurality of shared access targets are a plurality of storage areas included in one storage device. 4. The multiprocessor system according to claim 1, wherein said processor specifies the semaphore bit to be read when reading a plurality of said semaphore bits from said semaphore register. 5. The multiprocessor system has a bus, and the processor unit outputs an address of the semaphore register to be output to the bus when reading the semaphore bit from the semaphore register via the bus. 5. The multiprocessor system according to claim 4, wherein information for identifying the semaphore bit to be specified is included. 6. The multiprocessor system has a control unit for controlling the semaphore register. The processor unit specifies a required number of semaphore bits when reading a plurality of the semaphore bits from the semaphore register. The control unit selects, from among the plurality of semaphore bits stored in the semaphore register, semaphore bits that are not occupied by the number of requested semaphore bits, outputs the selected semaphore bits, and outputs the selected semaphore bits. The multiprocessor system according to claim 1, wherein the unit reads the semaphore bit output by the control unit. 7. The multiprocessor system has a bus, and the processor unit reads the semaphore bit from the semaphore register via the bus, and outputs the address of the semaphore register to be output to the bus. 7. The multiprocessor system according to claim 6, wherein the number of requested semaphore bits is included in the number. 8. The multiprocessor system has a plurality of processor ID registers associated with the semaphore bits, and the processor unit identifies the processor units themselves in the processor ID registers corresponding to the acquired semaphore bits. 2. The multiprocessor system according to claim 1, wherein a processor ID is stored. 9. The multiprocessor system has a control unit for controlling the semaphore register and a bus, and the processor unit reads the semaphore bit from the semaphore register via the bus. , Including the processor ID in the address of the semaphore register to be output to the bus, the control unit stores the processor ID included in the address in a processor ID register corresponding to the acquired semaphore bit. 9. The multiprocessor system according to claim 8, wherein the information is stored in the multiprocessor system. 10. The multiprocessor system has a bus, and the processor unit outputs an address of the semaphore register to be output to the bus when reading the semaphore bit from the semaphore register via the bus. 2. The multiprocessor system according to claim 1, wherein the number of semaphore bits requested and a processor ID for identifying the processor unit itself are included in the number. 11. The multiprocessor system according to claim 1, further comprising a warning unit for outputting a warning when the semaphore bit is occupied for a limited period or more.
A multiprocessor system as described. 12. The multiprocessor system according to claim 11, wherein said warning unit uses a different time limit for each semaphore bit.