JP2001136155A - Digital transmitter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To maintain transmission quality high by taking high-order and low- order bits of data into account so as to minimize the loss of the data even on the occurrence of an error in the data on a transmission line. SOLUTION: A digital transmitter is provided with an analog/digital converter 11 that converts analog data into digital data, a packet generating section 12 that divides the received digital data into a plurality of data depending on the high-order and low-order bits, adds an error correction code to at least the high-order bits of the divided digital data and assembles the high-order and low-order data into respective packets, and radio transmission section 13 and an antenna 14 that transmits the obtained data packets.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital transmission device for converting analog data into digital values and transmitting the digital values.

[0002]

2. Description of the Related Art In a digital radio apparatus for converting analog data such as voice into digital data and then transmitting the radio data, a PHS (Personal Handyphone) is used.
System: a simple cordless telephone system), all data to be transmitted are treated as being equivalent on a transmission line.

[0003]

However, as described above, analog data is treated as equivalent, digitized and transmitted, and even when an error occurs in data due to noise or the like on a transmission path, the case where an error occurs in higher-order data is not affected. In the case where an error occurs in the lower data, the transmission quality is greatly different even though the error rate is the same, and naturally, when an error occurs in the upper data, the transmission quality is greatly impaired. .

[0004] The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to minimize data loss even if an error occurs in data on a transmission path in consideration of upper and lower data. It is an object of the present invention to provide a digital transmission device capable of keeping transmission quality high while keeping transmission quality high.

[0005]

According to the first aspect of the present invention,
A / D conversion means for digitizing analog data;
A dividing means for dividing the digital data obtained by the A / D conversion means into a plurality of pieces in accordance with the upper and lower order, and adding at least an error correction code to at least the upper side of each digital data divided by the dividing means. It is characterized by comprising packet generating means for packetizing, and transmitting means for transmitting each data packet obtained by the packet generating means.

With such a configuration, at least the data packet on the upper side is added with an error correction code, so that even if an error occurs during transmission, there is a high possibility that the data packet can be restored. It is possible to minimize the loss of data even if an error occurs on the transmission path and maintain high transmission quality by taking into account the upper and lower bits of the data when digitizing and transmitting analog data such as Become.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a digital transmitting apparatus according to the present invention will be described below with reference to the drawings.

FIG. 1 shows a basic circuit configuration of the apparatus, in which an analog signal to be transmitted, such as audio and video, is A / A.
It is input to the D converter 11. The A / D converter 11 digitizes the analog signal by sampling the analog signal with a predetermined number of quantization bits based on a sampling clock (not shown), and sends the digital signal to the packet generator 12.

[0010] The packet generator 12 includes an A / D converter 11
The digital data is divided into upper and lower parts and packetized, and the obtained data packets are sequentially transmitted to the wireless transmission unit 13.

The radio transmission unit 13 sequentially performs predetermined modulation on the data packets transmitted from the packet generation unit 12 and superimposes them on a carrier wave, and causes the antenna 14 to transmit and output the data packets to a transmission partner (not shown).

FIG. 2 shows a detailed circuit configuration in the packet generator 12. The digital data sent from the A / D converter 11 is first converted into upper bits and lower bits by a bit distributor 21. The upper bit is sent to the buffer 22 and the lower bit is sent to the buffer 23.

The buffer 22 is composed of a FIFO memory and stores the transmitted upper bit data in a buffer. The stored content is read out to the error detection / addition unit 24.

The error detection adding section 24 adds parity or CRC (Cyclic Redundan) to the upper bit data read from the buffer 22 as an error detection code.
cyCheck) is added to the end to add an error correction adding unit 25.
To send to.

The error correction adding section 25 adds and sets an error correction code to the data of the upper bits to which the error detection code is added at the end, and outputs the data to the header adding section 26.

The header adding section 26 completes the data packet by adding a predetermined header to the upper bit data to which the error correction code is added and the error detection code, and outputs the data packet to the switch 27.

On the other hand, the buffer 23 is also
In the same manner as described above, the buffer memory stores the transmitted lower-order bit data in a FIFO memory, and reads out the stored contents to the error detection / addition unit 28.

The error detection addition unit 28 adds a parity or CRC as an error detection code to the end of the lower bit data read from the buffer 23 and adds a header or CRC to the header.
Output to

The header adding section 29 completes the data packet by adding a predetermined header to the lower-order bit data and the error detection code, and outputs the data packet to the switch 27.

The switch 27 is operable, based on a switching control signal from the control unit 30, to select one of an upper-bit data packet sent from the header adding unit 26 and a lower-bit data packet sent from the header adding unit 29. One of them is alternately switched and selected and output to the wireless transmission unit 13.

The control unit 30 controls the entire operation of the packet generation unit 12 including the switch 27. Based on the count value of the counter 31, the control unit 30 determines the transmission time of the higher-order data packet and the lower-order bit data packet. By performing the management, a switching control signal is output to the switch 27.

Next, the operation of the above embodiment will be described.

It is assumed that the digital data obtained by one sampling sent from the A / D converter 11 is composed of 8 bits "BIT7" to "BIT0" as shown in FIG. I do.

In this case, the bit distribution unit 21 divides the upper two bits “BIT7” and “BIT6” into a first packet A, and the lower six bits “BIT5” to “BIT0” into a second packet B. Then, the upper packet A is stored in the buffer 22 and the lower packet B is stored in the buffer 23.

The packet A, which is the high-order data held in the buffer 22, is read out by the error detecting and adding unit 24, and an error detecting code is added to the end thereof.
5, the header is added by the header adding unit 26 after the error correction code is added to the data itself, so that a data format as shown in FIG.

On the other hand, the packet B, which is lower-order data held in the buffer 23, is read out by the error detecting and adding section 28, an error detecting code is added to the end thereof, and the header is directly added by the header adding section 29. As a result, FIG. 4 (2)
The data format is as shown in FIG.
Sent to

A switch 27 that performs a switching operation under the control of the control unit 30 selects, for example, the packet B sent from the header adding unit 29 first and the packet A sent from the header adding unit 26 later. As a result, assuming that two data packets are alternately output to the wireless transmission unit 13, in the signal as shown in FIG. The data packets are sequentially arranged and superimposed in the state shown in FIG.

Here, especially for the packet A on the upper side in the transmitted signal, an error correction code is added in addition to the error detection code as shown in FIG.
Even if an error occurs due to noise or the like during transmission, there is a high possibility that the original signal can be restored on the receiving side.

Therefore, when digitizing and transmitting analog data such as voice and image data, an error may occur in the data on the transmission line in consideration of the upper / lower digital data obtained by one sampling. Since data loss can be minimized, transmission quality can be maintained at a high level.

In the above embodiment, the modulation method, the transmission frequency band, and the like are not particularly specified for transmission. However, any communication system capable of converting analog data into digital data and then transmitting the data after converting the data into digital data. It goes without saying that any of them can be applied.

In addition, the present invention can be variously modified and implemented without departing from the gist thereof.

[0031]

According to the first aspect of the present invention, since at least the data packet on the upper side is added with an error correction code, it is highly possible to recover even if an error occurs during transmission. When digitizing and transmitting analog data such as voice and images, the upper and lower bits of the data are taken into account, minimizing data loss and maintaining high transmission quality even if data errors occur on the transmission path. It becomes possible.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a basic configuration of a digital transmission device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a detailed circuit configuration in a packet generator of FIG. 1;

FIG. 3 is a diagram showing a bit configuration of sampled digital data according to the embodiment;

FIG. 4 is an exemplary view showing a configuration format of a data packet according to the embodiment;

FIG. 5 is an exemplary view for explaining the arrangement of data packets on a transmission signal according to the embodiment;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 ... A / D converter 12 ... Packet generation part 13 ... Wireless transmission part 14 ... Antenna 21 ... Bit distribution part 22 ... Buffer 23 ... Buffer 24 ... Error detection addition part 25 ... Error correction addition part 26 ... Header addition part 27 ... Switch 28 Error adding unit 29 Header adding unit 30 Control unit 31 Counter

Claims (1)

[Claims] An A / D for digitizing analog data
Converting means; dividing means for dividing the digital data obtained by the A / D converting means into a plurality of pieces according to the upper and lower order; and error correcting code for at least the upper side of each digital data divided by the dividing means. A digital transmitting apparatus comprising: packet generating means for adding and packetizing each; and transmitting means for transmitting each data packet obtained by the packet generating means.