JP2001127250A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To downsize a semiconductor integrated circuit including a circuit for generating non-overlap two-phase clock signals. SOLUTION: When a plurality of modules (41-43) including a clock driver for generating non-overlap clock signals and a logic circuit which is operated based on the non-overlap signals outputted from the clock driver are formed, an on-resistance of a transistor is changed by the non-overlap signals (Vr) fetched from the outside of a semiconductor integrated circuit, thereby controlling a charge time or a discharge time of a capacitor. Accordingly, there is no need of formation of a circuit for generating the non-overlap control signals inside the semiconductor integrated circuit (50) and the chip occupying area can be reduced as a result.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a technique for adjusting a plurality of clock signals, and more particularly to a technique effective when applied to a data processing device such as a single-chip microcomputer.

[0002]

2. Description of the Related Art Japanese Patent Application Laid-Open No. 7-28553 discloses an example of a document describing a technique for generating a non-overlapping clock signal. According to this, in a clock generation circuit, a first circuit for taking in a clock to form a first clock, an inverting circuit for inverting the clock, and taking in the inverted output to form a second clock And a second circuit for performing the operation. The first circuit and the second circuit each include a delay circuit for delaying an input clock and a delay amount for controlling a delay amount of the delay circuit by controlling charging and discharging of a capacitor via a constant current source. And a control circuit. The delay amount control circuit controls the delay amount of the delay circuit by controlling charging and discharging of a capacitor via a constant current source, whereby temperature dependency and power supply voltage dependency of the delay circuit are reduced, The fluctuation of the non-overlap amount is suppressed.

[0003]

However, the present inventor has studied the above-mentioned prior art, and found that the non-overlapping clock signal is supplied to a plurality of modules in the semiconductor integrated circuit. If circuits were formed for each module as they were, they found that the chip occupation area of the semiconductor integrated circuit would increase, and the current consumption would increase, thereby hindering chip miniaturization and lower current consumption. .

An object of the present invention is to provide a technique for reducing the size and current consumption of a semiconductor integrated circuit including a circuit for generating a non-overlapping clock signal.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0006]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, as a first means, a module including a clock driver for generating a non-overlapping clock signal, and a logic circuit operated based on the non-overlapping clock signal output from the clock driver Are formed, the clock driver changes the on-resistance by a capacitor that is charged and discharged in accordance with an input clock signal and a non-overlap control signal taken from outside the semiconductor integrated circuit. It is configured to include a transistor for controlling a charging time or a discharging time of the capacitor, and a logic gate for performing a logic determination of a terminal voltage of the capacitor based on a logic threshold value.

According to the first means, the transistor controls the charging time or the discharging time of the capacitor by changing the on-resistance by the non-overlap control signal taken from outside the semiconductor integrated circuit. By using a non-overlapping control signal from the outside, it is not necessary to form a circuit for generating the non-overlapping control signal inside the semiconductor integrated circuit. In addition, current consumption can be reduced.

At this time, in order to reduce radiated electromagnetic noise by the clock dithering technique, a signal with a level fluctuation for frequency-modulating the non-overlap clock signal is applied as the non-overlap control signal. Can be.

As a second means, a clock driver for generating a non-overlap clock signal based on an input clock signal, and a logic circuit operated based on the non-overlap clock signal output from the clock driver And a non-overlap adjusting circuit that is shared between the plurality of clock drivers and forms a non-overlap control signal capable of adjusting the non-overlap amount of the non-overlap clock signal. Constitutes a semiconductor integrated circuit. At this time, the clock driver controls the charging time or discharging time of the capacitor by changing the on-resistance according to the output signal of the non-overlap adjusting circuit and the capacitor charged and discharged according to the input clock signal. And a logic gate for making a logic determination of the terminal voltage of the capacitor based on a logic threshold value.

According to the second means, since the non-overlap adjusting circuit is shared between the plurality of clock drivers, the non-overlap adjusting circuit is formed in the chip for each clock driver. Compared with this, the area occupied by the chip and the current consumption can be reduced.

At this time, the non-overlap adjusting circuit includes a capacitor that is charged and discharged in accordance with the input clock signal, and a transistor that controls the charging time or discharging time of the capacitor by changing the on-resistance. A driver unit comprising: a logic gate for making a logical determination of a terminal voltage of the capacitor based on a logical threshold value; and a charge pump for generating the control signal based on an output signal of the driver unit. And a part. In order to stabilize the non-overlap control signal, the output signal of the charge pump section is preferably fed back to the control terminal of the transistor.

In order to enable trimming of a voltage supplied to a control terminal of the transistor, the non-overlap adjusting circuit has a capacitor which is charged and discharged in accordance with an input clock signal, and an on-resistance which is changed. A driver unit including a transistor for controlling a charging time or a discharging time of the capacitor, and a logic gate for performing a logic determination of a terminal voltage of the capacitor based on a logic threshold value; And a trimming circuit capable of trimming the voltage supplied to the control terminal.

In order to facilitate the change of the trimming information, it is preferable to provide a register capable of setting the trimming information in the trimming circuit.

Further, in order to reduce radiated electromagnetic noise by the clock dithering technique, the non-overlap adjusting circuit includes a capacitor which is charged and discharged in accordance with an input clock signal, and an output of the non-overlap adjusting circuit. A transistor for controlling a charge time or a discharge time of the capacitor by changing an on-resistance by a signal; and a logic gate for performing a logic determination of a terminal voltage of the capacitor based on a logic threshold. A driver, a constant current source, a capacitor charged and discharged via the constant current source in accordance with an output signal of the driver, a charge pump for generating the control signal, and the charge pump. The non-overlap control signal by controlling the constant current source in It can be configured to include a constant current control circuit for performing frequency modulation of the lap clock signal.

At this time, for each semiconductor integrated circuit, it is possible to determine whether the non-overlapping amount of the non-overlapping clock signal used therein is appropriate or not. A non-overlap amount determination circuit for determining the non-overlap amount based on the lap control signal can be provided.

The above non-overlap amount determination circuit has a first
A first latch circuit for latching predetermined test pattern data based on a clock signal, a second latch circuit for latching an output signal of the first latch circuit based on a second clock signal, and the clock signal And a clock driver for generating the first clock signal and the second clock signal based on the non-overlap control signal.

Further, in order to secure an appropriate non-overlap amount for each chip, a non-volatile storage means for storing non-overlap amount control information determined based on the judgment result of the non-overlap judgment circuit is provided. And control means for setting a non-overlapping amount of the non-overlapping clock signal based on information stored in the non-volatile storage means.

[0019]

FIG. 1 shows an example of a semiconductor integrated circuit according to the present invention. The semiconductor integrated circuit is, but not limited to, a single-chip microcomputer that performs predetermined arithmetic processing, and includes a central processing unit (CPU).
Modules 41, 42, and 43 that perform predetermined functions such as a memory and a memory are formed on a single semiconductor substrate such as a single crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique. Although not particularly limited, the module 41
Includes clock drivers (CDRs) 44 and 45 for generating non-overlapping clock signals φ1 and φ2 supplied to the internal logic circuit based on an external clock signal CK input from the outside. A non-overlap clock signal φ supplied to an internal logic circuit based on an external clock signal CK input from the outside.
Clock driver (CDR) for generating 1, φ2
The module 43 includes a clock driver (CDR) 47 for generating non-overlapping clock signals φ1 and φ2 supplied to the internal logic circuit based on an external clock signal CK input from the outside. Generally, a non-overlap clock signal refers to a plurality of clock signals having a period in which both do not go to a low level or a period in which they do not go to a high level. In this example, the high level of the clock signal is enabled in each of the modules 41 to 43. Therefore, the non-overlap clock signals φ1 and φ2 are both designed to have a period in which they do not become high level.

Each of the clock drivers 44 to 47 has a non-overlap control signal Vr input from the outside.
, The adjustment of the non-overlap clock signals φ1 and φ2 is enabled.

Next, a detailed configuration of the clock drivers 44 to 47 will be described. Although not particularly limited, since the clock drivers 44 to 47 have the same configuration, only one of them, the clock driver 44, will be described in detail.

FIG. 2 shows an example of the configuration of the clock driver 44, and FIG. 3 shows the operation timing of the main part of the clock driver 44.

P-channel type MOS transistor 11
, An n-channel MOS transistor 14 is connected in series.
4, an n-channel MOS transistor 12 is connected in series. The source electrode of the p-channel MOS transistor 11 is coupled to the high potential side power supply Vdd, and the source electrode of the n-channel MOS transistor 12 is
Coupled to ND. External clock signal CK is transmitted to the gate electrode of p-channel MOS transistor 11 and the gate electrode of n-channel MOS transistor 12. The drain electrode of the p-channel type MOS transistor 11 and the drain electrode of the n-channel type MOS transistor 14 are connected to the input terminal of the inverter 16 at the subsequent stage and to the ground GND via the capacitor 15. Here, the capacitor 15 does not necessarily have to have a fixed capacitance, and can be replaced with the input parasitic capacitance of the inverter 16. The input terminal of the inverter 16 is a node n1, and the signal at the node n1 is inverted by the inverter 16. The output terminal of the inverter 16 is set to a node n2. After the signal at the node n2 is inverted by the subsequent inverter 17,
8, the clock signal φ1 is obtained.

An n-channel MOS transistor 22 is connected in series to the p-channel MOS transistor 20, and an n-channel MOS transistor 21 is connected in series to the n-channel MOS transistor 22. p-channel type MOS transistor 2
The source electrode of 0 is coupled to the high potential side power supply Vdd, and the source electrode of the n-channel MOS transistor 21 is coupled to the ground GND. An inverter 19 for inverting the external clock signal CK is provided.
An external clock signal CK is transmitted to the gate electrode of the OS transistor 20 and the gate electrode of the n-channel MOS transistor 21 via the inverter 19. a drain electrode of the p-channel MOS transistor 20;
The drain electrode of the n-channel MOS transistor 22 is coupled to the input terminal of the inverter 24 at the subsequent stage and to the ground GND via the capacitor 23. Here, the capacitor 23 does not necessarily have to have a fixed capacitance, but can be replaced by the input parasitic capacitance of the inverter 24. The input terminal of the inverter 24 is a node n3.
Inverted at 4. The output terminal of the inverter 24 is a node n
4 and the signal of this node n4 is
After being inverted at 5, the signal is further inverted by the inverter 26 at the subsequent stage to obtain the clock signal φ2.

Further, the gate electrode of the n-channel MOS transistor 14 and the n-channel MOS
An external non-overlap control signal Vr is transmitted to the gate electrode of transistor 22.

In the above configuration, the external clock signal C
According to K, the p-channel MOS transistor 11 and the n-channel MOS transistor 12 are switched complementarily. When the p-channel MOS transistor 11 is turned on by the external clock signal CK,
The capacitor 15 is charged through the p-channel MOS transistor 11. The external clock signal C
When the n-channel MOS transistor 12 is turned on by K, the n-channel MOS transistor 1
2, the charge stored in the capacitor 15 is released to the ground GND (discharge). The charge / discharge of the capacitor 15 causes the potential at the node n1 to be delayed from a high level to a low level as shown in FIG.
, The waveform rising timing of the clock signal (= φ1) is delayed as compared with the waveform rising timing of the external clock signal CK. This delay amount affects the duty of the clock signal φ1 (the ratio of the high-level period to one cycle).

Similarly, in response to the external clock signal CK inverted by the inverter 19, the p-channel MOS transistor 20 and the n-channel MOS transistor 21
Are switched complementarily. External clock signal C
When the p-channel MOS transistor 20 is turned on by K, the capacitor 23 is charged through the p-channel MOS transistor 20. When the n-channel MOS transistor 21 is turned on by the external clock signal CK, the n-channel MOS transistor 21
The charge stored in the capacitor 23 is released to the ground GND via the transistor 21. The above capacitor 2
3, the transition of the potential of the node n3 from the high level to the low level is delayed, as shown in FIG.
The rising timing of the waveform of the clock signal (= φ2) at the node n4 is delayed as compared with the falling timing of the waveform of the external clock signal CK in relation to the logical threshold value of the inverter 24 at the subsequent stage. This delay amount affects the duty of the clock signal φ2.

The above n-channel MOS transistor 1
Reference numerals 4 and 22 function as variable resistors whose resistance value between the drain and the source changes according to the voltage level of the non-overlap control signal Vr. By changing the voltage level of the non-overlap control signal Vr from outside, the resistance value between the drain and source of the n-channel MOS transistors 14 and 22 is changed, and the charge release time of the corresponding capacitors 15 and 23 is changed. Is done. Since the change in the charge release time of the capacitors 15 and 23 affects the duty of the non-overlap clock signals φ1 and φ2,
By changing the voltage level of the non-overlap control signal Vr from the outside, the period in which the clock signals φ1 and φ2 are simultaneously at the low level, that is, the clock signal φ
It is possible to control the non-overlap amount of 1, φ2.
Since the non-overlap control signal Vr is taken in from the outside of the chip, there is no need to provide a circuit for generating such a signal Vr in the chip.
It is possible to reduce the chip occupation area and the current consumption.

According to the above example, the following effects can be obtained.

The n-channel MOS transistors 14,
Numeral 22 functions as a variable resistor in which the resistance value between the drain and the source changes according to the voltage level of the non-overlapping control signal Vr supplied from the outside. Therefore, the voltage level of the non-overlapping control signal Vr is changed from the outside. As a result, the n-channel MOS transistor 14,
Since the resistance value between the drain and the source of the capacitor 22 is changed and the charge release time of the corresponding capacitors 15 and 23 is changed, the duty of the clock signals φ1 and φ2 is changed. External control of the non-overlap amount is enabled.

FIG. 4 shows the clock driver (CD)
R) 44 shows another configuration example.

P-channel type MOS transistor 28
, A p-channel MOS transistor 29 is connected in series.
9, an n-channel MOS transistor 30 is connected in series. The source electrode of the p-channel MOS transistor 28 is coupled to the high potential side power supply Vdd, and the source electrode of the n-channel MOS transistor 30 is connected to the ground G.
Coupled to ND. An external clock signal CK is transmitted via the inverter 27 to the gate electrode of the p-channel MOS transistor 28 and the gate electrode of the n-channel MOS transistor 30. p-channel type MOS
A drain electrode of the transistor 29 is coupled to an input terminal of a subsequent inverter 32 and a capacitor 31
To the ground GND. The input terminal of the inverter 32 is set to a node m1, and the signal at the node m1 is inverted by the inverter 32 and further inverted by the inverter 33 at the subsequent stage to obtain the clock signal φ1.

Then, a p-channel MOS transistor 35 is connected in series to the p-channel MOS transistor 34, and an n-channel MOS transistor 36 is connected in series to the p-channel MOS transistor 35. p-channel type MOS transistor 3
4 is connected to the high-potential-side power supply Vdd, and the source electrode of the n-channel MOS transistor 30 is connected to the ground GND. The external clock signal CK is applied to the gate electrode of the p-channel type MOS transistor 34 and the gate electrode of the n-channel type MOS transistor 36.
Is transmitted. P-channel type MOS transistor 35
Is coupled to the input terminal of the inverter 38 at the subsequent stage and to the ground GND via the capacitor 37. The input terminal of the inverter 38 is a node m3. The signal at the node m3 is inverted by the inverter 38 and further inverted by the inverter 39 at the subsequent stage to obtain the clock signal φ2.

Further, the gate electrode of the p-channel MOS transistor 29 and the p-channel MOS
An external non-overlap control signal Vr is transmitted to the gate electrode of transistor 35.

In the above configuration, the p-channel MOS transistor 28 and the n-channel MOS transistor 28 respond to the external clock signal CK inverted by the inverter 27.
The S transistor 30 is switched complementarily.
When the p-channel MOS transistor 28 is turned on by the external clock signal CK, the capacitor 31 is charged via the p-channel MOS transistor 28. When the n-channel MOS transistor 30 is turned on by the external clock signal CK,
The charge stored in the capacitor 31 is released to the ground GND via the channel type MOS transistor 30. The charge / discharge of the capacitor 31 causes the potential of the node m1 to transition from a low level to a high level with a delay as shown in FIG. , The waveform rising timing of the clock signal (= φ1) is delayed as compared with the waveform rising timing of the external clock signal CK. This delay amount affects the duty of the clock signal φ1.

Similarly, according to the external clock signal CK,
The p-channel MOS transistor 34 and the n-channel MOS transistor 36 are switched complementarily. P-channel type M by external clock signal CK
When the OS transistor 34 is turned on, a capacitor 37 is connected via the p-channel MOS transistor 34.
Is charged. When the n-channel MOS transistor 36 is turned on by the external clock signal CK,
Through this n-channel MOS transistor 36,
The charge stored in the capacitor 37 is released to the ground GND. By charging and discharging the capacitor 37, the node m3
3, the transition from the low level to the high level is delayed, and the waveform of the clock signal (= φ2) at the output terminal of the inverter 39 in relation to the logical threshold value of the inverter 38 at the subsequent stage The rising timing is delayed as compared with the rising timing of the waveform of the external clock signal CK. This delay amount is equal to the clock signal φ2
Affects the duty of the vehicle.

The above p-channel type MOS transistor 2
Reference numerals 9 and 35 function as variable resistors whose resistance value between the drain and the source changes according to the voltage level of the non-overlap control signal Vr. By changing the voltage level of the non-overlap control signal Vr from the outside, the resistance value between the drain and the source of the p-channel MOS transistors 29 and 35 is changed, and the charge release time of the corresponding capacitors 31 and 37 is changed. Is done. Since the change in the charge release time of the capacitors 31 and 37 affects the rising timing of the non-overlapping clock control signals φ1 and φ2, the non-overlapping control signal V
By changing the voltage level of r, it is possible to control the non-overlap amount of the non-overlap clock signals φ1 and φ2.

As described above, since the duty of the clock signal can be changed based on the non-overlap control signal Vr from the outside, the non-overlap amount can be controlled.

Next, another configuration example will be described.

FIG. 6 shows another configuration example of the semiconductor integrated circuit according to the present invention. Although not particularly limited, the circuit shown in FIG. 6 includes modules 51 to 56 each having a predetermined function, and is formed on one semiconductor substrate such as a single crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique. . The semiconductor integrated circuit 50 includes a clock generation circuit (CPG) 57 for generating a clock signal of a predetermined frequency based on a crystal EX arranged outside the semiconductor integrated circuit 50, and a clock signal based on an output signal thereof. And a non-overlap adjusting circuit 58 for adjusting the amount of non-overlap.

The module 51 receives the non-overlap clock signal φ1 supplied to the internal logic circuit based on the external clock signal CK input from the outside and the non-overlap control signal Vr from the non-overlap adjusting circuit 58. , Φ2, and a module 52 based on an external clock signal CK input from the outside and a non-overlap control signal Vr from the non-overlap adjusting circuit 58. And a clock driver 61 for generating the non-overlapping clock signals φ1 and φ2 supplied to the internal logic circuit. The module 54 includes a non-overlap clock signal φ1, supplied to an internal logic circuit based on an external clock signal CK input from the outside.
Includes clock driver 63 for generating φ2. The module 55 receives the non-overlap clock signals φ1 and φ2 supplied to the internal logic circuit based on the external clock signal CK input from the outside and the non-overlap control signal Vr from the non-overlap adjustment circuit 58.
For generating the clock signal. The module 55 includes an external clock signal C input from the outside.
And a clock driver 64 for generating non-overlapping clock signals φ1 and φ2 supplied to the internal logic circuit based on K and the non-overlapping control signal Vr from the non-overlap adjusting circuit 58. The module 56 includes an externally input external clock signal CK,
And a clock driver 65 for generating non-overlap clock signals φ1 and φ2 supplied to the internal logic circuit based on the non-overlap control signal Vr from the non-overlap adjustment circuit 58.

Here, the clock drivers 59 to 65 are not particularly limited, but the circuit configuration shown in FIG. 2 or 4 can be applied as it is.

FIG. 7 shows the non-overlap adjusting circuit 5.
8 is shown.

As shown in FIG. 7, the non-overlap adjusting circuit 58 includes a clock driver (CDRX) 581.
And a charge pump (CP) 582 for generating the non-overlap control signal Vr based on the output signal of the clock driver 581.

The clock driver 581 is configured as follows.

P-channel MOS transistor 67
, An n-channel MOS transistor 69 is connected in series.
9, an n-channel MOS transistor 68 is connected in series. The source electrode of the p-channel MOS transistor 67 is coupled to the high potential side power supply Vdd, and the source electrode of the n-channel MOS transistor 68 is connected to the ground G.
Coupled to ND. External clock signal CK is transmitted to the gate electrode of p-channel MOS transistor 67 and the gate electrode of n-channel MOS transistor 68. The drain electrode of the p-channel type MOS transistor 67 and the drain electrode of the n-channel type MOS transistor 69 are connected to the input terminal of the inverter 71 at the subsequent stage and to the ground GND via the capacitor 70. The input signal of the inverter 71 is inverted by the inverter 71. After the output signal of inverter 71 is inverted by inverter 72 at the subsequent stage and further inverted by inverter 73 at the subsequent stage, clock signal φ1 is obtained, and this clock signal φ1 is input to charge pump 582 at the subsequent stage. Also, the non-overlap control signal Vr output from the charge pump 582
Is an n-channel MOS transistor 6 in the clock driver 581 for stabilizing the control signal Vr.
9 is fed back to the gate electrode
The on-resistance of the channel type MOS transistor 69 is controlled.

The charge pump 582 is configured as follows.

A p-channel MOS transistor 74 forming a constant current source for flowing a constant current IC;
N-channel type MO that forms a constant current source for flowing D
An S transistor 77 is provided.

A p-channel MOS transistor 75 is connected in series to a p-channel MOS transistor 74, an n-channel MOS transistor 76 is connected in series to the p-channel MOS transistor 75, and an n-channel MOS transistor 77 is connected in series. Connected. The source electrode of the p-channel MOS transistor 74 is connected to the high potential power supply Vdd, and the source electrode of the n-channel MOS transistor 77 is connected to the ground GND. The p-channel MOS transistor 74 functions as a constant current source for supplying a constant current IC by supplying a predetermined bias voltage to the gate electrode. The n-channel MOS transistor 77 functions as a constant current source for supplying a constant current ID when a predetermined bias voltage is supplied to the gate electrode.

The clock driver 581 is connected to the gate electrode of the p-channel MOS transistor 75 and the gate electrode of the n-channel MOS transistor 76.
Is transmitted. The drain electrode of the p-channel MOS transistor 75 and the drain electrode of the n-channel MOS transistor 76 are connected to the ground GND via the capacitor 78. The terminal voltage of the capacitor 78 is used as the non-overlap control signal Vr.

In the above configuration, the clock generation circuit 5
7 according to the clock signal CK from
When the S transistor 67 is turned on, the capacitor 70
Is charged, and the n-channel MOS transistor 6 is charged.
When 8 is turned on, the charge stored in the capacitor 70 is released via the n-channel MOS transistor 69.

When the clock signal CK from the clock generation circuit 57 changes from the high level to the low level, the p-channel MOS transistor 67 is turned on, whereby the capacitor 70 is rapidly charged and the inverter 71 is turned on.
, The output logic of the inverter 72 becomes high level, and the output logic of the inverter 73 becomes low level. Then, the p-channel MOS transistor 75 in the charge pump 582 is turned on, and the constant current IC
Thereby, the capacitor 78 is charged. This charging raises the gate potential of the n-channel MOS transistor 69, and controls the on-resistance of the MOS transistor 69.

Next, when the clock signal CK from the clock generation circuit 57 changes from low level to high level, the p-channel MOS transistor 67 is turned off,
The n-channel MOS transistor 68 is turned on. Then, the charge stored in the capacitor 70 is released via the n-channel MOS transistors 69 and 68. Due to this charge release, when the terminal potential of the capacitor 70 is gradually lowered and becomes lower than the logical threshold value of the inverter 71, the output logic of the inverter 71 is inverted.

The duty of clock signal φ1 can be controlled by changing the voltage level of non-overlap control signal Vr. The voltage level of the non-overlap control signal Vr can be adjusted by adjusting the bias voltage of the p-channel MOS transistor 74 or the bias voltage of the n-channel MOS transistor 77 to change the values of the constant current IC and ID. . Here, the duty D of the clock CK145 is represented by the following equation.

[0055]

D = ID / (IC + ID)

In the above equation, when IC = ID, a clock signal having a duty of 50% is obtained. And IC>
In the case of ID, the duty 5
Clock signals of less than 0% can be obtained.

[0057]

D = 1 / (IC / ID + 1) <0.5

According to the above example, the following functions and effects can be obtained.

One non-overlap adjusting circuit 58 is shared among a plurality of clock drivers 59 to 65 in the semiconductor integrated circuit 50. Therefore, it is possible to reduce the chip area occupied by the clock system and the current consumption as compared with the case where the dedicated non-overlap adjusting circuit 58 is configured for each clock driver.

FIG. 8 shows another configuration example of the semiconductor integrated circuit according to the present invention.

The difference between the circuit shown in FIG. 8 and the circuit shown in FIG.
Non-overlap adjusting circuit 58-1 and module 53
To the second non-overlap adjusting circuits 58-
2 is provided. The non-overlap control signal Vr1 generated by the first non-overlap adjustment circuit 58-1 is supplied to clock drivers 59 to 61, and the non-overlap control signal Vr1 generated by the second non-overlap adjustment circuit 58-2. Vr2 is supplied to clock drivers 62 to 65. The first non-overlap adjustment circuit 58-1 and the second non-overlap adjustment circuit 58-2 have basically the same configuration as the non-overlap adjustment circuit 58 shown in FIG.

According to the above configuration, the modules 51, 5
1st non-overlap adjusting circuit 58-1 corresponding to 2
And the second non-overlap adjusting circuit 58-2 corresponding to the modules 53 to 56 are provided separately.
The non-overlap amount in the non-overlap clock signals φ1 and φ2 used in the modules 51 and 52;
Even when the non-overlapping amounts of the non-overlapping clock signals φ1 and φ2 used in the modules 53 to 56 are different, it is possible to easily cope with the case.

Further, between the clock drivers 59 to 61,
One non-overlap adjusting circuit 58-1 is shared,
One non-overlap adjusting circuit 58-2 is shared between the clock drivers 62 to 65, and the chip occupied area of the clock system is reduced as compared with a case where a dedicated non-overlap adjusting circuit is provided for each clock driver. Can be reduced.

FIG. 9 shows another example of the configuration of the non-overlap adjusting circuit 58.

The difference between the non-overlap adjusting circuit 58 shown in FIG. 9 and that shown in FIG. 7 is that a trimming circuit 583 is provided so that the non-overlap control signal Vr is trimmed by the trimming circuit 583. It is a point that was made. The trimming circuit 583 includes a voltage dividing resistor 8
2 and a switch circuit 81 for selecting taps of the voltage dividing resistor 82. One end of the voltage dividing resistor 583 is coupled to the high-potential-side power supply Vdd, and the other end is coupled to the ground GND. The switch circuit 81 is driven by a trimming control signal. The trimming control signal is generated based on trimming information set in the register 83 in the semiconductor chip. When the tap selection is performed by the switch circuit 81, the level of the voltage supplied to the gate electrode of the n-channel MOS transistor 69 is changed. This voltage is transmitted to a plurality of clock drivers as a non-overlap control signal. The output signal MON of the clock driver CDRX is externally output for monitoring.

FIG. 10 shows a change in the non-overlap amount when the configuration shown in FIG. 9 is employed. When the taps are switched in the order of the taps a1 and a2 in the voltage dividing resistor 82 in accordance with the setting information of the register 83, the non-overlap amount increases in the order of non1 to non2 and eventually stabilizes at non3.

FIG. 11 shows a non-overlap adjusting circuit 5
8 shows another configuration example.

The difference between the non-overlap adjusting circuit 58 shown in FIG. 11 and the circuit shown in FIG.
The difference is that a constant current source control circuit 80 capable of adjusting the constant current ID in the charge pump 582 is provided. The constant current source control circuit 80 is configured as shown by 800, although not particularly limited.

A predetermined bias voltage is applied to a bias circuit 81.
4, and a selector 801 for switching a constant current amount based on a control signal input from the outside. The selector 801 generates two types of select signals indicated by s1 and s2 as select signals. Although not particularly limited, the select signal s1 is always at a high level (logical value “1”), and the logical value of the select signal s2 is changed according to the control signal. The select signal s1 from the selector 801 is transmitted to the gate electrode of the n-channel MOS transistor 809 and, after being inverted by the inverter 810, is transmitted to the gate electrode of the subsequent n-channel MOS transistor 812. Also, the selector 8
01 is an n-channel MOS
The signal is transmitted to the gate electrode of the transistor 808, inverted by the inverter 811, and then transmitted to the gate electrode of the subsequent n-channel MOS transistor 813. The bias circuit 814 has a terminal OUT for outputting two kinds of bias voltages having different voltage levels from each other.
1 and OUT2. The bias voltage output from the first terminal OUT1 is supplied as P1 to the gate electrode of the p-channel MOS transistor 74 in the charge pump 582. The supply of the constant voltage IC is performed by the supply of the bias voltage. The bias voltage output from the second terminal OUT2 is output as N1 or N2 depending on selection by the n-channel MOS transistors 808 and 809. N1 is n in the charge pump 582
N2 is supplied to the gate electrode of the channel type MOS transistor 771, and N2 is supplied to the gate electrode of the n-channel type MOS transistor 772 in the charge pump 582.

The bias circuit 814 is configured as follows.

An n-channel MOS transistor 802
And an n-channel MOS transistor 803 are connected in series, a p-channel MOS transistor 804 and an n-channel MOS transistor 805 are connected in series, and a p-channel MOS transistor 806 and an n-channel MOS transistor 807 are connected in series Is done. N-channel MOS transistors 805 and 807
Are current mirror-coupled to an n-channel MOS transistor 803, and a p-channel MOS transistor 806 is current-mirror-coupled to a p-channel MOS transistor 804. A first bias voltage is obtained from the drain electrode side of the p-channel MOS transistor 806, and a second bias voltage is obtained from the drain electrode side of the p-channel MOS transistor 802.

FIG. 12 shows the operation timing of the main part when the non-overlap adjusting circuit 58 is configured as described above.

The select signal s1 is selected by the selector s1.
Is at a high level and the select signal s2 is at a low level, the n-channel MOS transistor 809
Is turned on, a predetermined bias voltage is supplied to the gate electrode of the n-channel MOS transistor 771 in the charge pump 800, and a predetermined constant current flows. Select signal s according to the control signal
When the select signal s2 is set to a high level in addition to 1, the n-channel MOS transistors 771, 77
When a predetermined bias voltage is supplied to the second gate electrode, the amount of charge release from the capacitor 78 increases, and the potential of the non-overlap control signal Vr decreases,
Thereby, the non-overlapping two-phase clock signal φ
The non-overlap amount of 1 and φ2 is changed from non1 to non2
(Where NON1 <non2). When the select signal s2 is set to the low level in response to the control signal, the supply of the bias voltage to the gate electrode of the n-channel MOS transistor 772 is cut off, so that the amount of charge released from the capacitor 78 decreases. As a result, the potential of the non-overlap control signal Vr is raised, and the non-overlap two-phase clock signals φ1, φ2
Is returned to φ1.

As described above, since the non-overlapping amount of the non-overlapping two-phase clock signals φ1 and φ2 can be switched according to the control signal, the non-overlapping control signal Vr can be modulated by the frequency of the control signal. it can. Although the frequency of this control signal is not particularly limited, it is 32.768 KHz, which is a clock subclock used in a single-chip microcomputer, or a frequency obtained by dividing the frequency. When the non-overlap control signal Vr is modulated, the charge release time from the capacitors 15 and 23 and the charge time to the capacitors 31 and 37 in the clock drivers 59 to 56 are changed. Is performed. Thus, clock dithering can be performed. According to the clock dithering, the frequency distribution of the noise peak is widened, so that the noise peak value is reduced,
Thereby, EMI is reduced. An example of a document describing clock dithering is Nikkei B
Published by Company P, "Nikkei Electronics, 199
8.1.12 (No. 707) pp. 135-143
Page ".

FIG. 13 shows another configuration example of the semiconductor integrated circuit according to the present invention.

The semiconductor integrated circuit 50 shown in FIG. 3 is formed on one semiconductor integrated circuit such as a single crystal silicon substrate including the modules 41, 42, and 43, although not particularly limited. It is assumed that the non-overlap control signal Vr supplied from the outside is frequency-modulated by a circuit arranged outside the semiconductor integrated circuit 50. By inputting such a non-overlap control signal Vr to the modules 41 to 43, the frequency modulation of the internally generated non-overlap two-phase clock signals φ1 and φ2 can be performed. The module 41 includes first clock drivers (CDd) 91 and 92, and second clock drivers (CD) 95 and 96 disposed downstream of the first clock drivers (CDd) 91 and 92. The module 42 includes a first clock driver (C
Dd) 93, and a second clock driver (CD) 97 disposed at a stage subsequent thereto. Module 4 above
Reference numeral 2 denotes a first clock driver (CDd) 93 and a second clock driver (CD) 97 disposed downstream of the first clock driver (CDd) 93.
Comprising.

The first clock drivers 91 to 94 have the same configuration, and the second clock drivers 95 to 98 have the same configuration.

FIG. 14 shows first clock drivers 91-91.
A configuration example of the first clock driver 91 which is one of the 94 is representatively shown.

External clock signal CK input from outside
Is provided. Then, an n-channel MOS transistor 114 is connected in series to the p-channel MOS transistor 112,
Further, the n-channel MOS transistor 114
, An n-channel MOS transistor 113 is connected in series. The source electrode of the p-channel MOS transistor 112 is connected to the high potential side power supply Vdd, and the source electrode of the n-channel MOS transistor 113 is connected to the ground GND. The external clock signal CK is transmitted to the gate electrode of the p-channel MOS transistor 112 and the gate electrode of the n-channel MOS transistor 113 via the inverter 111. The drain electrode of the p-channel type MOS transistor 112 and the drain electrode of the n-channel type MOS transistor 114 are connected to the input terminal of the inverter 116 at the subsequent stage and to the ground GND via the capacitor 115. The output signal of the inverter 116 is transmitted to the subsequent circuit after being inverted by the subsequent inverter 117.

Similarly, an n-channel MOS transistor 120 is connected to a p-channel MOS transistor 118.
Are connected in series, and an n-channel MOS transistor 119 is connected in series to the n-channel MOS transistor 120. The source electrode of the p-channel type MOS transistor 118 is connected to the high potential side power supply Vdd, and the source electrode of the n-channel type MOS transistor 119 is connected to the ground GND. The output signal of the inverter 117 is transmitted to the gate electrode of the p-channel MOS transistor 118 and the gate electrode of the n-channel MOS transistor 119. The drain electrode of the p-channel type MOS transistor 118 and the drain electrode of the n-channel type MOS transistor 120 are connected to the input terminal of the inverter 122 at the subsequent stage and to the ground GND via the capacitor 121. The output signal CKi of the inverter 122 is transmitted to the corresponding second clock driver 95.

The above n-channel MOS transistor 1
The non-overlap control signal Vr taken in from the outside is transmitted to the gate electrodes 14 and 120, whereby the amount of charge release from the capacitors 115 and 120 is controlled.

FIG. 15 shows a configuration example of the second driver 95.

Inverters 102 and 103 for delaying the output signal CKi of the first clock driver 91 are provided, and the output signal of the inverter 103 and the first
The NAND logic with the output signal CKi of the clock driver 91 is obtained by the NAND gate 103. This NAND Gate 1
The output signal of 04 is inverted by the inverter 105 at the subsequent stage, and then supplied to the internal logic circuit (not shown) of the module 41 as a clock signal φ1 which is one of the non-overlapping two-phase clock signals.

An inverter 106 for inverting the output signal CKi of the first clock driver 91 is provided. Inverters 107 and 108 for delaying the output signal of the inverter 106 are provided.
Is obtained by the NAND gate 109. The output signal of the NAND gate 109 is inverted by the inverter 110 at the subsequent stage, and then supplied to the internal logic circuit (not shown) in the module 41 as the clock signal φ2 which is the other of the non-overlapping two-phase clock signals.

In the above configuration, the non-overlap control signal Vr externally input to the first clock drivers 91 to 94 is input after being modulated outside the semiconductor integrated circuit 50 for clock dithering. . As a result, the non-overlapping two-phase clock signal φ
The EMI noise of 1, 2 can be reduced.

The non-overlap signal Vr may be modulated in the semiconductor integrated circuit 50 and supplied in the same manner as described with reference to FIGS.

FIG. 16 shows another configuration example of the semiconductor integrated circuit according to the present invention.

A major difference between the semiconductor integrated circuit shown in FIG. 16 and the circuit shown in FIG. 6 is that a non-overlap amount determination circuit 123 for determining a non-overlap amount is provided.
Is provided. In FIG. 16, components corresponding to the modules 51 and 52 shown in FIG. 6 are omitted.

The non-overlap amount determination circuit 123 includes:
Clock signal CK is transmitted from clock generation circuit 57, non-overlap control signal Vr is transmitted from non-overlap adjustment circuit 58, and predetermined test pattern data is input from outside semiconductor integrated circuit 123. The non-overlap amount determination circuit 123 determines the non-overlap amount by determining whether or not the test pattern data can be accurately latched based on the clock signal CK and the non-overlap control signal Vr.

FIG. 17 shows an example of the configuration of the non-overlap amount determination circuit 123.

As shown in FIG. 17, the non-overlapping amount determining circuit 123 converts the non-overlapping two-phase clock signals φ1 and φ2 based on the clock signal CK and the non-overlapping control signal Vr. The operation is controlled by the clock driver 124 for generating, the first latch circuit 125 for latching the test pattern data input from the outside by the operation control by the generated clock signal φ1, and the operation control by the clock signal φ2. Accordingly, the second latch circuit 126 for latching the test pattern data of the output node P of the first latch circuit 125 is included. The output signal of the second latch circuit 126 is used as the determination result of the non-overlap amount determination circuit 123. The configuration shown in FIG. 2 or FIG. 4 can be adopted as the clock driver 124.

FIG. 18 shows the operation timing of the non-overlap amount determination circuit 123.

When the level of the non-overlap control signal Vr is changed by the non-overlap adjustment circuit 58, the non-overlap amount of the non-overlap two-phase clocks φ1 and φ2 in each of the modules 53 to 56 is changed. This change also appears in the non-overlapping two-phase clock signals φ1 and φ2 output from the clock driver 124 in the non-overlap amount determination circuit 123. If the non-overlap amount in the non-overlap two-phase clock signals φ1 and φ2 is appropriate, the logic of the output node P of the first latch circuit 125 is changed to the second
Correct latching can be performed by the latch circuit 126. When the level of the non-overlap control signal Vr is changed by the non-overlap adjustment circuit 58, the non-overlap amount of the non-overlap two-phase clock signals φ1 and φ2 is gradually reduced. The logic of the output node P of the first latch circuit 125 cannot be correctly latched by the second latch circuit 126. In other words, according to the example of FIG. 18, although the logic of the node P must be latched as a low level in the second latch circuit 126, it is erroneously latched as a high level due to a shortage of non-overlap. Would. Therefore, by gradually reducing the non-overlap amount while monitoring the determination result of the non-overlap amount determination circuit 123, it is possible to grasp the non-overlap amount immediately before a malfunction occurs in the second latch circuit 126. Can be.
Thereby, the optimal non-overlap amount can be obtained in the semiconductor integrated circuit 50. In order to be able to easily reproduce the optimal non-overlap amount thus obtained, the non-overlap amount control information for obtaining the optimal non-overlap amount is stored in a non-volatile memory such as a flash memory. Every other, for example, a semiconductor integrated circuit 5
When the power supply is turned on, the adjustment state of the non-overlap adjustment circuit 58 may be reproduced based on information stored in the nonvolatile memory. FIG. 19 shows a configuration example for realizing this.

In FIG. 19, a module 54 includes a CPU
(Central processing unit), the module 55 is a RAM, and the module 56 is a nonvolatile memory. The nonvolatile memory is not particularly limited, but is a flash memory,
It is made accessible by the PU.

By gradually reducing the non-overlap amount while monitoring the result of the determination by the non-overlap amount determination circuit 123, the non-overlap amount immediately before a malfunction occurs in the second latch circuit 126 is grasped. ,
Thereby, the optimum non-overlap amount is determined in advance in the semiconductor integrated circuit 50. Then, the control information of the non-overlap adjustment circuit 58 at that time is stored in the nonvolatile memory as the module 56. Here, the control information of the non-overlap adjustment circuit 58 is set information of the register 83 when the non-overlap adjustment circuit 58 has, for example, the configuration shown in FIG.
It is stored in a nonvolatile memory 56 which is a module 56. Then, in the initialization performed after the power of the semiconductor integrated circuit 50 is turned on, the setting information of the register 83 is reset based on the storage information in the nonvolatile memory, so that the optimal non-overlap in the semiconductor integrated circuit 50 is performed. The amount is reproduced.

Although the invention made by the inventor has been specifically described above, the present invention is not limited to this, and it goes without saying that various modifications can be made without departing from the gist of the invention.

For example, the clock driver in the non-overlap adjusting circuit 58 is configured to release the electric charge stored in the capacitor 70 by the n-channel MOS transistor, but as shown in FIG. 4, the p-channel MOS transistor 29 (or 35) via the capacitor 31
(Or 37) may be charged.

In the above example, the non-overlap clock signals φ1 and φ2 are both designed to have a period in which they do not go to a high level, but they may be designed to have a period in which they do not go to a low level. The present invention can be applied to such a case.

Further, the case where the non-overlapping clock signal has two phases of φ1 and φ2 has been described. However, the non-overlapping clock signal may exceed two phases, and the present invention is applied to such a case. can do.

In the above description, the case where the invention made by the present inventor is mainly applied to a single-chip microcomputer which is the field of application as the background has been described, but the present invention is not limited thereto.
It can be widely applied to various semiconductor integrated circuits.

The present invention can be applied on condition that at least a clock driver is included.

[0102]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the charge time or the discharge time of the capacitor is controlled by changing the on-resistance of the transistor by the non-overlap control signal received from the outside of the semiconductor integrated circuit. Since it is not necessary to form a circuit for generating the non-overlap control signal, the area occupied by the chip and the current consumption can be reduced accordingly.

Further, since the non-overlap adjusting circuit is shared by a plurality of clock drivers, the chip occupation area is reduced and the current consumption is reduced as compared with the case where the non-overlap adjusting circuit is formed in each chip for each clock driver. Can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an overall configuration example of a semiconductor integrated circuit according to the present invention.

FIG. 2 is a circuit diagram illustrating a configuration example of a clock driver illustrated in FIG. 1;

FIG. 3 is an operation timing chart of a main part in the clock driver shown in FIG. 2;

FIG. 4 is a circuit diagram illustrating another configuration example of the clock driver shown in FIG. 1;

FIG. 5 is an operation timing chart of a main part in the clock driver shown in FIG. 4;

FIG. 6 is a block diagram showing another configuration example of the semiconductor integrated circuit according to the present invention.

FIG. 7 is a circuit diagram illustrating a configuration example of a non-overlap adjusting circuit in FIG. 6;

FIG. 8 is a block diagram showing another configuration example of the semiconductor integrated circuit according to the present invention.

FIG. 9 is a circuit diagram of another configuration example of the non-overlap adjusting circuit.

FIG. 10 is a timing chart showing a change in the non-overlap amount when the configuration shown in FIG. 9 is employed.

FIG. 11 is a circuit diagram illustrating another configuration example of the non-overlap adjusting circuit.

FIG. 12 is an operation timing chart of a main part when the configuration shown in FIG. 11 is adopted;

FIG. 13 is a block diagram illustrating another configuration example of the semiconductor integrated circuit according to the present invention.

FIG. 14 is a circuit diagram showing a configuration example of a first clock driver shown in FIG. 13;

FIG. 15 is a circuit diagram showing a configuration example of a second clock driver shown in FIG. 13;

FIG. 16 is a block diagram showing another configuration example of the semiconductor integrated circuit according to the present invention.

FIG. 17 is a block diagram illustrating a configuration example of a non-overlap amount determination circuit illustrated in FIG. 16;

FIG. 18 is an operation timing chart of the non-overlap amount determination circuit.

FIG. 19 is a block diagram showing another configuration example of the semiconductor integrated circuit according to the present invention.

[Explanation of symbols]

 41 to 43, 51 to 56 Modules 44 to 47, 59 to 65 Clock Driver 50 Semiconductor Integrated Circuit 53 Clock Generation Circuit 57 Clock Generation Circuit 58 Non-Overlap Adjustment Circuit 31, 37, 69, 78 Capacitor 14, 22, 69 n Channel Type MOS transistor 29, 35 p-channel type MOS transistor 81 switch circuit 82 voltage dividing resistor 83 register 581 clock driver 582 charge pump 583 trimming circuit

Continuing on the front page (72) Inventor Hirozo Kawai 5-22-1, Kamimizuhoncho, Kodaira-shi, Tokyo F-term in Hitachi Super LSI Systems Co., Ltd. 5F038 AV06 BB07 BB08 BG05 CA02 CA03 CD06 CD08 DF04 DF05 DF11 EZ20 5J039 EE04 EE21 EE27 KK10 MM04

Claims (11)

[Claims] 1. A plurality of modules each including a clock driver for generating a plurality of clock signals and a logic circuit operated based on the plurality of clock signals output from the clock driver are formed. The clock driver controls the charge time or the discharge time of the capacitor by changing the on-resistance by the charge and discharge of the capacitor according to the input clock signal and the control signal taken from outside the semiconductor integrated circuit. And a logic gate for making a logic determination of a terminal voltage of the capacitor based on a logic threshold value. 2. A plurality of modules each including a clock driver for generating a non-overlapping clock signal and a logic circuit operated based on the non-overlapping clock signal output from the clock driver are formed. The clock driver is configured to charge or discharge the capacitor by charging and discharging in accordance with an input clock signal and changing the on-resistance by a non-overlap control signal taken from outside the semiconductor integrated circuit. A transistor for controlling time;
A logic gate for making a logic determination of a terminal voltage of the capacitor based on a logic threshold value. 3. A clock driver for generating a non-overlapping clock signal based on an input clock signal, and a logic circuit operated based on the non-overlapping clock signal output from the clock driver. And a non-overlap adjusting circuit shared by the plurality of clock drivers to form a non-overlap control signal capable of adjusting a non-overlap amount of the non-overlap clock signal. The clock driver has a logic circuit that performs charging and discharging in accordance with the input clock signal, and a transistor that controls the charging time or discharging time of the capacitor by changing the on-resistance according to the non-overlap control signal. Of the terminal voltage of the capacitor based on the threshold value The semiconductor integrated circuit, characterized in that comprising a logic gate for performing a management decision. 4. The semiconductor integrated circuit according to claim 2, wherein the non-overlap control signal is a signal accompanied by a level change for frequency-modulating the non-overlap clock signal. 5. The non-overlap adjusting circuit includes: a capacitor that is charged and discharged in accordance with an input clock signal; a transistor that controls a charging time or a discharging time of the capacitor by changing an on-resistance;
A driver unit including a logic gate for making a logical determination of a terminal voltage of the capacitor based on a logical threshold value, and a non-overlap control signal for generating the non-overlap control signal based on an output signal of the driver unit 4. The semiconductor integrated circuit according to claim 3, further comprising: a charge pump section, wherein an output signal of the charge pump section is fed back to a control terminal of the transistor. 6. The non-overlap adjusting circuit includes: a capacitor that is charged and discharged in accordance with an input clock signal; a transistor that controls a charging time or a discharging time of the capacitor by changing an on-resistance;
A driver unit including a logic gate for making a logical determination of a terminal voltage of the capacitor based on a logical threshold value; and a trimming circuit capable of trimming a voltage supplied to a control terminal of the transistor. 4. The semiconductor integrated circuit according to claim 3, comprising: 7. The semiconductor integrated circuit according to claim 6, further comprising a register capable of setting trimming information in said trimming circuit. 8. The non-overlap adjusting circuit includes a capacitor that is charged and discharged in accordance with an input clock signal, and a charging time or a charging time of the capacitor that is changed by an on-resistance according to an output signal of the non-overlap adjusting circuit. A driver unit including a transistor for controlling a discharge time, and a logic gate for making a logic determination of a terminal voltage of the capacitor based on a logic threshold value; a constant current source; and an output of the driver unit. A capacitor charged and discharged via the constant current source in response to a signal, a charge pump unit for generating the non-overlap control signal, and a non-overlap control by controlling a constant current source in the charge pump unit Constant current control for frequency modulation of non-overlap clock signal by giving level fluctuation to signal It includes a circuit, a semiconductor integrated circuit according to claim 3, wherein the control terminal formed by the feedback of the output signal is the transistor of the charge pump section. 9. The semiconductor integrated circuit according to claim 3, further comprising a non-overlap amount determining circuit for determining a non-overlap amount based on said clock signal and said non-overlap control signal. circuit. 10. The non-overlap amount determining circuit,
A first latch circuit for latching predetermined test pattern data based on a first clock signal, a second latch circuit for latching an output signal of the first latch circuit based on a second clock signal, 10. The semiconductor integrated circuit according to claim 9, further comprising: a clock driver for generating the first clock signal and the second clock signal based on a clock signal and the non-overlap control signal. 11. A nonvolatile storage means for storing non-overlap amount control information determined based on a determination result of said non-overlap amount determination circuit, and resetting the storage information of said nonvolatile storage means by resetting. 11. The semiconductor integrated circuit according to claim 9, further comprising control means for setting a non-overlapping amount of the non-overlapping clock signal based on the non-overlapping clock signal.