JP2001127172A - Input protection circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an input protection circuit which is hardly short-circuited even if a high voltage is applied from a high-potential power supply Vdd in a normal operation ensuring a voltage input terminal of a high electrostatic breakdown voltage. SOLUTION: An input protection circuit is composed of a discharge circuit 3 and a voltage detection circuit 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input protection circuit against electrostatic discharge.

[0002]

2. Description of the Related Art Conventionally, a semiconductor integrated circuit, especially a complementary MO
As shown in FIG. 6, an input protection circuit in an S integrated circuit connects a voltage input terminal 2 and an internal circuit 1 via a resistor R1, and forms a gate electrode, a source electrode, and a back gate electrode of an N-channel MOS field effect transistor Q1. Is connected to the low potential power supply Vss, the drain electrode is connected to the voltage input terminal 2, the gate electrode and the source electrode and the back gate electrode of the P-channel MOS field effect transistor Q22 are connected to the high potential power supply Vdd, and the drain electrode is connected to the voltage. It is configured to be connected to the input terminal 2.

A high potential power supply Vd is externally applied to a voltage input terminal 2.
When a positive static electricity exceeding d is applied, the emitter-collector of the parasitic PNP bipolar transistor having the drain electrode of the P-channel MOS field-effect transistor Q22 as the emitter electrode, the source electrode as the collector electrode, and the back gate electrode as the base electrode Path becomes conductive and P
The conduction of the source / drain path of the channel MOS field-effect transistor Q22 causes static electricity to flow to the high potential power supply V
dd, and when negative static electricity exceeding the low potential power supply Vss is applied to the voltage input terminal 2 from the outside,
An emitter-collector path of a parasitic NPN bipolar transistor having a drain electrode as an emitter electrode, a source electrode as a collector electrode, and a back gate electrode as a base electrode of the N-channel MOS field effect transistor Q1 conducts,
Further, by conducting the source / drain path of the N-channel MOS field effect transistor Q1, static electricity is discharged to the low potential power supply Vss, and furthermore, the current flowing into the internal circuit 1 is suppressed by the resistor R1, thereby protecting the internal circuit. Is done.

[0004]

However, for example, if the internal circuit 1 is a PROM (programmable read only memory) circuit and the voltage input terminal 2 is a high potential power supply V
If the write power supply Vpp further boosted than dd is the voltage input terminal to be connected, the P-channel MOS field effect transistor Q22 conducts and the write power supply Vp
p and the high-potential power supply Vdd are short-circuited. Therefore, as shown in FIG.
The configuration had to exclude the protection transistor on the side.

Therefore, the conventional input protection circuit of the voltage input terminal to which the write power supply Vpp is connected has a lower positive electrostatic breakdown voltage than a general signal terminal.

SUMMARY OF THE INVENTION It is an object of the present invention to secure a short circuit with respect to the high potential power supply Vdd even when a voltage higher than the high potential power supply Vdd is applied to the voltage input terminal during normal operation while securing the electrostatic withstand voltage of the voltage input terminal. An object of the present invention is to provide an input protection circuit that does not occur.

[0007]

The configuration of the input protection circuit according to the present invention comprises a discharge circuit disposed between a voltage input terminal for inputting a voltage supplied from the outside to an internal circuit and a power supply; A voltage detection circuit for detecting a voltage of a voltage input terminal, wherein the voltage detection circuit comprises:
When the voltage at the voltage input terminal exceeds a reference voltage, the operation of the discharge circuit is stopped.

In the discharge circuit, a field effect transistor includes a source / drain path connected between the voltage input terminal and the power supply, and a gate electrode and a back gate electrode connected to the power supply via a resistor. It is characterized by having.

In the discharge circuit, one end of a source / drain path is connected to the voltage input terminal, and the other end of the source / drain path is connected to the power supply via a first diode in a reverse bias direction. A gate electrode and a back gate electrode are provided with a field effect transistor connected to the power supply via a second diode in a reverse bias direction.

[0010] Further, the configuration of the discharge circuit includes a switch means for applying a voltage of the voltage input terminal to the gate electrode of the field effect transistor when the discharge circuit is turned on by an output signal of the voltage detection circuit. And

Further, the voltage detecting circuit is characterized in that when the voltage of the voltage input terminal exceeds the reference voltage, the switch means is turned on.

Further, the reference voltage is a voltage obtained by adding a threshold value of the field effect transistor to a voltage of the power supply.

[0013]

Next, an input protection circuit according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a configuration diagram of an input protection circuit according to a first embodiment of the present invention, and FIG. 2 is a configuration diagram of a voltage detection circuit of the input protection circuit according to the first embodiment of the present invention. FIG. 3 shows the first embodiment of the present invention.
FIG. 9 is an explanatory diagram of a cross-sectional structure of a main part of the input protection circuit according to the embodiment. 1 and 3, the same components as those of the conventional input protection circuit shown in FIG. 7 are denoted by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 1, an input protection circuit according to a first embodiment of the present invention comprises a discharge circuit 3 and a voltage detection circuit 4.
It is composed of

The discharge circuit 3 includes P-channel MOS field effect transistors Q2 and Q3 and a resistor R2.
The source electrode 23 of the P-channel MOS field effect transistor Q2 is connected to the high potential power supply Vdd, and the gate electrode 21
And the back gate electrode 24 are connected to each other, and further connected to a high potential power supply Vdd via a resistor R2.

The drain electrode 32 of the P-channel MOS field effect transistor Q3 is connected to the back gate electrode 34, and the source electrode 33 of the P-channel MOS field effect transistor Q3 is connected to the gate electrode 21 of the P-channel MOS field effect transistor Q2. It is connected.

P channel MOS field effect transistor Q
2 functions as an electrostatic discharge element and is a P-channel MOS
Field effect transistor Q3 functions as switching means for switching the gate voltage of P channel MOS field effect transistor Q2.

As an example, the voltage detecting circuit 4 includes a voltage comparator 7 and a reference voltage 8 as shown in FIG. The positive input terminal of the voltage comparator 7 is connected to the input terminal 5, the negative input terminal of the voltage comparator 7 is connected to the reference voltage 8, and the output terminal of the voltage comparator 7 is connected to the output terminal 6.

The reference voltage 8 is a voltage with respect to the low potential power supply Vss. The voltage comparator 7 compares the voltage input to the input terminal 5 with the reference voltage 8, and when the voltage at the input terminal 5 is lower than the reference voltage 8, The voltage of the high potential power supply Vdd is output to the output terminal 6
When the voltage of the input terminal 5 is higher than the reference voltage 8, the voltage of the low potential power supply Vss is output to the output terminal 6.

Here, the reference voltage 8 is set to a voltage (Vdd + Vtp) obtained by adding the threshold voltage Vtp of the P-channel MOS field effect transistor Q2 to the voltage of the high potential power supply Vdd.

The drain electrode 22 of the P-channel MOS field effect transistor Q2 of the discharge circuit 3 is connected to the voltage input terminal 2, and the drain electrode 32 of the P-channel MOS field effect transistor Q3 is connected to one end of the resistor R1 on the side of the internal circuit 1. The input terminal 5 of the voltage detection circuit 4 is connected to one end of the resistor R1 on the side of the internal circuit 1, and the output terminal 6 is connected to the P-channel MOS field effect transistor Q3 of the discharge circuit 3.
Is connected to the gate electrode 31.

As shown in FIG. 3, the discharge circuit 3 is formed on a P substrate 40 which is a semiconductor integrated circuit substrate.
The P substrate 40 is connected to a low potential power supply Vss.

P channel MOS field effect transistor Q
2 is formed in an N well 25, the N well 25 has a back gate electrode 24 of the same potential, and a P channel MOS field effect transistor Q3 is formed in an N well 35;
The N well 35 has a back gate electrode 34 of the same potential.

Next, the operation of the input protection circuit according to the first embodiment of the present invention will be described with reference to FIGS. 1, 2, 3 and 4. FIG. 4 is an explanatory diagram of the operation of the input protection circuit according to the first embodiment of the present invention, showing the voltage waveform of each part, the voltage V1 indicates the voltage of the voltage input terminal 2, and the voltage V1
1 'indicates a voltage at one end of the resistor R1 on the side of the internal circuit 1, a voltage V2 indicates a voltage of the gate electrode 21 of the P-channel MOS field-effect transistor Q2, and a voltage V3 indicates a P-channel M
It shows the voltage of the gate electrode 31 of the OS field effect transistor Q3, the current I1 shows the current flowing through the P-channel MOS field effect transistor Q2, the vertical axis shows the potential, and the horizontal axis shows time.

Although not shown, the voltage input terminal 2
Vdd from time t1 and Vpp from time t3 to time t4
(> Vdd), PRO that becomes Vdd after time t6
A write pulse voltage of the M write power supply is input.

First, before the time t1, no write pulse voltage is input, and the voltage V1 is Vdd.
Since the input resistance of the internal circuit 1 is high, the voltage drop due to the resistor R1 can be ignored, and the voltage V1 'is also Vdd.

Therefore, since the voltage of the input terminal 5 of the voltage detection circuit 4 is lower than the reference voltage 8 (Vdd + Vtp), the output terminal 6 outputs Vdd, and the voltage V3 also becomes Vdd.
P channel MOS field effect transistor Q3 is off.

Since the gate electrode 21 of the P-channel MOS field effect transistor Q2 is pulled up to the high potential power supply Vdd by the resistor R2, the voltage V2 is also Vdd.
, And the P-channel MOS field effect transistor Q2 remains off. Therefore, the current I1 is zero.

Next, at time t1, the write pulse voltage rises, and at time t2, the voltage V1 (= voltage V1 ') becomes Vdd.
When the voltage exceeds + Vtp, the voltage at the input terminal 5 of the voltage detection circuit 4 is higher than the reference voltage 8 (Vdd + Vtp), so that the output terminal 6 outputs the voltage of the low-potential power supply Vss and the voltage V3
Becomes Vss, and the P-channel MOS field effect transistor Q3 is turned on.

Therefore, the voltage V1 (= voltage V1 ') is
After lapse of time t3 or t4, which is pp, the voltage falls and Vd again.
Until the time t5 when d + Vtp is reached, the voltage V2 is always equal to the voltage V1 'and the gate voltage and the drain voltage of the P-channel MOS field-effect transistor Q2 are always equal, so that the P-channel MOS field-effect transistor Q2
Never goes on. Therefore, the current I1 is zero.

Note that the reference voltage 8 is set to a voltage (Vdd + Vt).
The reason for setting to p) is that if the P-channel MOS field-effect transistor Q3 does not exist, the voltage (Vdd
+ Vtp) and the P-channel MOS field effect transistor Q
2, the gate voltage of the P-channel MOS field-effect transistor Q2 is switched by the P-channel MOS field-effect transistor Q3 with this voltage as a boundary.

Further, after the time t5, the voltage of the input terminal 5 of the voltage detection circuit 4 becomes the reference voltage 8 (Vdd + Vt).
p), the output terminal 6 outputs the voltage of the high potential power supply Vdd again, the voltage V3 also becomes Vdd, and P
The channel MOS field effect transistor Q3 is turned off.

Since the voltage V2 also becomes Vdd, the P-channel MOS field effect transistor Q2 remains off. Therefore, the current I1 is zero.

As described above, since the gate voltage of the P-channel MOS field effect transistor Q2 is Vdd until time t2 and after time t5, the P-channel MOS field effect transistor Q2 functions as an electrostatic discharge element. I do.

That is, when positive static electricity exceeding the high potential power supply Vdd is input to the voltage input terminal 2 with respect to the low potential power supply Vss, the P-channel MOS field effect transistor Q
The emitter-collector path of the parasitic PNP bipolar transistor having the drain electrode 22 as the emitter electrode, the source electrode 23 as the collector electrode, and the back gate electrode 24 as the base electrode conducts, and the P-channel MOS field-effect transistor Q2 turns on. As a result, the static electricity is discharged to the high potential power supply Vdd, and the withstand voltage of the static electricity of the voltage input terminal 2 is secured.

Further, during the writing operation from time t2 to time t5, even if a high voltage Vpp exceeding the high potential power supply Vdd is input to the voltage input terminal 2, the P-channel MOS field effect transistor Q2, which is an electrostatic discharge element, The off state is always maintained, and no short circuit occurs to the high potential power supply Vdd.

FIG. 5 is a configuration diagram of an input protection circuit according to a second embodiment of the present invention. In FIG. 5, the same components as those of the input protection circuit according to the first embodiment of the present invention shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 5, the input protection circuit according to the second embodiment of the present invention comprises a discharge circuit 13 and a voltage detection circuit 4.

In the discharge circuit 13, a different part from the discharge circuit 3 of the input protection circuit according to the first embodiment of the present invention shown in FIG. 1 is that a resistor R2 is replaced by a diode D1 and a P-channel MOS field effect transistor. This is a portion where the diode D2 is added to the source electrode of Q12.

P channel MOS field effect transistor Q
Twelve gate electrodes and back gate electrodes are both connected to the cathode electrode of the diode D1, and the anode electrode of the diode D1 is connected to the high potential power supply Vdd.

The source electrode of the P-channel MOS field effect transistor Q12 is connected to the cathode electrode of the diode D2, and the anode electrode of the diode D2 is connected to the high potential power supply Vdd.

The P-channel MOS field-effect transistor Q13 is the same as the P-channel MOS field-effect transistor Q3 of the discharge circuit 3 of the input protection circuit according to the first embodiment of the present invention shown in FIG.

Next, the operation of the input protection circuit according to the second embodiment of the present invention will be described with reference to FIG. The operation of P-channel MOS field-effect transistors Q12 and Q13 when a write pulse voltage is applied to voltage input terminal 2 differs from the operation of the input protection circuit of the first embodiment of the present invention shown in FIG. , Diodes D1, D2
Is set to Vd, and when the P-channel MOS field-effect transistor Q13 is off, the P-channel MOS
The pull-up voltage of the gate electrode and the back gate electrode of the OS field effect transistor Q12 becomes Vdd-Vd,
Diode D for compensating for the voltage drop of diode D1
2, the P-channel MOS field effect transistor Q1
The voltage of the source electrode of No. 2 is also only the portion where Vdd-Vd is obtained.

Accordingly, the voltage V11 is the voltage at the voltage input terminal 2, the voltage V11 'is the voltage at one end of the resistor R1 on the side of the internal circuit 1, the voltage V12 is the gate voltage of the P-channel MOS field effect transistor Q12, and the voltage V13 Is the gate voltage of the P-channel MOS field-effect transistor Q13 and the current I11 is the current flowing through the P-channel MOS field-effect transistor Q12, the voltage V11 is equal to the voltage V1 shown in FIG. 1, and the voltage V11 'is also equal to the voltage V1'. , Voltage V12 becomes voltage V2-Vd when P-channel MOS field effect transistor Q13 is off, voltage V13 is equal to voltage V3, and current I11 is also equal to current I1.

As described above, even when the high voltage Vpp exceeding the high potential power supply Vdd is input to the voltage input terminal 2, the P-channel MOS field effect transistor Q12, which is an electrostatic discharge element, is always kept in the off state. High potential power supply Vd
No short circuit occurs for d.

When positive static electricity exceeding the high potential power supply Vdd is applied to the voltage input terminal 2 with respect to the low potential power supply Vss, the drain electrode of the P-channel MOS field effect transistor Q12 is used as the emitter electrode, and the source electrode is used as the source electrode. Is a collector electrode, the emitter-collector path of a parasitic PNP bipolar transistor having a back gate electrode as a base electrode is conductive, the P-channel MOS field effect transistor Q12 is turned on and the source-drain path is conductive,
Further, the breakdown of the diode D2 discharges the static electricity to the high potential power supply Vdd, and the static electricity withstand voltage of the voltage input terminal 2 is secured.

Further, by replacing the resistor R2 with the diode D1, when the voltage V12 rises to Vdd or more, the diode D1 becomes reverse-biased and no bias current flows, so that the input resistance of the voltage input terminal can be increased. it can.

[0048]

As described above, the first effect of the input protection circuit according to the present invention is that the electrostatic withstand voltage of the voltage input terminal can be ensured, and that the voltage input terminal can be used during normal operation such as PROM write operation. High potential power supply Vd
Even when a voltage higher than d is applied, a short circuit between the voltage input terminal and the high-potential power supply Vdd does not occur.

A second effect is that the input resistance of the voltage input terminal can be increased during a normal operation such as a PROM write operation.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an input protection circuit according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a voltage detection circuit of the input protection circuit according to the first embodiment of the present invention.

FIG. 3 is an explanatory diagram of a cross-sectional structure of a main part of the input protection circuit according to the first embodiment of the present invention.

FIG. 4 is an explanatory diagram of an operation of the input protection circuit according to the first embodiment of the present invention.

FIG. 5 is a configuration diagram of an input protection circuit according to a second embodiment of the present invention.

FIG. 6 is a configuration diagram of a conventional input protection circuit.

FIG. 7 is a configuration diagram of another conventional input protection circuit.

[Explanation of symbols]

Reference Signs List 1 internal circuit 2, 5, 6 terminal 3, 13 discharge circuit 4 voltage detection circuit 7 voltage comparator 8 reference voltage 21, 31 gate electrode 22, 32 drain electrode 23, 33 source electrode 24, 34 back gate electrode 25, 35N Well 40 P substrate Q1 N channel MOS field effect transistor Q2, Q3, Q12, Q13, Q22 P channel M
OS field effect transistor D1, D2 Diode R1, R2 Resistance

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference)

Claims (6)

[Claims] A discharge circuit provided between a voltage input terminal for inputting a voltage supplied from the outside to an internal circuit and a power supply; and a voltage detection circuit for detecting a voltage of the voltage input terminal. An input protection circuit, wherein the voltage detection circuit stops the operation of the discharge circuit when the voltage of the voltage input terminal exceeds a reference voltage. 2. The discharge circuit includes a field effect transistor having a source / drain path connected between the voltage input terminal and the power supply, and a gate electrode and a back gate electrode connected to the power supply via a resistor. The input protection circuit according to claim 1, wherein: 3. The discharge circuit, wherein one end of a source / drain path is connected to the voltage input terminal, and the other end of the source / drain path is connected to the power supply via a first diode in a reverse bias direction. 2. The input protection circuit according to claim 1, wherein an electrode and a back gate electrode include a field effect transistor connected to the power supply via a second diode in a reverse bias direction. 4. The discharge circuit further comprises switch means for applying a voltage of the voltage input terminal to the gate electrode of the field effect transistor when the discharge circuit is turned on by an output signal of the voltage detection circuit. The input protection circuit according to claim 2 or 3. 5. The input protection circuit according to claim 4, wherein said voltage detection circuit turns on said switch means when the voltage of said voltage input terminal exceeds said reference voltage. 6. The input protection circuit according to claim 1, wherein said reference voltage is a voltage obtained by adding a threshold value of said field effect transistor to a voltage of said power supply.