JP2001125539A - Picture display device provided with picture data correcting function - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a picture display device capable of making the quantity of correction data which are to be held in a buffer small and capable of correcting picture data with simple circuit constitution. SOLUTION: This device is a picture display device which is provided with a horizontal driving part supplying driving currents to respective columns of a display part in accordance with picture data corresponding to selected rows, a picture data correcting part which corrects the picture data inputted from the outside in accordance with variations of light emitting elements for every pixel and outputs the corrected picture data to the driving part and a correction data storage part storing correction data for correction and the correcting part reads out correction data equivalent to the amount of data of a row from the storage part every time the part outputs the picture data posterior to the correction by an amount equivalent of a row to the driving part. As a result, the device can make the quantity of correction data which are to be temporarily stored in the correcting small and the device can correct the picture data with simple constitution without using a RAM having a large capacity or the like as a buffer memory.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display device in which a plurality of light emitting elements are arranged in a matrix, and more particularly, to an image display device having a function of correcting image data according to variations in characteristics of light emitting elements. About.

[0002]

2. Description of the Related Art Today, high-luminance light-emitting elements such as light-emitting diodes (LEDs) have been developed for RGB, respectively, and large self-luminous full-color displays have been manufactured. Above all, LED displays have features such as light weight, thinness and low power consumption, and the demand for LED displays is rapidly increasing as large displays that can be used outdoors.

[0003] As a driving method of the LED display,
Generally, a dynamic drive system is used. For example, in the case of an LED display composed of an m × n dot matrix, the anode terminals of the LEDs located in each row are commonly connected to one common source line, and the cathode terminals of the LEDs located in each column are connected to one current line. Are connected in common. The m rows of common source lines are sequentially turned on at a predetermined cycle, and an LED drive current is supplied to n columns of current lines according to image data corresponding to the turned-on lines. As a result, an LED drive current corresponding to the image data is applied to the LED of each pixel, and an image is displayed.

[0004] In the case of a large-sized LED display to be installed outdoors, it is generally constituted by combining a plurality of LED units, and each LED unit displays each part of the full screen data. In the LED unit, light emitting diodes each having a set of RGB are arranged in a dot matrix on a substrate, and each unit performs the same operation as the above-described LED display. In a large large LED display, for example,
A total of 120,000 LED units (0x400) are used.

In order for image data to be accurately reproduced on an LED display, it is necessary that the light output characteristics (drive current-luminance characteristics) of each LED be uniform. However, LEDs are formed on a wafer by semiconductor technology, but the light output characteristics vary depending on the production lot, wafer, or chip. Therefore, it is necessary to correct the size of the image data according to the variation in the LED light output characteristics of each pixel.

Conventionally, image data has been corrected, for example, as follows. FIG. 5 is a block diagram showing an example of a conventional LED display. In FIG. 5, 1
1 is an LED matrix of m rows and n columns, 15 is a control circuit,
26 is a microprocessor (MPU), 17 is a ROM for storing correction data, 14 is a common drive circuit, 18 is a horizontal drive circuit, 29 is a correction circuit for correcting image data, 3
0 represents a RAM for temporarily storing correction data. The horizontal drive circuit 18, the correction circuit 29, and the RAM 30
An LED driving IC 32 for each column of the matrix 11
(K) (k = 1 to n).

First, before the screen is turned on, correction data for m × n pixels input to the ROM 17 is transferred to a buffer capable of high-speed reading. RAM 30 in the buffer
Is used. The transfer of the correction data is performed as follows. First, the MPU 26 reads the correction data input to the ROM 17. The MPU 26
The LED drive ICs 32 (k) are sequentially designated via the address bus 33, and one column of correction data corresponding to the designated column is designated.
That is, m pixels are sequentially output. The output correction data is supplied to each drive IC 32 (k) via the correction data bus 34.
And stored in the RAM 30 in the drive IC 32 (k).

When the LED is turned on, the correction circuit 29
2 is sequentially read out, and image data (IMDATA) input based on the correction data is read out.
The image data is corrected by increasing or decreasing the value for each pixel. The corrected image data is output to the drive circuit 18, and the drive circuit 18 supplies a drive current to each LED based on the corrected image data.

[0009]

However, the conventional L
In an ED display, a RAM 3 serving as a buffer
Since the correction data for a total of m × n pixels must be stored in 0, a large capacity RAM is required as the number of pixels of the display increases, and the operation of reading the correction data from the RAM 30 to the correction circuit 29 becomes complicated. There was a problem of doing. Further, n drive ICs 32 (1) to 32 (n)
It is necessary to branch and connect the address bus 33 and the data bus 34 to each of them, so that there is a problem that wiring becomes complicated and a peripheral circuit becomes large in area.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to provide an image display element capable of correcting image data with a small amount of data held in a buffer and a simple circuit configuration. Aim.

[0011]

According to a first aspect of the present invention, there is provided an image display apparatus comprising:
A display section in which a plurality of light emitting elements are arranged in a matrix of m rows and n columns; (b) a vertical drive section for applying a current to each row of the display section while sequentially selecting each row; A horizontal drive unit that supplies a drive current to each column of the display unit according to image data corresponding to the selected row;
(D) an image data correction unit that corrects image data input from the outside in accordance with variations in light emitting element characteristics of each pixel and outputs the corrected data to the horizontal drive unit; and (e) corrects the correction data for the correction. An image display device comprising: a stored correction data storage unit, wherein the image data correction unit outputs one line of corrected image data to the horizontal drive unit each time the correction data storage unit outputs one line. It is characterized in that the correction data for a row is read. As a result, the amount of correction data to be temporarily stored in the image data correction unit can be reduced, and image data can be corrected with a simple circuit configuration without using a large-capacity RAM or the like as a buffer memory. .

According to a second aspect of the present invention, the image data correction unit includes a buffer memory for storing at least one line of correction data, and outputs the corrected image data for one line to the horizontal drive unit. During this period, the next one line of correction data is read from the correction data storage unit. This can prevent a display time lag between lines due to image data correction.

According to a third aspect of the present invention, the buffer memory includes a shift register, and reads the correction data serially one bit at a time via the shift register. This eliminates the need for branching the data bus for transferring the correction data from the correction data storage unit to the buffer memory of each column, and eliminates the need for an address bus for specifying the buffer memory. Therefore, the wiring area can be reduced, and the degree of freedom of wiring can be improved.

According to a fourth aspect of the present invention, the buffer memory includes two stages of registers connected to each other, and the second register outputs the next one while the first register outputs the correction data for one row. It is characterized in that the correction data for a row is read, and the second register transfers the correction data to the first register every time the output and the reading of the correction data for one row are completed. Thus, image data can be corrected with a simple circuit configuration.

According to a fifth aspect of the present invention, the second register comprises a shift register, and the correction data is serially stored as one.
It is characterized by reading while shifting bit by bit.
This eliminates the need for branching the data bus for transferring correction data, and eliminates the need for an address bus for specifying a buffer memory.

The invention according to claim 6 is characterized in that the light emitting element is a light emitting diode. This allows
It is possible to simplify the peripheral circuit configuration of the LED display and reduce the size of the display.

The invention according to claim 7 is characterized in that the image display device divides and displays a part of the entire image display. Since the image display device of the present invention can simplify the peripheral circuit configuration, it is suitable for an image display device that displays a part of the entire image display, for example, an LED unit used for a large LED display.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram schematically showing an example of the image display device according to the present invention.
The image display device shown in FIG.
A display unit 1 arranged in a matrix of rows and n columns;
(B) a vertical drive unit 4 that applies a current to each row of the display unit 1 while sequentially selecting each row; and (c) a column of the display unit 1 according to image data corresponding to the selected row. And (d) image data (IMDATA) input from outside, which is corrected according to the variation in the light emitting element characteristics of each pixel, and output to the horizontal drive unit 8. The control unit 5 includes a correction unit 9 and (e) a correction data storage unit 7 that stores correction data for the correction. The operation of each component is controlled by the control unit 5.

The image data correction unit 9 reads the correction data (CRDATA) from the correction data storage unit 7 via the control unit 5, and based on the correction data, the image data (IMDATA) input via the control unit 5. Is corrected and output to the horizontal drive unit 8. Reading of correction data is mxn
Rather than performing the processing for the pixels at once, the processing is performed sequentially for one row (for n pixels) in parallel with the output of the image data.

When the image data is a combination of still images, the image data can be corrected without providing any buffer memory. However, when the image data is a moving image, the display time lag between lines is reduced. 1 to prevent
It is preferable to provide a buffer memory that can store two rows of correction data. The buffer memory 10 can be composed of, for example, two-stage registers 20 and 21 connected to each other.

The reading of the correction data is performed, for example, as follows. The image data correction unit 9 includes a buffer memory 10 including upper and lower two registers 20 and 21 connected to each other, while the first register 20 outputs one line of correction data to the correction circuit 19. Then, the next one line of correction data is read into the second register 21. First
When the output of the correction data by the register 20 and the reading of the correction data by the second register 21 have been completed for one row, the contents stored in the second register 21 are stored in the first register 2.
0 is transferred.

First register 20 and second register 2
For example, 1 may be a D flip-flop in which the number of data is equal to the number of data for one row of the screen (= n pixels × the number of bits per pixel a). Second register 21
Is preferably a shift register in which flip-flops are connected in cascade so that the input wiring of the correction data can be simplified. As a result, the correction data input to the leftmost flip-flop of the second register 21 is sequentially transferred to the right flip-flop in synchronization with the clock (CLK) timing, and is read into the second register 21. Therefore, it is sufficient if there is a wiring for supplying a clock to each flip-flop, and it is not necessary to branch the correction data input bus for each column.

FIG. 2 is a block diagram showing a specific configuration of the image display device shown in FIG. First, the configuration of each unit will be described. The LED dot matrix 11 serving as a display unit is composed of LEDs arranged in a matrix of m rows and n columns, and the anode terminals of the LEDs located in each row are commonly connected to one common source line, and the LEDs located in each column are arranged. Are commonly connected to one current line. The common driver 14, which is a vertical drive unit,
The current source switching circuit includes m switch circuits and a current source, and supplies a current to an LED connected to the common line by connecting the common source line to the current source. The drive circuit 18 serving as a horizontal drive unit includes a constant current control circuit that performs ON-OFF control of a drive current applied to each column in accordance with the gradation width of the image data output from the correction circuit 19.

The image data correction section corrects the sequentially input image data by one line and outputs the corrected data.
Register 2 which is a buffer memory for storing correction data
0 and a shift register 21. The register 20 and the shift register 21 have flip-flops corresponding to the number of pixel bits per column. Each flip-flop of the register 20 is connected to a flip-flop of the corresponding shift register 21. The control unit includes a control circuit (CTL) 15 and a DMAC 16. The ROM 17 serving as a correction data storage unit includes an EEPROM or the like,
Brightness correction data for correcting a brightness difference due to a variation in light output characteristics of each LED in the LED dot matrix 11 is stored. The correction data is data for controlling the drive current of each LED for each pixel and each color. Instead of the drive current, the data may be data for controlling the lighting time of the LED or a combination of the lighting time and the drive current.

Drive circuit 18, correction circuit 19, register 2
0 and the shift register 21 are provided for each column of the LED dot matrix 11, and are stored in the driver IC 22 (k) for each column (k = 1 to
n). The shift registers 21 in each column are connected to each other so that data can be shifted. In addition, in order to reduce the number of driver ICs, an appropriate number of driving circuits 18
And the like may be collectively stored in the driver IC 22.

The writing of the correction data to the ROM 17 and the reading of the correction data to the outside can be performed independently of the reception of the image data via the SCI 3 which is a serial communication interface. Note that writing to the ROM 17 can be performed by a method of directly connecting to the ROM 17 and transferring data, or can be performed via various interfaces such as a parallel bus. When writing data to the ROM 17 during reading of the correction data, D
By interrupting the transfer of the MAC 6 and giving priority to data reception via the SCI, it is possible to control access conflicts to the ROM 17.

The flow of image data in the present embodiment is as follows. Image data (IMDATA)
CTL15, and the correction circuit 19
After being corrected for each row in the correction circuit 19, it is output to the drive circuit 18.

Next, the flow of the correction data will be described with reference to the timing chart of FIG. For simplicity, FIG. 3 shows the timing when three common source lines # 0 to # 2 are sequentially turned on.

When the vertical and horizontal image timing data Vsync and Hsync are input to the CTL 15, reading of the correction data of the line # 0 into the shift register 21 starts. Note that Vsync input to the CTL 15 is L
The SYNC signal is sent to the common driver 14 as an INE ADR signal, and the Hsync signal is sent to the drive circuit 18 and the correction circuit 19 as a BLANK signal.

(1) First, the CTL 15
0 read start address (ADDR
ESS) is input to the DMAC 16. DAMC16
Writes the read start address via the data input / output bus DIO while transmitting the write enable signal XWE to the ROM 17. Incidentally, as schematically shown in FIG.
The read start address indicates the start address of the correction data corresponding to the selected line in the ROM memory map. C
The TL 15 generates a read start address corresponding to the recognized line number based on Vsync and Hsync.

(2) When the writing of the address is completed, the DMAC 16 transmits the read enable signal XOE, and sends the read enable signal XOE from the ROM 17 to the line # 0 via the bus DIO.
Read out the correction data for use. In the ROM 17, XOE l
The correction data is sequentially read in accordance with the number of ow pulse inputs.

(3) The correction data (CRDATA) of line # 0 read by the DMAC 16 is stored in the driver IC
22 (k) is transferred to the shift register 21. The correction data is transferred to the shift register 21 while being sequentially shifted bit by bit in synchronization with the clock CLK.

On the other hand, while the correction data of the line # 0 is being read into the shift register 21,
Holds the correction data of the last line, line # 2. The correction data of the line # 2 held in the register 20 is output to the drive circuit 18 at the same time as being held, and the LED of the line # 2 is turned on.

When the next Hsync is input, a latch signal (LATCH) is transmitted from the DMAC 16 to the register 20, and the correction data of the line # 0 stored in the shift register 21 is transferred to the register 20 in a lump.
LED starts to be turned on. And from CTL15 to D
The read start address of the line # 1 is input to the MAC 16, and the DMAC 16 reads the correction data of the line # 1 from the ROM 17 by the same operation as described above, and writes the read correction data of the line # 1 to the shift register 21.

In this way, while the previous row is lit,
Next, the input of the correction data for each pixel of the row to be turned on is completed. The correction data input to the shift register 21 is transferred to the register 20 immediately before switching of the lighting row, and is held in the register 20. Based on the held correction data, the correction circuit 19 corrects the image data, and corrects the luminance variation of each LED on the line being driven. By repeating these operations sequentially, the brightness of the LEDs is corrected over the entire screen.

The transfer of the correction data by the shift register 21 needs to be completed within the lighting time of one row. For this reason, the embodiment in which data transfer is performed by the shift register is suitable for an image display device in which the number of image data bits per row is not so large, such as an LED unit used for a large-screen LED display.

Although the case where the ROM 17 is a serial EEPROM from which data is read serially has been described, an EEPROM having an n-bit address and data bus may be used. Also, DMAC16
Although the example in which the correction data transfer between the shift register 21 and the shift register 21 is performed via the serial bus has been described, the transfer may be performed using the parallel bus.

When the LED display is full color, one pixel is composed of RGB three-color LEDs.
Similar correction can be performed for each of the GB image data.

[0039]

According to the present invention, each time the image data correction unit outputs one line of the corrected image data to the horizontal drive unit, one line of the correction data is read from the correction data storage unit. Need only hold the correction data for one row, and there is no need to use a large-capacity RAM or the like as a buffer memory. Further, since only one row of correction data is held, it is not necessary to specify an address when the correction circuit refers to the correction data, and the control signal is simplified. Further, since the circuit configuration of the image data correction unit is simplified, the peripheral circuit area can be reduced.

Further, if the correction data is read into the shift register while shifting the correction data serially one bit at a time,
There is no need to branch the data bus for transferring the correction data from the correction data storage unit to the buffer memory of each column, and it is only necessary to connect the shift registers of each driver IC in series. Further, an address bus for specifying the buffer memory is not required. Therefore, the circuit configuration can be simplified, the wiring area can be reduced, and the freedom of wiring can be improved.

Further, the data shift by the shift register can be completed within the lighting period of one row (for example, 10 msec) by dividing and displaying a part of the entire image display on the image display device.

[Brief description of the drawings]

FIG. 1 is a block diagram schematically showing a circuit configuration of an image display device according to the present invention.

FIG. 2 is a block diagram showing a circuit configuration of the image display device according to the present invention.

FIG. 3 is a timing chart illustrating a correction data transfer operation.

FIG. 4 is a schematic diagram showing the correspondence between control line numbers and read start addresses of a ROM.

FIG. 5 is a block diagram showing a circuit configuration of a conventional image display device.

[Description of Signs] 1 ... display unit, 2 ... image data input unit, 4 ... vertical drive unit,
5 control unit, 7 correction data storage unit, 8 horizontal drive unit,
9: image data correction unit, 10: buffer memory, 11 ...
LED dot matrix, 12 ... common control line,
13: Serial communication interface, 14: Common driver, 15: Control circuit, 16: DMAC, 17: RO
M, 18 drive circuit, 19 correction circuit, 20 first register, 21 second register, 22 (1) to 22
(N) Driver IC

Claims (7)

[Claims] 1. A display section comprising (a) a plurality of light-emitting elements arranged in a matrix of m rows and n columns, and (b) applying a current to each row of the display section while sequentially selecting each row. A vertical drive unit, (c) a horizontal drive unit that supplies a drive current to each column of the display unit according to the image data corresponding to the selected row, and (d) image data input from outside. An image data correction unit that corrects according to variations in the light emitting element characteristics of each pixel and outputs the corrected data to the horizontal drive unit;
A correction data storage unit storing correction data for the correction, wherein the image data correction unit outputs one line of the corrected image data to the horizontal drive unit each time An image display device for reading one line of correction data from the correction data storage unit. 2. The image data correction unit according to claim 1, wherein
A buffer memory for storing correction data for one row is provided, and while the corrected image data is output to the horizontal drive unit for one row, the correction data for the next one row is read from the correction data storage unit. The image display device according to claim 1, wherein: 3. The image display device according to claim 2, wherein the buffer memory includes a shift register, and reads the correction data serially via the shift register while shifting the data one bit at a time. 4. The buffer memory according to claim 2, wherein said buffer memories are connected to each other.
While the first register outputs the correction data for one row, the second register reads the correction data for the next row, and the output and reading of the correction data are completed for one row. 3. The image display device according to claim 2, wherein the second register transfers the correction data to the first register every time. 5. The image display device according to claim 4, wherein said second register comprises a shift register, and reads the correction data serially by shifting one bit at a time. 6. The image display device according to claim 1, wherein the light emitting element is a light emitting diode. 7. The image display device according to claim 1, wherein a part of the entire image display is divided and displayed.