JP2001119702A - Video signal receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a video signal receiver that is provided on a receiver side of a video signal transmission system where a high resolution video signal is divided into a low resolution video signal (1st video signal) and a high resolution component signal (2nd video signal), they are separately encoded and the encoded signals are transmitting and that independently decodes the 1st video signal and the 2nd video signal and can composite the original high resolution signal from the decoded 1st video signal and the decoded 2nd video signal. SOLUTION: A vertical synchronizing signal generated in a 1st decoder 103 is given to a 2nd decoder 104 and the 2nd decoder 104 adjusts decoding timing and output timing of the 2nd video signal according to the vertical synchronizing signal. The vertical synchronizing signal given from the 1st decoder 103 to the 2nd decoder 104 has precision in the unit of pixels and the decoded 1st video signal and the decoded 2nd video signal can be synchronized in the unit of pixels in each frame (that is, in-frame synchronization).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal receiving apparatus, and more particularly, to a video signal transmitting system for transmitting a video signal after encoding the video signal with high efficiency. The present invention relates to a video signal receiving device that receives a video signal and decodes the original video signal.

[0002]

2. Description of the Related Art At present, MPEG2 is standardized as a standard high-efficiency encoding and compression system for TV signals. MPEG
If MPEG2 is used, it is possible to record or transmit high-quality video at a relatively low data rate, and it can be compressed to various data rates. Are also being considered. When transmitting a video signal (high-resolution video signal) to the MPEG2, a high-resolution component signal composed of a high-resolution component of the video signal and a low-resolution video signal obtained by removing the high-resolution component from the video signal Are separately transmitted, and the receiving side converts the low-resolution video signal and the high-resolution component video signal into an original video signal (high-resolution video signal).
Is defined. However, this method has a problem that decoding of the high-resolution component signal is complicated because information obtained in the process of decoding the low-resolution video signal is used for decoding the high-resolution component signal. Conventionally, in order to solve this problem, a video signal transmission device capable of independently decoding a low-resolution video signal and a high-resolution component signal has been proposed (for example, Japanese Patent Application Laid-Open No. H10-33664).
No. 5).

FIG. 11 is a block diagram showing an example of the configuration (on the transmission side) of the conventional video signal transmission apparatus. FIG.
1, a conventional video signal transmission apparatus includes an input terminal 1101 for inputting a video signal, a divider 1102 for dividing the input signal into two types of video signals, and a first device for encoding the two types of video signals. An encoder 1103, a second encoder 1104, and a synchronization information adder 1105 for adding synchronization information for synchronizing frames between two types of video signals.
And a first output terminal 1106 and a second output terminal 1107 for outputting two types of encoded video signals to different transmission channels. The operation of the conventional video signal transmission device configured as described above will be described below.

A video signal (high-resolution video signal) input from an input terminal 1101 is input to a splitter 1102,
The video signal is divided into a first video signal and a second video signal. Here, the high-resolution video signal is, for example, a signal having 1280 horizontal pixels, 720 vertical lines, and a frame frequency of 60 Hz. The first video signal is obtained by down-converting the high-resolution video signal using a band limiting filter or the like. Low-resolution video signal (hereinafter referred to as low-resolution video signal; for example, 720 horizontal pixels, 480 vertical lines, 60H frame frequency)
z signal), and the second video signal is input terminal 1101
Is a signal having a high-resolution component corresponding to the difference between the high-resolution video signal input from the controller and the video signal obtained by up-converting the first video signal by an interpolation circuit or the like (hereinafter, a high-resolution component signal).

[0005] The first video signal output from the divider 1102 is encoded by a first encoder 1103, and the second video signal is encoded by a second encoder 1104. The first video signal coded by the first coder 1103 and the second video signal coded by the second coder 1104 are input to a synchronization information adder 1105, and the first video signal is received on the receiving side. Synchronization information for enabling frame synchronization between the signal and the second video signal is added. Thus, the first video signal and the second video signal to which the synchronization information has been added are output from the synchronization information adder 1105 to different transmission channels via the first output terminal 1106 and the second output terminal 1107.

[0006]

As described above, in the conventional video signal transmission apparatus, the video signal (high-resolution video signal) is converted into a low-resolution video signal (first video signal) and a high-resolution component signal (second video signal). Video signals), separately encoded, and transmitted with synchronization information added. Thereby, the receiving side decodes the first video signal and the second video signal independently of each other based on the synchronization information, and extracts the original video signal from the decoded first video signal and the decoded second video signal. Is expected to be able to synthesize video signals (high-resolution video signals). However, it is not clear what kind of information the synchronization information is, and it is not known how to synchronize the first video signal and the second video signal at the time of decoding / combining. There was no proof that they could be obtained.

Therefore, an object of the present invention is to divide a high-resolution video signal into a low-resolution video signal (first video signal) and a high-resolution component signal (second video signal) and encode them separately. A first video signal and a second video signal are provided on a receiving side of a video signal transmission system that transmits the video signal, and decode the first video signal and the second video signal independently of each other. It is an object of the present invention to provide a video signal receiving apparatus capable of synthesizing a high-resolution video signal.

[0008]

According to a first aspect of the present invention, a high resolution video signal is converted into a low resolution video signal (hereinafter, a first video signal) and a high resolution component signal (hereinafter, a second video signal). Is provided on the receiving side of a video signal transmission system for separately encoding and transmitting the encoded first video signal and the encoded second video signal independently of each other. A video signal receiving apparatus for combining an original high-resolution video signal from a decoded first video signal and a decoded second video signal, wherein the first decoding unit decodes the encoded first video signal , A second decoding unit that decodes the encoded second video signal, a decoded first video signal output from the first decoding unit, and a decoded second video signal output from the second decoding unit And a combining unit for combining
The decoding unit is provided with a first timing generation unit that generates a decoding timing signal, a vertical synchronization signal and a horizontal synchronization signal, and a decoding timing signal, a vertical synchronization signal, and a horizontal synchronization signal generated by the first timing generation unit. A first decoding control unit that decodes the encoded first video signal according to the decoding timing signal and outputs the decoded first video signal according to the vertical synchronization signal and the horizontal synchronization signal. The second decoding unit is provided with a vertical synchronization signal generated by the first timing generation unit, and based on the vertical synchronization signal, a decoding timing signal generated by the first timing generation unit, a vertical synchronization signal, and a horizontal synchronization signal. A second timing generator for generating a decoding timing signal, a vertical synchronizing signal, and a horizontal synchronizing signal which are synchronized with the signal, and a second timing Decode timing signal grayed generating unit occurs, given a straight and horizontal synchronizing signals,
A second decoding control unit that decodes the encoded second video signal according to the decoding timing signal and outputs the decoded second video signal according to the vertical synchronization signal and the horizontal synchronization signal. Contains.

In the first invention, the vertical synchronization signal generated in the first decoding unit is passed to the second decoding unit, and the second decoding unit receives the second video signal based on the vertical synchronization signal. The decoding timing and the output timing of are adjusted.
The vertical synchronization signal passed from the first decoding unit to the second decoding unit has pixel accuracy, and therefore, the first video signal after decoding and the second video signal after decoding are divided into pixels in a frame as a unit. (Ie, intra-frame synchronization). Therefore, when the encoded first video signal input to the first decoding unit and the encoded second video signal input to the second decoding unit are inter-frame synchronized, The original high-resolution video signal can be synthesized from the first video signal and the decoded second video signal.

[0010] In a second aspect based on the first aspect, each frame constituting the coded first video signal and each frame constituting the coded second video signal are provided with the decoded second video signal. Synchronization information for synchronizing one video signal and the decoded second video signal between frames is provided, and
A synchronization information extracting unit configured to extract synchronization information from the encoded first video signal input to the decoding unit and the encoded second video signal input to the second decoding unit; The extraction unit further compares the two pieces of extracted synchronization information with each other, and as a result, the encoded first video signal input to the first decoding unit and the code input to the second decoding unit. When the decoded second video signal is shifted by one frame period or more, the decoded first video signal output from the first decoding unit and the decoded second video signal output from the second decoding unit. An inter-frame synchronization control signal for keeping a deviation from a video signal within one frame period is generated, and the first decoding control unit and / or the second decoding control unit is coded according to the inter-frame synchronization control signal. First video signal and / or encoded And the operation of decoding the second video signal 1
The feature is to stop or skip the frame period.

According to the second aspect, the deviation between the decoded first video signal and the decoded second video signal can be kept within one frame period. That is, the first video signal after decoding and the second video signal after decoding can be synchronized with each other in units of frames (that is, inter-frame synchronization). Even if the encoded first video signal and the encoded second video signal input to the second decoding unit are not synchronized between frames,
The original high-resolution video signal can be synthesized from the decoded first video signal and the decoded second video signal.

In a third aspect based on the first aspect, each frame constituting the encoded first video signal and each frame constituting the encoded second video signal are decoded by the decoding of the frame. Synchronization information describing timing and output timing associated with the reference clock of the video signal transmission system is added, and the encoded first video signal input to the first decoding unit and input to the second decoding unit are input. A synchronization information extraction unit for extracting synchronization information from the encoded second video signal to be encoded, and the synchronization information extraction unit further compares each of the extracted two synchronization information with a reference clock. , The coded first video signal input to the first decoding unit and / or the coded second video signal input to the second decoding unit are the reference clock and one frame period. In the case of upward deviation, the deviation between the decoded first video signal output from the first decoding unit and / or the decoded second video signal output from the second decoding unit and the reference clock is determined. A reference clock synchronization control signal for keeping within one frame period is generated, and the extracted two pieces of synchronization information are compared with each other. As a result, the encoded first video input to the first decoding unit If the signal and the encoded second video signal input to the second decoding unit are shifted by one frame period or more, the decoded first video signal output from the first decoding unit and the second video signal 2 generates an inter-frame synchronization control signal for keeping the deviation from the decoded second video signal output from the second decoding unit within one frame period, and the first decoding control unit and / or the second decoding control unit Reference clock synchronization control signal and Depending on the frame synchronizing control signals, and characterized in that one frame period stop or skip the operation for decoding the second video signal first video signal and / or coded encoded.

In the third aspect of the present invention, the decoded first video signal and the decoded second video signal are synchronized with the decoded first video signal and the decoded second video signal, respectively, while being synchronized with the reference clock.
The mutual deviation from the video signal can be kept within one frame period. That is, the first video signal after decoding and the second video signal after decoding can be synchronized with each other in units of frames (that is, inter-frame synchronization). Even when the decoded first video signal and the encoded second video signal input to the second decoding unit are not synchronized between frames, the decoded first video signal and the decoded second video signal The original high-resolution video signal can be synthesized from the video signal. Also, synchronization information for synchronizing the decoded first video signal and the decoded second video signal with the reference clock is used to convert the decoded first video signal and the decoded second video signal into frames. Since synchronization is performed between frames, there is no need to add synchronization information dedicated to inter-frame synchronization to each frame.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Prior to describing the embodiments of the present invention in detail, an outline thereof will be described for the purpose of facilitating understanding. MPEG2 has PTS and D as synchronization information.
There is a TS, and the receiving side has a PTS (Present
ation Time Stamp) or DTS (Dec)
A method of synchronizing a video signal and an audio signal using an “Olding Time Stamp” is specified. It is the following method. In the case of MPEG2, each frame of a video signal (video frame) and each frame of an audio signal (audio frame) have a PTS or DTS describing reproduction output and decoding timing. The video frame and the audio frame are synchronized based on the PTS and the DTS. The synchronization referred to here is synchronization between a video frame and an audio frame in units of frames (hereinafter, inter-frame synchronization). In other words, based on the PTS and DTS, the time position of a certain video frame (the position on the time axis) and the time position of an audio frame corresponding to the video frame are different by one video frame. Adjust to fit within the period. Then, the viewer does not feel strange.

In order to achieve the object of the present invention, the receiving side synchronizes the first video signal with the second video signal by using the same method as that for synchronizing the video signal and the audio signal. It is also possible to take. That is, in the above-mentioned conventional video signal transmission apparatus (see FIG. 11), the video frame of the first video signal and the video frame of the second video signal are synchronized with each other based on the PTS and DTS. The first video signal and the second video signal are decoded independently of each other, and the original video signal is synthesized from the decoded first video signal and the decoded second video signal.

However, when decoding the first video signal and the second video signal independently of each other and synthesizing the original video signal, an interframe between the first video signal and the second video signal is determined based on the PTS or DTS. Synchronization is not enough. This is because, in the inter-frame synchronization, a time shift corresponding to a maximum of one frame period is allowed, but in order to obtain the original video signal, the first video signal after decoding and the second video signal after decoding are combined. This is because it is necessary to synchronize with each other in units of pixels in the frame (hereinafter referred to as intra-frame synchronization). Therefore, each of the following embodiments discloses a video signal receiving apparatus that can synchronize the decoded first video signal and the decoded second video signal with each other between frames and within frames.

(First Embodiment) A video signal receiving apparatus according to a first embodiment of the present invention converts a video signal (high-resolution video signal) into a low-resolution video signal (first video signal) and a high-resolution component. A first video signal and a second video signal, which are separately provided on a receiving side of a video signal transmission system that separately divides the first video signal and the second video signal, and decodes the first video signal and the second video signal independently of each other; And an original video signal (high-resolution video signal) from the decoded first video signal and the decoded second video signal.
Are synthesized. On the transmitting side of this system, for example, FIG.
1 is provided (in the first embodiment, it is not always necessary to add synchronization information to the first video signal and the second video signal).

First Embodiment (and Second Embodiment)
However, a high-resolution video signal has, for example, 1280 horizontal pixels,
The first video signal is a signal with a vertical 720 lines and a frame frequency of 60 Hz. ,
480 vertical lines, 60 Hz frame frequency), and the second video signal is a video signal (high-resolution video signal).
And a signal having a high-resolution component corresponding to a difference between the first video signal and a signal obtained by up-converting the first video signal by an interpolation circuit or the like (hereinafter, a high-resolution component signal).

FIG. 1 is a block diagram showing a configuration of a video signal receiving apparatus according to the first embodiment of the present invention. In FIG. 1, the video signal receiving apparatus according to the first embodiment includes a first input terminal 101, a second input terminal 102, a first decoder 103, a second decoder 104, a combiner 105, And an output terminal 106.

First, the basic operation of the video signal receiving apparatus according to the first embodiment will be described. The first decoder 103 is supplied with (encoded) first video signal input through the first input terminal 101. The second video signal input (encoded) through the second input terminal 102 is supplied to the second decoder 104. In the present embodiment, it is assumed that the first video signal and the second video signal are synchronized with each other between frames. That is, in the first video signal and the second video signal, it is assumed that the time difference between the frames corresponding to each other falls within the time corresponding to one frame period.

The first decoder 103 decodes a given first video signal. The second decoder 104 provides a second
Decode the video signal. At that time, the vertical synchronization signal generated on the first decoder 103 side is supplied to the second decoder 104, and the second decoder 104 decodes the second video signal based on the supplied vertical synchronization signal. Adjust the timing and output timing. The first video signal output from the first decoder 103 and the second video signal output from the second decoder 104 are input to the synthesizer 105.

The synthesizer 105 first up-converts the input first video signal (low-resolution video signal) into the same video format as the original video signal (high-resolution video signal). Next, the upconverted first
The video signal and the input second video signal (high-resolution component signal) are synthesized. Then, the original video signal (high-resolution video signal) obtained by the synthesis is output through the output terminal 106.

Next, of the above series of basic operations, the operation of the first decoder 103 decoding the first video signal,
The operation of the decoder 104 decoding the second video signal will be specifically described. FIG. 2 is a block diagram showing an internal configuration of first decoder 103 in FIG. 2, the first decoder 103 includes a bit stream decoder 201 and a timing generator 202. The timing generator 202
A decoding timing signal indicating a timing at which the bit stream decoder 201 decodes the encoded first video signal (bit stream);
Generates a horizontal synchronizing signal and a vertical synchronizing signal indicating the timing of outputting the decoded first video signal. here,
If the first video signal is a signal as described above, the vertical synchronization signal is generated every 1/60 second. On the other hand, the horizontal synchronization signal has a frequency of 31.5 kHz.

The encoded first video signal (bit stream) is input to the bit stream decoder 201, and the decoded timing signal and the vertical synchronization signal generated by the timing generator 202 are supplied to the bit stream decoder 201. The bit stream decoder 201 decodes an input bit stream according to a given decoding timing signal, and outputs a first video signal obtained by decoding according to a given vertical synchronization signal. I do.

FIG. 3 is a block diagram showing the internal configuration of the second decoder 104 of FIG. In FIG. 3, the second decoder 104 includes a bit stream decoder 301 and a timing generator 302. Timing generator 302
Is the second encoded bitstream decoder 301
A decoding timing signal indicating timing for decoding a video signal (bit stream);
01 generates a horizontal synchronizing signal and a vertical synchronizing signal indicating the timing of outputting the decoded second video signal. Second
If the video signal is a signal as described above, a vertical synchronizing signal is generated every 1/60 second. On the other hand, the horizontal synchronization signal has a frequency of 45 kHz.

At this time, as shown in FIG. 4, the vertical synchronization signal generated by the timing generator 202 on the first decoder 103 side is supplied to the timing generator 302, and the timing generator 302 receives the vertical synchronization signal. A vertical synchronization signal generated by the timing generator 202 based on the vertical synchronization signal;
A vertical synchronizing signal, a horizontal synchronizing signal and a decoding timing signal which are synchronized with the horizontal synchronizing signal and the decoding timing signal are generated. What is important here is that since the vertical synchronization signal passed from the first decoder 103 to the second decoder 104 has pixel accuracy, the vertical synchronization signal, the horizontal synchronization signal, and the decoding timing signal generated by the timing generator 202 are generated. And the vertical synchronization signal, the horizontal synchronization signal, and the decoding timing signal generated by the timing generator 302 can be synchronized with pixel accuracy.

The encoded second video signal (bit stream) is input to the bit stream decoder 301, and the decoded timing signal, the horizontal synchronization signal, and the vertical synchronization signal generated by the timing generator 302 are supplied to the bit stream decoder 301. . The bit stream decoder 301 decodes an input bit stream according to a given decoding timing signal, and obtains a second bit stream obtained by decoding according to a given horizontal synchronization signal and a given vertical synchronization signal. Output video signal.

Thus, the decoding timing and the output timing of the first video signal and the decoding timing and the output timing of the second video signal can be made to coincide with each other with a pixel precision. As a result, the video signal reception timing shown in FIG. The apparatus obtains a first video signal and a second video signal synchronized with each other (that is, intra-frame synchronization) in units of pixels in a frame. The images are shown in FIGS. That is, FIG. 5 shows the phase relationship between the first video signal and the second video signal output from the first decoder 103 and the second decoder 104 when the inter-frame synchronization is performed but the intra-frame synchronization is not performed. FIG. 6 is a diagram visually illustrating a phase relationship when synchronization is performed between frames and synchronization is performed within a frame.

As described above, in the present embodiment, the vertical synchronization signal generated by the timing generator 202 on the first decoder 103 side and indicating the output timing of the decoded first video signal with pixel accuracy is the second decoding signal. Timing generator 3 on the device 104 side
02, and the timing generator 302 receives a signal from the timing generator 202 based on the applied vertical synchronization signal.
Generates a vertical synchronizing signal, a horizontal synchronizing signal, and a decoding timing signal which are synchronized with the vertical synchronizing signal, the horizontal synchronizing signal, and the decoding timing signal generated. This makes it possible to match the decoding timing and output timing of the first video signal with the decoding timing and output timing of the second video signal with pixel accuracy. As a result, the intra-frame synchronization between the decoded first video signal and the decoded second video signal is obtained, so that the original video signal can be obtained on the receiving side.

It should be noted that, even if the horizontal synchronization signal generated by the timing generator 202 is supplied to the timing generator 302 instead of supplying the vertical synchronization signal generated by the timing generator 202 to the timing generator 302, The decoding timing signal generated by 202 may be provided to timing generator 302. Alternatively, the vertical synchronization signal, the horizontal synchronization signal, and the decoding timing signal generated by the timing
, Any two of which are provided by the timing generator 302.
You may give to. Since the horizontal synchronization signal and the decoding timing signal also have pixel accuracy like the vertical synchronization signal,
The vertical synchronization signal, the horizontal synchronization signal, and the decoding timing signal generated by the timing generator 202 can be synchronized with the vertical synchronization signal, the horizontal synchronization signal, and the decoding timing signal generated by the timing generator 302 with pixel accuracy. However, in reality, it is not necessary to use a horizontal synchronization signal or a decoding timing signal having an extremely higher frequency than the vertical synchronization signal.

In the first embodiment, the first decoder 10
3 and that the second video signal input to the second decoder 104 is synchronized between frames. That is, when the first video signal before decoding and the second video signal before decoding are synchronized between frames, the intra-frame synchronization between the first video signal after decoding and the second video signal after decoding is performed. By taking this, the original video signal is obtained on the receiving side. However, when the first video signal before decoding and the second video signal before decoding are not synchronized between frames, the first video signal after decoding and the second video signal after decoding are not synchronized as shown in FIG. By simply taking the intra-frame synchronization with the signal, the time difference between the frames corresponding to each other in the first video signal after decoding and the second video signal after decoding is one.
It becomes equivalent to the frame period or an integral multiple thereof, and the original video signal cannot be obtained.

FIG. 7 shows the case where the first video signal and the second video signal output from the first decoder 103 and the second decoder 104 are synchronized within a frame but not between frames. FIG. 5 is a diagram visually showing the phase relationship of FIG. FIG. 7 shows a case where the time positions of mutually corresponding frames of the first video signal and the second video signal are shifted by exactly one frame period. Therefore, in the second embodiment, even when the first video signal before decoding and the second video signal before decoding are not synchronized between frames, the video signal reception such that the original video signal can be obtained on the receiving side is performed. An apparatus is disclosed.

Second Embodiment A video signal receiving apparatus according to a second embodiment of the present invention converts a video signal (high-resolution video signal) into a low-resolution video signal (first A video signal) and a high-resolution component signal (a second video signal). The video signal is provided on the receiving side of a video signal transmission system that separately encodes and transmits the first video signal and the second video signal. Decoding independently of each other and the first
An original video signal (high-resolution video signal) is synthesized from the video signal and the decoded second video signal. On the transmitting side of this system, for example, a video signal transmitting device having a configuration similar to that of FIG. 11 is provided (in the second embodiment, unlike the first embodiment, the first video signal and the second video signal Need to add synchronization information to

FIG. 8 is a block diagram showing a configuration of a video signal receiving apparatus according to the second embodiment of the present invention. 8, the video signal receiving apparatus according to the second embodiment includes a first input terminal 101, a second input terminal 102, a synchronization information extractor 801, a first decoder 802, and a second decoder 80.
3, a synthesizer 105, and an output terminal 106.

That is, the video signal receiving apparatus according to the second embodiment differs from the video signal receiving apparatus according to the first embodiment (see FIG. 1) in that the first decoder 103 and the second decoder 104 are replaced. , A first decoder 802 and a second decoder 803, and a synchronization information extractor 801.

First, the basic operation of the video signal receiving apparatus according to the second embodiment will be described. A first video signal input (encoded) through the first input terminal 101 and a video signal input (encoded) through the second input terminal 102
The second video signal is supplied to a first decoder 802 and a second decoder 803 via a synchronization information extractor 801.

The synchronization information extractor 801 includes a first decoder 80
2 and a second decoder 803
From the second video signal provided to
And DTS) are extracted. Then, based on the extracted synchronization information, the first video signal after decoding and the second video signal after decoding
An inter-frame synchronization control signal for synchronizing frames with a video signal is generated.

The first decoder 802 decodes the supplied first video signal. The second decoder 803 outputs the given second
Decode the video signal. At that time, to the second decoder 803,
The inter-frame synchronization control signal generated by the synchronization information extractor 801 and the vertical synchronization signal generated by the first decoder 802 are provided. The second decoder 803 controls the inter-frame synchronization control signal and the vertical synchronization signal. , The decoding of the second video signal is stopped or skipped by one frame, and
The decoding timing and the output timing of the second video signal are adjusted. The first video signal output from the first decoder 802 and the second video signal output from the second decoder 803 are input to the synthesizer 105.

The synthesizer 105 first up-converts the input first video signal (low-resolution video signal) to have the same video format as the original video signal (high-resolution video signal). Next, the upconverted first
The video signal and the input second video signal (high-resolution component signal) are synthesized. Then, the original video signal (high-resolution video signal) obtained by the synthesis is output through the output terminal 106.

Next, of the above series of basic operations, an operation in which the synchronization information extractor 801 generates an inter-frame synchronization control signal, an operation in which the first decoder 802 decodes the first video signal,
The operation of decoding the second video signal by the second decoder 803 will be specifically described. The synchronization signal extractor 801 initially
Synchronization information is extracted from the first video signal provided to the first decoder 802 and the second video signal provided to the second decoder 803, respectively. Next, the two extracted synchronization signals are compared with each other to determine whether the first video signal and the second video signal are shifted by one frame period or more. If the determination result is affirmative, it is determined whether decoding of the second video signal is stopped or skipped by one frame so that the mutual shift is within one frame period. And
Generate an inter-frame synchronization control signal indicating the determination result,
Output to the second decoder 803.

FIG. 9 is a block diagram showing the internal configuration of first decoder 802 in FIG. In FIG. 9, the first decoder 802 includes a bit stream decoder 901 and a timing generator 902. Timing generator 902
Is the first encoded bit stream decoder 901
A decoding timing signal indicating timing for decoding a video signal (bit stream);
01 generates a horizontal synchronizing signal and a vertical synchronizing signal indicating the timing of outputting the decoded first video signal. Here, if the first video signal is a signal as described above, the vertical synchronization signal is generated every 1/60 second. On the other hand, the horizontal synchronization signal has a frequency of 31.5 kHz.

The coded first video signal (bit stream) is input to the bit stream decoder 901, and the decoded timing signal, the horizontal synchronization signal, and the vertical synchronization signal generated by the timing generator 902 are supplied to the bit stream decoder 901. . A bit stream decoder 901 decodes an input bit stream according to a given decoding timing signal, and decodes a first bit stream obtained according to a given horizontal synchronization signal and vertical synchronization signal. Output video signal.

FIG. 10 is a block diagram showing the internal configuration of the second decoder 803 in FIG. In FIG. 10, the second
The decoder 803 includes a bit stream decoder 1001 and
And a timing generator 1002. The timing generator 1002 outputs a decoding timing signal indicating the timing at which the bit stream decoder 1001 decodes the encoded second video signal (bit stream), and outputs the decoded second video signal by the bit stream decoder 1001. A horizontal synchronizing signal and a vertical synchronizing signal indicating the timing of the synchronization are generated. Here, if the second video signal is a signal as described above, the vertical synchronization signal is generated every 1/60 second. On the other hand, the horizontal synchronization signal has a frequency of 45 kHz.

At that time, the timing generator 1002
As shown in FIG. 4, the vertical synchronization signal generated by the timing generator 902 on the first decoder 802 side is provided, and the timing generator 1002 generates the vertical synchronization signal based on the provided vertical synchronization signal. The vertical synchronizing signal, the horizontal synchronizing signal and the decoding timing signal are synchronized with the vertical synchronizing signal, the horizontal synchronizing signal and the decoding timing signal. What is important here is that the first decoder 80
Since the vertical synchronization signal passed from the second to the second decoder 803 has pixel accuracy, the vertical synchronization signal generated by the timing generator 902, the horizontal synchronization signal and the decoding timing signal, and the timing generator 1002 are generated. The point is that the vertical synchronization signal, the horizontal synchronization signal, and the decoding timing signal can be synchronized with pixel accuracy.

The encoded second video signal (bit stream) is input to the bit stream decoder 1001, and the decoded timing signal, the horizontal synchronization signal and the vertical synchronization signal generated by the timing generator 1002,
An inter-frame synchronization control signal generated by the synchronization information extractor 801 is provided. Bit stream decoder 1001
Decodes an input bit stream according to a given decoding timing signal, and outputs a second video signal obtained by decoding according to a given horizontal synchronization signal and a vertical synchronization signal. . Bit stream decoder 10
01 further executes a process of stopping or skipping the operation of decoding the bit stream by one frame according to the given inter-frame synchronization control signal.

Thus, while synchronizing the first video signal and the second video signal between frames, the decoding timing and the output timing of the first video signal and the decoding timing and the output timing of the second video signal are adjusted in pixel accuracy. As a result, the video signal receiving apparatus of FIG. 8 obtains the first video signal and the second video signal that are synchronized between frames and synchronized within the frame (see FIG. 6).

As described above, in the present embodiment, the synchronization information extractor 801 uses the synchronization information (from the first video signal supplied to the first decoder 802 and the second video signal supplied to the second decoder 803). For example, PTS and DTS) are extracted. Then, based on the extracted synchronization information, the second
Generating an inter-frame synchronization control signal for controlling inter-frame synchronization of the decoded first video signal and the decoded second video signal by controlling an operation of decoding the video signal;
It is provided to the second decoder 803. The second decoder 803 stops or skips the operation of decoding the second video signal by one frame according to the given inter-frame synchronization control signal. Thus, the first video signal and the second video signal can be synchronized between frames.

The vertical synchronizing signal generated by the timing generator 902 on the first decoder 802 side is supplied to the timing generator 1002, and the timing generator 1002
Based on the applied vertical synchronization signal, a vertical synchronization signal, a horizontal synchronization signal, and a decoding timing signal synchronized with the vertical synchronization signal, the horizontal synchronization signal, and the decoding timing signal generated by the timing generator 902 are generated. This makes it possible to match the decoding timing and output timing of the first video signal with the decoding timing and output timing of the second video signal with pixel accuracy. As a result, both inter-frame synchronization and intra-frame synchronization can be achieved between the decoded first video signal and the decoded second video signal, so that the original video signal can be obtained on the receiving side.

In this embodiment, the inter-frame synchronization control signal is supplied to the second decoder 803 (that is, by controlling the operation of decoding the second video signal, the first video signal and the second video signal are controlled). Are synchronized between frames), but may instead be provided to the first decoder 802 (ie, the first decoder 802).
By controlling the operation of decoding the video signal, the first
The video signal and the second video signal may be synchronized between frames.) In this case, the synchronization information extractor 801 extracts synchronization information from the first video signal and the second video signal, respectively.
An inter-frame synchronization control signal for synchronizing the first video signal and the second video signal between frames is generated by controlling an operation of decoding the first video signal based on the extracted synchronization information, and the first decoding is performed. To the container 802. The first decoder 802 stops or skips the operation of decoding the first video signal by one frame according to the given inter-frame synchronization control signal.

Alternatively, the inter-frame synchronization control signal may be provided to both the first decoder 802 and the second decoder 803 (that is, the operation of decoding the first video signal and the operation of decoding the second video signal) Respectively, thereby synchronizing the first video signal and the second video signal between frames.) Supplementing here, generally, the first decoder 802
The first video signal and the second video signal can be synchronized between frames by providing the inter-frame synchronization control signal to one of the second decoder 803 and the second decoder 803.
In the case of EG2, the first video signal and the second video signal are further converted to STC (System TimeClock).
k), the first decoder 8
02 and the second decoder 803, the synchronization control signal (S
TC synchronization / inter-frame synchronization control signal).

In this case, the synchronization information extractor 801
Synchronization information is extracted from the video signal and the second video signal, respectively, and the first synchronization information is extracted based on the extracted synchronization information and the STC.
By controlling the operation of decoding the video signal and the operation of decoding the second video signal, respectively, the first video signal and the second video signal are synchronized with the STC, respectively, and the first video signal and the second video signal are synchronized. An STC synchronization / interframe synchronization control signal for interframe synchronization is generated and provided to the first decoder 802 and the second decoder 803. The first decoder 802 stops or skips the operation of decoding the first video signal by one frame according to the supplied STC synchronization / inter-frame synchronization control signal, and the second decoder 803 outputs the supplied STC synchronization / interframe synchronization. The operation of decoding the second video signal is stopped or skipped by one frame in accordance with the synchronization / inter-frame synchronization control signal.

Specifically, the synchronization signal extractor 801 first extracts synchronization information from the first video signal supplied to the first decoder 802 and the second video signal supplied to the second decoder 803, respectively. I do. Next, the synchronization signal extracted from the first video signal is compared with STC,
It is determined whether or not the shift from the TC is one frame period or more. If the determination result is affirmative, the decoding of the first video signal is stopped by one frame so that the shift from the STC is within one frame period. Decide whether to skip or skip. Then, it generates an STC synchronization / inter-frame synchronization control signal indicating the determination result and outputs the generated signal to first decoder 802.

Next, the synchronization signal extracted from the second video signal is compared with the STC, and if the second video signal is 1
It is determined whether the shift is longer than the frame period, and if the determination result is affirmative, whether to stop or skip the decoding of the second video signal by one frame so that the shift with respect to the STC is within one frame period. To determine. Then, an STC synchronization / inter-frame synchronization control signal indicating the result of the determination is generated and output to second decoder 803.

Next, the synchronization signal extracted from the first video signal and the synchronization signal extracted from the second video signal are compared with each other, and the first video signal and the second video signal are shifted by one frame period or more. Is determined, and if the determination result is affirmative, the mutual deviation is within one frame period.
It is determined whether decoding of the second video signal is stopped or skipped for one frame. And an STC indicating the result of the determination.
A synchronization / interframe synchronization control signal is generated and output to the second decoder 803 (or, it is determined whether decoding of the first video signal is stopped or skipped by one frame, and the determination result is shown. An STC synchronization / inter-frame synchronization control signal may be generated and output to the first decoder 802).

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a video signal receiving device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing an internal configuration of a first decoder 103 in FIG.

FIG. 3 is a block diagram showing an internal configuration of a second decoder 104 in FIG.

FIG. 4 is a timing generator 302 on the second decoder 104 side;
Is a diagram showing a vertical synchronization signal, a horizontal synchronization signal, and a decoding timing signal generated based on a vertical synchronization signal provided from the first decoder 103 side.

FIG. 5 is a view showing a visual phase relationship between a first video signal and a second video signal output from a first decoder 103 and a second decoder 104 when synchronization is performed between frames but not within a frame. FIG.

FIG. 6 is a view visually showing a phase relationship between a first video signal and a second video signal output from a first decoder 103 and a second decoder 104 when inter-frame synchronization and intra-frame synchronization are performed; FIG.

FIG. 7 is a view visually illustrating a phase relationship between a first video signal and a second video signal output from a first decoder 103 and a second decoder 104 when synchronization is performed within a frame but not between frames. FIG.

FIG. 8 is a block diagram illustrating a configuration of a video signal receiving device according to a second embodiment of the present invention.

9 is a block diagram showing an internal configuration of a first decoder 802 in FIG.

FIG. 10 is a block diagram showing an internal configuration of a second decoder 803 in FIG.

FIG. 11 is a block diagram illustrating an example of a configuration (on a transmission side) of a conventional video signal transmission device.

[Explanation of symbols]

101: first input terminal 102: second input terminal 103, 802: first decoder 104, 803: second decoder 105: synthesizer 106: output terminal 201, 301, 901, 1001: bit stream decoder 202, 302,902,1002 ... timing generator 801 ... synchronization information extractor

Claims (3)

[Claims] A high-resolution video signal is divided into a low-resolution video signal (hereinafter, a first video signal) and a high-resolution component signal (hereinafter, a second video signal), and separately encoded and transmitted. Provided on the receiving side of a video signal transmission system, decodes the encoded first video signal and the encoded second video signal independently of each other, and decodes the first video signal and the decoded second video signal. A video signal receiving apparatus for synthesizing an original high-resolution video signal from two video signals, a first decoding unit for decoding an encoded first video signal, and a second decoding unit for decoding an encoded second video signal A decoding unit, and a combining unit that combines the decoded first video signal output from the first decoding unit and the decoded second video signal output from the second decoding unit; The decoding unit includes a decoding timing signal, a vertical synchronizing signal, First timing generator for generating a horizontal synchronizing signal, and the first
A decoding timing signal, a vertical synchronizing signal, and a horizontal synchronizing signal generated by the timing generator are provided, and the encoded first video signal is decoded according to the decoding timing signal, and the vertical synchronizing signal and the horizontal synchronizing signal are decoded. A first decoding control unit that outputs a first video signal after decoding in accordance with the signal, wherein the second decoding unit is provided with a vertical synchronization signal generated by the first timing generation unit, and the vertical synchronization signal A second timing generator that generates a decoding timing signal, a vertical synchronization signal, and a horizontal synchronization signal that are synchronized with the decoding timing signal, the vertical synchronization signal, and the horizontal synchronization signal generated by the first timing generator, respectively, and The decoding timing signal, the direct synchronizing signal, and the horizontal synchronizing signal generated by the second timing generating section are provided. A second decoding control unit that decodes the encoded second video signal according to the decoding signal and outputs the decoded second video signal according to the vertical synchronization signal and the horizontal synchronization signal. Video signal receiving device. 2. Each of the frames forming the encoded first video signal and each of the frames forming the encoded second video signal include a decoded first video signal and a decoded second video signal.
Synchronization information for synchronizing a video signal with an inter-frame is attached, and an encoded first video signal input to the first decoding unit and an encoded first video signal input to the second decoding unit A synchronization information extraction unit that extracts the synchronization information from the second video signal, wherein the synchronization information extraction unit further compares the extracted two pieces of synchronization information with each other. When the encoded first video signal input to the decoding unit and the encoded second video signal input to the second decoding unit are shifted by one frame period or more, the first decoding is performed. Generating an inter-frame synchronization control signal for keeping the difference between the decoded first video signal output from the unit and the decoded second video signal output from the second decoding unit within one frame period, The first decryption control unit and / or The second decoding control unit stops or skips the operation of decoding the encoded first video signal and / or the encoded second video signal for one frame period according to the inter-frame synchronization control signal. The video signal receiving device according to claim 1, wherein: 3. The video signal transmission system according to claim 1, wherein each frame constituting the encoded first video signal and each frame constituting the encoded second video signal have a decoding timing and an output timing of the frame. And a coded first video signal input to the first decoding unit and a coded first video signal input to the second decoding unit. A synchronization information extraction unit that extracts the synchronization information from each of the two video signals, the synchronization information extraction unit further compares the extracted two pieces of synchronization information with the reference clock, and as a result, The encoded first video signal input to one decoding unit and / or the encoded second video signal input to the second decoding unit are the reference clock and one frame. The first video signal output from the first decoding unit and / or the second video signal output from the second decoding unit.
A reference clock synchronization control signal for keeping a difference between a video signal and the reference clock within one frame period is generated, and the extracted two pieces of the synchronization information are compared with each other. As a result, the first decoding unit When the encoded first video signal input to the second decoding unit and the encoded second video signal input to the second decoding unit are shifted by one frame period or more, the first decoding unit Output first after decryption
The video signal and the second decoded signal output from the second decoding unit.
Generating an inter-frame synchronization control signal for keeping a deviation from a video signal within one frame period, wherein the first decoding control unit and / or the second decoding control unit is configured to control the reference clock synchronization control signal and the inter-frame The method according to claim 1, wherein the operation of decoding the encoded first video signal and / or the encoded second video signal is stopped or skipped for one frame period according to the synchronization control signal. Video signal receiving device.