JP2001119292A - Frequency division circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify the circuit constitution to save power furthermore. SOLUTION: A frequency division circuit is comprised of a T-FF 21 which divides the frequency of an input signal into two to output a signal, an OR gate 22 for switching between input of three continuous pulses of a clock signal CLK and input of two out of three pulses with one pulse masked, and a NOR gate 23 which generates a control signal to control switching of the number of input pulses in the OR gate 22. When three continuous pulses of the clock signal CLK are inputted to the T-FF as they are, an output signal OUT of the T-FF 21 is a signal obtained by dividing the frequency of the clock signal CLK into two. When one of three continuous pulses of the clock signal CLK is masked to input two pulses to the T-FF 21, the output signal OUT of the T-FF 21 is a signal obtained by dividing the frequency of the clock signal CLK into three.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a frequency dividing circuit.
2. Description of the Related Art In recent years, there has been a demand for a reduction in the size and weight of wireless mobile terminals that have been spreading rapidly. In order to reduce the size and weight of the wireless portable terminal, it is important to reduce the size and weight of the built-in battery that occupies most of the capacity and weight of the portable terminal. For that purpose, it is effective to reduce the power consumption of the wireless IC built in the terminal. The wireless IC is provided with a frequency synthesizer. This frequency synthesizer is provided with a prescaler (frequency dividing circuit).

[0002]

2. Description of the Related Art A frequency divider used in a radio synthesizer has a power of 2 n and a power of 2 n plus 1 (n = 1, 2, 2).
3,...), For example, when n = 2, a function called a pulse swallow counter for realizing frequency division by 4 and frequency division by 5 is required.

FIG. 10 is a circuit diagram showing a conventional 4/5 frequency dividing circuit. This 4/5 frequency dividing circuit is constituted by three D flip-flop circuits 11, 12, and 13 and one two-input OR gate 14. A clock signal CLK is supplied to each of the flip-flop circuits 11, 12, and 13 from an external or internal clock generation circuit (not shown) via a clock buffer 15.

The first-stage flip-flop circuit 11 includes:
The output signal of the OR gate 14 is supplied as the D input signal. The two input signals of the OR gate 14 are the Q output signals of the flip-flop circuit 12 of the second stage and the flip-flop circuit 13 of the third stage.

The second-stage flip-flop circuit 12 includes:
As the D input signal, the / Q output signal (inverted signal of the Q output) of the first-stage flip-flop circuit 11 is supplied. The Q output signal of the second-stage flip-flop circuit 12 becomes the output signal OUT of the frequency divider.

The third-stage flip-flop circuit 13 includes:
The Q output signal of the second-stage flip-flop circuit 12 is supplied as the D input signal. The enable (disable) or disable (disable) of the third-stage flip-flop circuit 13 is switched by an MDC signal which is a control signal. The MDC signal is supplied by an external or internal logic circuit (not shown).

This frequency dividing circuit operates as a frequency dividing circuit when the third flip-flop circuit 13 is disabled. On the other hand, the third-stage flip-flop circuit 13 is enabled to perform a divide-by-5 operation.

FIG. 11 is a circuit diagram showing a 16/17 frequency dividing circuit using the 4/5 frequency dividing circuit shown in FIG. This one
The 6/17 frequency dividing circuit includes a 4/5 frequency dividing circuit unit 1 including three D flip-flop circuits 11, 12, and 13, an OR gate 14, and a clock buffer 15 shown in FIG.
A counter circuit unit 2 for dividing by 4 composed of T flip-flop circuits 16 and 17 and one 3-input OR gate 18 are added.

In the counter circuit section 2, the clock signal input terminal of the preceding flip-flop circuit 16
The Q output signal of the second-stage flip-flop circuit 12 of the divide-by-5 circuit unit 1 is supplied. In the counter circuit section 2,
The Q output signal of the preceding flip-flop circuit 16 is supplied to the clock signal input terminal of the subsequent flip-flop circuit 17. In this 16/17 frequency dividing circuit, the output signal OUT is given by the Q output signal of the flip-flop circuit 17 at the subsequent stage of the counter circuit section 2.

The enable (valid) or disable (invalid) of the third flip-flop circuit 13 of the 4/5 frequency divider 1 is controlled by the output signal of the OR gate 18. The OR gate 18 has the MD signal and the / Q of each of the two flip-flop circuits 16 and 17 of the counter circuit unit 2.
An output signal is provided. That is, switching between the divide-by-16 and divide-by-17 by the 16/17 divider circuit is controlled by the MDC signal, that is, the MD signal and the OR output of each of the / Q output signals of the flip-flop circuits 16 and 17.

[0011]

The conventional 4/5 frequency dividing circuit shown in FIG. 10 is widely used in actual products such as mobile phones. The circuit constants are also optimized to a level close to the limit. Therefore, the “2 n
It is difficult to further reduce the power consumption and reduce the circuit size of the frequency divider circuit of (power / 2 / nth power plus 1).

The present invention has been made in view of the above circumstances, and has as its object to provide a frequency dividing circuit having a simple circuit configuration and capable of further reducing power consumption.

[0013]

To achieve the above object, a frequency dividing circuit according to the present invention comprises a frequency dividing means (T-FF) for dividing an input signal by two and outputting the divided signal, and a frequency dividing means (T-FF). -FF)
A pulse number limiting means (OR gate) for switching between inputting three consecutive pulses of a clock signal as it is or inputting two pulses by masking one of the three pulses, and limiting the number of pulses And a control signal for controlling switching of the number of input pulses by means (OR gate).

According to the present invention, when three consecutive pulses of the clock signal are directly input to the frequency dividing means (T-FF), a signal obtained by dividing the clock signal by two is obtained. On the other hand, three consecutive pulses of the clock signal are converted into two pulses by the pulse number limiting means (OR gate), and the frequency dividing means (T-
FF), a signal obtained by dividing the clock signal by three is obtained. Therefore, a 2/3 frequency dividing circuit is obtained.

In the present invention, the frequency dividing means (T-FF)
At the subsequent stage, a counter means (T-FF) for further dividing the output signal of the frequency dividing means (T-FF) may be provided.
Then, the 4/5 frequency divider, the 8/9 frequency divider, the 16 /
A frequency dividing circuit, such as a 17-frequency dividing circuit, that divides the frequency of 2 to the power of n + 1 and 2 to the power of n + 1 plus 1 (n = 1, 2, 3,.

Specifically, for example, the frequency dividing means (TF)
F) may be configured by a toggle flip-flop circuit, or the pulse number limiting means (OR gate) may be configured by a logic circuit that outputs an OR logic of a clock signal and a control signal. In this case, the control signal has a relatively high potential level only during a period in which the pulse number limiting means (OR gate) prohibits the output of the clock signal pulse.

Further, the present invention may further include timing adjusting means (a delay circuit or a clock synchronous circuit) for adjusting the input timing of the control signal to the pulse number limiting means (OR gate).

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a frequency dividing circuit according to the present invention will be described below in detail with reference to the drawings.

(Embodiment 1) FIG. 1 is a circuit diagram showing a 2/3 frequency dividing circuit according to Embodiment 1 of the present invention. This 2 /
The frequency-divided-by-3 circuit includes a toggle flip-flop circuit (hereinafter referred to as T-FF) 21 as frequency dividing means, a two-input OR gate 22 as pulse number limiting means, and an OR gate 2
2 is provided with a two-input NOR gate 23 for supplying a control signal to the second. When a pulse is input, the T-FF alternately changes the potential level of the output signal between a relatively high “H” level and a relatively low “L” level.

The / Q output signal of the T-FF 21 is 2 /
This becomes the output signal OUT of the divide-by-3 circuit. Also, T-FF2
The / Q output signal of 1 becomes one input signal of the NOR gate 23. The other input signal of the NOR gate 23 is an MDC signal supplied from an MDC signal generation circuit (not shown) or the like.

The MDC signal generation circuit is a logic circuit designed to generate a signal having a waveform described later. For example, the MDC signal generation circuit is a counter circuit (not shown) connected to a stage subsequent to the output of the ／ frequency divider.

The output signal of the NOR gate 23 becomes one input signal of the OR gate 22. The other input signal of the OR gate 22 is, for example, a clock signal CLK.
Since the output of the clock signal CLK from the OR gate 22 is controlled by the potential level of the output signal of the NOR gate 23, the output signal of the NOR gate 23 is a control signal for controlling the pulse number limiting means.

The output signal of the OR gate 22 is T-FF2
1 clock signal input terminal. The clock signal input terminal is a trigger input terminal for causing the T-FF 21 to perform a toggle operation. OR gate 22
Also serves as a clock buffer. Clock signal CL
K is supplied, for example, by a clock generation circuit (not shown) provided outside or inside the 2/3 frequency dividing circuit.

Next, the operation of the 2/3 frequency dividing circuit shown in FIG. 1 will be described. FIG. 2 is a timing chart showing the operation timing of the ／ frequency divider of the first embodiment.
When the MDC signal is at a relatively high “H” level, the potential level of the output signal of the NOR gate 23 (input signal of the OR gate 22) is always at a relatively low “L” level.

At this time, the output of the OR gate 22, that is, the input signal of the T-FF 21 is the clock signal C since one of the input signals is at the "L" level.
Same as LK. Therefore, the T-FF 21 outputs an output signal OUT having a ratio of one pulse to two pulses of the clock signal CLK from its / Q output terminal. That is, the ／ frequency divider circuit operates as a 分 frequency divider circuit.

On the other hand, when the MDC signal is at a relatively high “L” level, the output signal of NOR gate 23 (OR gate 2
2 input signal) is opposite to the potential level of the output signal OUT of the T-FF 21. When the potential level of the input signal of the OR gate 22 is “L” level, the output signal of the OR gate 22 becomes the same as the clock signal CLK.

On the other hand, when the potential level of the input signal of the OR gate 22 is at the "H" level (when the output signal OUT is at the "L" level), the output signal of the OR gate 22 is fixed at the "H" level. You. Therefore, T-FF2
1 is in a state where the input of the clock signal CLK is prohibited.

The potential level of the MDC signal is such that, of the three consecutive pulses of the clock signal CLK, for example, the rising edge of the second pulse P2 is input to the T-FF 21 and the falling edge of the second pulse P2 The edge and the rising edge of the third pulse P3 change so as not to be input. Further, the potential level of the MDC signal is such that the falling edge of the third pulse P3 is TF
It changes to be input to F21.

Therefore, as shown by the broken line in FIG. 2, the second pulse P2 and the third pulse P3 of the clock signal CLK are input to the T-FF 21 as one pulse. Therefore, the T-FF 21 outputs the first to third three pulses P of the clock signal CLK from its / Q output terminal.
Output signal OU of the ratio of one pulse to 1, P2 and P3
Output T. That is, the ／ frequency divider operates as a ３ frequency divider.

Actually, a delay occurs in signal propagation in each of the gates 22, 23 and the T-FF 21, so that the timing of each signal is slightly shifted. This deviation is taken into account in the timing chart of FIG.

Here, as described above, the clock signal C
In order to input the second pulse P2 and the third pulse P3 of LK to the T-FF 21 as one pulse, the output signal of the NOR gate 23, that is, the control signal rises during the period of t1 shown in FIG. It falls within the period of t2.

This can be expressed by the following equation (1). However, one cycle of the clock signal CLK is T, and the OR gate 2
2 is tpd1 and the delay time of the T-FF 21 is t
The delay time of pd2 and the NOR gate 23 is tpd3, and m is a natural number of 1 or more.

MT <(tpd1 + tpd2 + tpd3)
<MT + T / 2 (1) When the 2/3 frequency dividing circuit shown in FIG.
When the expression (1) is not satisfied, the configuration shown in FIG. 3 or FIG. 4 may be adopted.

FIG. 3 shows a configuration in which a delay circuit 26 is added to the 2/3 frequency dividing circuit shown in FIG. The delay circuit 26 is provided between the NOR gate 23 and the OR gate 22. The delay circuit 26 adjusts the timing of the control signal output from the NOR gate 23 so as to satisfy the above equation (1).

FIG. 4 is obtained by adding a clock synchronizing circuit 27 to the 2/3 frequency dividing circuit shown in FIG. The clock synchronization circuit 27 is interposed between the NOR gate 23 and the OR gate 22. The clock synchronization circuit 27 includes the NOR gate 23
Is synchronized with the clock signal CLK. Therefore, the rising and falling timings of the control signal satisfy the above equation (1).

According to the first embodiment, the 2/3 frequency dividing circuit includes one T-FF 21, OR gate 22, and NOR gate 23.
It consists of. The 2/3 frequency dividing circuit converts three consecutive pulses of the clock signal CLK into TF
When input to F21, it operates as a divide-by-2 circuit.

On the other hand, when three consecutive pulses of the clock signal CLK are converted into two pulses and input to the T-FF 21,
The ３ divider circuit operates as a ３ divider circuit. Therefore, if the "2n / 2th / 2nth power plus 1" frequency dividing circuit is configured by using the 2/3 frequency dividing circuit, the configuration becomes simple, so that the circuit size can be reduced and power consumption can be reduced. Can be planned.

(Embodiment 2) FIG. 5 is a circuit diagram showing a 4/5 frequency dividing circuit according to Embodiment 2 of the present invention. This 4 /
The ５ frequency divider differs from the ２ frequency divider of the first embodiment shown in FIG. 1 in the following three points. Other configurations are the same as those of the first embodiment.
The same reference numerals as in Embodiment 1 denote the same parts, and a description thereof will be omitted.

First, the / Q of the first T-FF 21
The output signal is used as an input signal, and its / Q output signal is
The second T-FF3 as counter means for frequency division
1 is provided.

Second, the Q output signal of the second T-FF 31 is the output signal OUT of the entire frequency divider. Third
In place of the two-input NOR gate 23, a second T-FF3
There is provided a three-input NOR gate 32 for outputting the OR logic of one Q output signal, the / Q output signal of the first T-FF 21 and the MD signal. The output signal of the three-input NOR gate 32 is
This is a control signal for controlling the number of pulses output from the OR gate 22, which is a pulse number limiting unit.

FIG. 6 is a timing chart showing the operation timing of the 4/5 frequency dividing circuit according to the second embodiment. FIG.
2 shows a case where the potential level of the MDC signal is at the “L” level, which is relatively low. The MDC signal is not always fixed at the “L” level.

The operation timing is basically the same as that of the first embodiment shown in FIG. 2, and therefore will be briefly described. 6, the input signal of the T-FF 21 rises, for example, triggered by the rising edge of the pulse indicated by P11 (arrow A in FIG. 6). Thereby, T-
The / Q output signal of the FF 21 falls (arrow B in FIG. 6).
Then, the control signal (the output signal of the NOR gate 32) becomes the “H” level whose potential level is relatively high (arrow C in FIG. 6).

With this "H" level control signal, one pulse (broken line portion) of five consecutive pulses of the clock signal CLK is masked (arrow d in FIG. 6). Thereby, the ／ frequency divider operates as a ５ frequency divider.

When the potential level of the MDC signal is at a relatively high "H" level, the control signal (output signal of the NOR gate 32) is always at a "L" level having a relatively low potential level. Therefore, the output of the OR gate 22, that is, the input signal of the T-FF 21 becomes the same as the clock signal CLK, and the ／ frequency divider operates as a ４ frequency divider.

As in FIG. 2, also in FIG. 6, a timing shift due to a delay of a signal generated in each of the gates 22 and 32 and each of the T-FFs 21 and 31 is considered.

Also, as in the first embodiment, in the second embodiment, the 4/5 frequency divider satisfies the above equation (1). If equation (1) is not satisfied, FIG. 7 or FIG.
The configuration shown in FIG.

FIG. 7 shows that the delay circuit 36 is added between the NOR gate 32 and the OR gate 22 of the 4/5 frequency dividing circuit shown in FIG. The adjustment is made so as to satisfy the expression.

FIG. 8 shows that a clock synchronizing circuit 37 is added between the NOR gate 32 and the OR gate 22 of the 4/5 frequency dividing circuit shown in FIG. 5 to synchronize the control signal output from the NOR gate 32 with the clock signal CLK. It is like that.

According to the second embodiment, since the 4/5 frequency dividing circuit includes two T-FFs 21 and 31, an OR gate 22, and a NOR gate 32, the conventional 4/5 frequency dividing circuit (see FIG. 10). ), The number of flip-flop circuits is smaller. The T-FF 31 is 、 of the T-FF 21.
The T-FF 31
Operating frequency can be reduced. Therefore, 4/5
The configuration of the frequency divider circuit is simplified, and the circuit size can be reduced and power consumption can be reduced.

(Embodiment 3) FIG. 9 is a circuit diagram showing a 16/17 frequency dividing circuit according to Embodiment 3. This 16/1
The divide-by-7 circuit has a counter circuit (for divide-by-8) consisting of three T-FFs 41, 42, and 43 connected to the subsequent stage of the ／ divider circuit of the first embodiment shown in FIG. is there.

In this 16/17 frequency dividing circuit, instead of the 2-input NOR gate 23, three T-FFs 4 of the counter circuit are used.
A 4-input NOR gate 44 for outputting the OR logic of the / Q output signals of 1, 42 and 43 and the MD signal is provided. The output signal of the 4-input NOR gate 44 serves as a control signal for controlling the number of pulses output from the OR gate 22 as the pulse number limiting means. Note that the configuration and operation timing of the third embodiment are the same as those of the first or second embodiment, and thus description thereof will be omitted.

According to the third embodiment, since the 16/17 frequency dividing circuit includes four T-FFs 21, 41, 42, 43, an OR gate 22, and a NOR gate 44, the conventional 16/17 frequency dividing circuit is used. The number of flip-flop circuits is smaller than that shown in FIG. Therefore, the configuration of the 16/17 frequency dividing circuit is simplified, and the circuit size can be reduced and power consumption can be reduced.

As described above, the present invention relates to the second embodiment of the first embodiment.
By connecting a counter circuit composed of a plurality of stages of T-FFs to the subsequent stage of the ３ frequency divider, for example, 32/33
Frequency divider, 64/65 frequency divider, or 128/12
A divide-by-9 circuit can also be configured. Also, the present invention
A configuration in which the positive logic and the negative logic are exchanged may be adopted.

[0054]

According to the present invention, the frequency dividing circuit is provided with frequency dividing means, pulse number limiting means, and a control signal. When three consecutive pulses of the clock signal are directly input to the frequency dividing means, the frequency dividing circuit is divided into two. On the other hand, when three consecutive pulses of the clock signal are converted into two pulses by the pulse number limiting means and input to the frequency dividing means, the circuit operates as a frequency dividing circuit. That is, it is possible to switch between the divide-by-2 circuit and the divide-by-3 circuit only by controlling the number of pulses of the clock signal.

Therefore, the circuit scale of the frequency dividing circuit is larger than that of a conventional frequency dividing circuit in which one more flip-flop circuit is provided and the number of divisions is changed by switching the valid / invalid state of the flip-flop circuit. Can be smaller. Further, the operating frequency of another flip-flop circuit can be reduced. Thus, the power consumption of the frequency dividing circuit can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a ／ frequency divider according to a first embodiment;

FIG. 2 is a timing chart showing operation timings of the ／ frequency divider according to the first exemplary embodiment;

FIG. 3 is a circuit diagram showing an example in which a delay circuit is added to the ／ frequency divider shown in FIG. 1;

FIG. 4 is a circuit diagram showing an example in which a clock synchronization circuit is added to the ／ frequency divider shown in FIG. 1;

FIG. 5 is a circuit diagram showing a 4/5 frequency dividing circuit according to a second exemplary embodiment;

FIG. 6 is a timing chart showing operation timings of the 4/5 frequency dividing circuit according to the second exemplary embodiment;

7 is a circuit diagram showing an example in which a delay circuit is added to the 4/5 frequency dividing circuit shown in FIG.

8 is a circuit diagram showing an example in which a clock synchronization circuit is added to the 4/5 frequency dividing circuit shown in FIG.

FIG. 9 is a circuit diagram showing a 16/17 frequency dividing circuit according to a third embodiment;

FIG. 10 is a circuit diagram showing a conventional 4/5 frequency dividing circuit.

FIG. 11 is a circuit diagram showing a 16/15 circuit using the 4/5 frequency dividing circuit shown in FIG. 10;
It is a circuit diagram which shows a 17 frequency dividing circuit.

[Description of Signs] 21 Frequency dividing means (T-FF) 22 Pulse number limiting means (OR gate) 31, 41, 42, 43 Counter means (T-FF) 26, 36 Timing adjusting means (delay circuit) 27, 37 Timing Adjustment means (clock synchronization circuit)

Claims (5)

[Claims] A pulse number limiting means for permitting or prohibiting the output of one of three consecutive pulses with respect to an input clock signal, and a pulse of the signal output from the pulse number limiting means. A frequency dividing circuit comprising: frequency dividing means for switching a level of an output signal; and a control signal for controlling permission or prohibition of the pulse number limiting means. 2. The frequency dividing circuit according to claim 1, further comprising: counter means for dividing the output signal of said frequency dividing means. 3. The frequency dividing circuit according to claim 1, wherein said frequency dividing means comprises a toggle flip-flop circuit. 4. The pulse number limiting means includes a logic circuit that outputs an OR logic of the clock signal and the control signal, and the control signal is such that the pulse number limiting means outputs a pulse of the clock signal. 4. The frequency dividing circuit according to claim 1, wherein the potential level is relatively high only during a period in which the frequency division is prohibited. 5. The frequency dividing circuit according to claim 1, further comprising timing adjusting means for inputting said control signal to said pulse number limiting means at a predetermined timing. .