JP2001119287A - High-speed and small-noise output buffer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high-speed and small-noise output buffer which is provided with many control functions equivalent to specifications of a GTL+ signal. SOLUTION: In the output buffer, general and speed driving elements exist together to drive the final output element. When an input signal is changed from a first logical level to a second logical level, the general and the speed driving elements simultaneously start functioning. The speed driving elements pulls down a control voltage of the output element to a potential different from the expected final potential. The general driving element pulls down it to a potential approximating the expected final potential. The output potential of the output element is first quickly changed and then is slowly changed toward the final potential. Large ring back doesn't occur in the output signal, and the delay time of the output buffer is shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output buffer, and more particularly, to a high-speed, low-noise output buffer having a number of control functions equivalent to the specification of a GTL + signal.

[0002]

2. Description of the Related Art In a typical digital circuit, 0V and 5V are used.
These two digital signals generally indicate two different logic levels. Devices used in digital circuits include TTL devices and CMOS devices. TTL
A digital circuit constituted by devices has a high switch speed but consumes a large amount of DC power. On the other hand, CMOS
Digital circuits composed of devices have low DC power consumption, but have low switch speeds and are noisy. Further, as the operating frequency of digital circuits increases to tens of MHz, improperly placed or isolated devices in digital circuits can cause electromagnetic interference (EMI) problems.

[0003] The operating voltage of CMOS digital circuits has been decreasing with the development of semiconductors. If the operating voltages of the two integrated circuits (hereinafter referred to as “ICs”) arranged at both terminals of the transmission line do not match, the two ICs
Outputs two high logic levels of different potentials. In order to solve the above-mentioned problem, GTL (Gunning Transceive) is provided in the output buffer.
r Logic) signal specifications are introduced. In the second half, an improved GTL + signal specification is provided. G
The magnitude of the TL + signal is between 0 V and 1.5 V, and one end of the signal transmission line is connected via a terminator to 1.
Because it is connected to 5V, when the transmission line is used for bi-directional transmission, the difference between the operating voltages of the two ICs cannot make their outputs a high potential difference.

[0004] In FIG. 1, the output buffer 100 receives the input signal A, and transmits the output signal _{V 0.} here,
Generally, the input signal A includes two logic levels of a high potential and a low potential, and the output signal V ₀ changes according to the input signal A. Next, the output signal V ₀ is sent to the input / output terminal of another device 171 via the transmission line 160. FET1
Since the open drain method is used to connect the T.30, the two-way transmission is performed on the transmission line.
When the FET 130 is turned off, the input buffer 180 can receive a signal from another device 172. To equalize the high potential between the two-way transmissions, one end of the transmission line 160 is connected to the terminating resistor 16
5 and a power supply Vtt (generally, 1.5 V).

The output buffer 100 includes two drive transistors (hereinafter, referred to as “FETs”) 110 and 120.
And an output transistor (hereinafter, referred to as “FET”).
130. Two drive transistors 110 and 12
0 receives the input signal A and generates sufficient drive current to drive the output transistor 130. Second, the output transistor 130 provides stronger driving capability,
Driving another device connected to the transmission line 160.

When input signal A is at a low potential, FET1
10 is turned on to raise the potential of the gate of FET 130 to a high potential, thereby
Turns on. Furthermore, the potential of the output signal V ₀ is lowered to near ground potential. Resistance of the terminating resistor 165 is Rtt, if the resistance value of the FET130 after being turned on Rm, the output voltage _{V 0} in the low potential is expressed as follows.

V ₀ = V _tt × R _m / (R _m + R _tt ) When the input signal A is at a high potential, the FET 120 is connected to the FET 1
The gate of 30 is turned on to pull it down to ground, thereby turning off FET 130. Since FET130 is connected to the transmission line 160 at the open-drain system, when the FET130 is turned off, the potential of the output signal _{V 0} is pulled to the power supply Vtt so that a high potential. Further, the output state can be changed to the input state, and the input buffer 180 can receive a signal sent from another device.

In FIG. 2, a waveform (A) shows an input signal A. Here, the low potential changes to a high potential at time t1. Here, attention is paid to the fluctuation of the signal of the output buffer.
Further, a time delay of the input signal A is omitted. When operating at low frequency, low potential after the delay time d1 as shown in waveform (B) showing the output potential V _0, changing to completely high potential. Therefore, a method of increasing the operating frequency by shortening the delay time d1 is important. However, the minimum value of the driving capability of the output transistor is determined by the specifications of the general-purpose output buffer. Therefore, only the performance of the driving current of the driving transistor of the output buffer 100 can improve the switching speed of the transistor. However, if the driving current performance of the driving transistors 110 and 120 is simply improved in order to reduce the delay time, the output signal is further deteriorated. As can be seen from the waveform (C) of FIG. 2, after a delay time d2, the output potential V ₀ which is changed from the low potential to a high potential. However, FET1
Since the switch 30 is quickly turned off, if the rate of change of the output potential V ₀ exceeds, the ringback indicated by the reference symbol P occurs. Therefore, it becomes difficult for the receiving terminal to distinguish between the signals of the logic levels "0" and "1", and the system becomes unstable.

As described below, the disadvantages of the prior art output buffer as shown in FIG. 1 are clear.

(1) The noise is reduced by lowering the driving capability of the driving transistor of the output buffer, which slows down the turn-on and turn-off of the output transistor and increases the delay time.
The operating frequency cannot be increased.

(2) By increasing the operating frequency, the driving capability of the driving transistor of the output buffer can be visually improved. However, this causes the output transistor to turn on and off quickly, increasing the switch speed. That is, although the operating frequency is improved, ringback is likely to occur, which causes unnecessary noise and unstable operation of the system.

[0012]

In view of the above, it is a primary object of the present invention to provide a high speed, low noise output buffer with multiple control functions. This output buffer can efficiently increase the operating frequency without generating ringback or noise.

[0013]

A high speed, low noise output buffer according to a first embodiment of the present invention receives an input signal including a first logic level and a second logic level and transmits an output signal. The output buffer is the first general-purpose driving element, the first
A speed drive element, a second general-purpose drive element, a second speed drive element, and an output element.

The first general-purpose driving element has a first terminal, a second terminal, and a third terminal. The first terminal receives an input signal, and the second terminal is connected to a positive power supply. In the first general-purpose drive element, when the input signal is at the first logic level, the second terminal and the third terminal are conductive.

The first speed driving element has a driving capability of the first speed.
It is very powerful compared to general-purpose drive elements.
It has a terminal and a third terminal. The first terminal receives an input signal, and the second terminal is connected to a positive power supply. In the first speed driving element, when the input signal is at the first logic level, the second terminal and the third terminal are conducted, and thereafter, the first potential difference is generated between the second terminal and the third terminal.

The second general-purpose driving element has a first terminal, a second terminal, and a third terminal. The first terminal receives an input signal, and the third terminal is grounded. In the second general-purpose drive element, when the input signal is at the second logic level, the second terminal and the third terminal are conductive.

The second speed driving element has a driving capability of the second speed.
It is very powerful compared to general-purpose drive elements.
A terminal has a terminal and a third terminal, the first terminal receiving an input signal, and the third terminal is grounded. When the input signal is at the second logic level, the second speed drive element is connected to the second terminal and the third
The terminal conducts, after which a second potential difference occurs between the second terminal and the third terminal.

The output element has a first terminal, a second terminal, and a third terminal. The first terminal is a third terminal of the first general-purpose driving element, a third terminal of the first speed driving element, and a second general-purpose driving element. And the second terminal of the second speed drive element, the third terminal is grounded, and the second terminal transmits an output signal. Further, when the first general-purpose drive element and the first speed drive element conduct, the output element conducts between the second terminal and the third terminal. When the second general-purpose drive element and the second speed drive element conduct, the output element does not conduct between the second terminal and the third terminal.

In the first embodiment of the present invention, the first potential difference ranges from 0V to 1V, and the second potential difference also ranges from 0V to 1V.

A high-speed, low-noise output buffer according to a second embodiment of the present invention includes a first input signal including a first logic level and a second logic level, and a second input signal which is an inverted signal of the first input signal. Receive the signal and send the output signal. The output buffer includes a first general-purpose transistor, a first speed transistor, a second general-purpose transistor, a second speed transistor, and an output transistor.

The gate of the first general purpose transistor receives a first input signal, and the source of the first general purpose transistor is connected to a positive power supply. When the input signal is at the first logic level, the drain of the first general-purpose transistor is conductive.

The first speed transistor has a much stronger driving capability than the first general-purpose transistor, the gate of the first speed transistor receives the second input signal, and the source of the first speed transistor is connected to a positive power supply. Is done. The first speed transistor conducts when the first input signal is at the first logic level, the drain and the source being conducted, and then a first potential difference is generated between the drain and the source.

The gate of the second general purpose transistor receives the first input signal, and the source of the second general purpose transistor is connected to a positive power supply. The drain and source of the second general-purpose transistor conduct when the first input signal is at the second logic level.

The second speed transistor has a much higher driving capability than the second general-purpose transistor. The gate of the second speed transistor receives the second input signal, and the source of the second speed transistor is grounded.
When the first input signal is at the second logic level, the second speed transistor conducts between the drain and the source, and then a second potential difference occurs between the drain and the source.

The gate of the output transistor is connected to the drain of the first general-purpose transistor, the drain of the first speed transistor, the drain of the second general-purpose transistor, and the drain of the second speed transistor. The source of the output transistor is grounded, while the drain of the output transistor transmits an output signal. Further, when the first general-purpose transistor and the first speed transistor conduct, the output transistor conducts the drain and the source.
In the output transistor, when the second general-purpose transistor and the second speed transistor conduct, the drain and the source do not conduct.

In the second embodiment of the present invention, the first logic level has a potential close to the positive power supply, while the second logic level has the second logic level.
The logic level has a potential close to the ground potential. Further, the first general-purpose transistor and the second speed transistor are PMOS FETs, and the first general-purpose transistor, the second general-purpose transistor, and the output transistor are:
It is an NMOS FET. The first potential difference is NMOS FE
T, and the second potential difference is equal to the PMOS F
Equal to the threshold voltage of ET.

[0027]

FIG. 3 shows a high speed, low noise output buffer 300 according to the present invention. The output buffer 300 receives the input signal A, and transmits the output signal _{V 0.} Here, the input signal A includes two logic levels of a high potential and a low potential. Further, the output signal V ₀ changes according to the input signal A.

The output buffer 300 includes a driving element 311,
312, 321 and 322 and an output element 330.
After receiving the input signal A, the driving elements 311, 312,
321 and 322 generate sufficient drive current to drive output element 330. Then, the output element 330
Provides a very large driving power to drive other external circuits.

Each of the driving elements 311, 312, 321 and 322 has three terminals. One terminal is a control terminal for receiving an input signal for determining whether or not the other two terminals are to be made conductive. is there. When the input signal A is at a low potential, the driving elements 311 and 312 are turned on, raising the potential of the node 350 to a high potential. on the other hand,
When the input signal A is at a high potential, the driving elements 321 and 32
2 is turned on, pulling the potential of node 350 down to ground potential. Turn-on and turn-off of the output element 330 depend on the potential of the node 350.

Driving elements 311, 312, 321 and 3
22 are divided into two types based on the driving ability. One is composed of driving elements 311 and 312 and is called a general-purpose driving element. The other consists of drive elements 321 and 322 with stronger operating capacity and switch speed,
The potential of the node 350 can be changed quickly. Drive element 31
When 1 is turned on, the potential at node 350 is pulled up near the positive power supply Vcc. On the other hand, the driving element 31
2 is turned on, the node 350 and the positive power supply Vcc
Is maintained at a constant value (for example, 1 V or less). Similarly, when the driving element 321 is turned on, the potential of the node 350 is reduced to near the ground potential.
On the other hand, when the driving element 322 is turned on, the node 35
The voltage drop between 0 and ground is maintained at a constant value (for example, 1 V or less).

The above output buffer 300 can be described by the equivalent circuit of FIG. FET 411 is the driving element 31
1, and the FET 412 and the diode 413 function as the driving element 312. Here, the FETs 411 and 412 are PMOS transistors. FET42
1 functions as the driving element 321, and the FET 422 and the diode 423 function as the driving element 322. Here, the FETs 421 and 422 are NMOS transistors. To achieve the above object, the driving capabilities of the FETs 412 and 422 are much stronger than the driving capabilities of the FETs 411 and 421. Further, the diode 41
When 3 and 423 are turned on, a voltage drop of about 0.
7V appears at both terminals of each diode.

The operation of the high-speed, low-noise output buffer can be described with reference to the waveform diagram of FIG. As shown in FIG. 5, the waveform (A) indicates that the input signal A changes from the high potential to the low potential at the time t. The delay time of the input signal A is omitted.

When the FET 411 is not connected, the FET
If only 412 and diode 413 are taken into account and turned on, then under this condition, waveform (B)
50 potential is shown. After the input signal A changes from the high potential to the low potential, the FET 412 is completely turned on after a delay time d1. As a result, the potential at node 450 is raised to a voltage equal to the positive power supply minus the voltage drop Vx. Here, Vx is a forward voltage drop 0.7 V of the diode 413.

When the FET 412 is not connected,
When only FET 411 is taken into account and turned on, waveform (C) shows the potential of node 450 under this condition. After the input signal A changes from the high potential to the low potential, the FET is completely turned on after a delay time d2. As a result, the potential at node 450 is pulled up to near positive power supply Vcc. The driving capability of FET 412 is FET
412, the delay time d2 is larger than the delay time d1.

When all FETs 411, 412 and diode 413 are taken into account and turned on, under this condition, waveform (D) shows the potential of node 450. When the input signal A changes from the high potential to the low potential, the FETs 411 and 412 are simultaneously turned on.
Since FET 412 is more likely to be involved in driving, the potential at node 450 is quickly pulled up to a voltage equal to the positive power supply Vcc minus the voltage drop Vx. Thereafter, the FET 411 further raises the potential of the node 450 to near the positive power supply Vcc. Node 45
The 0 potential changes from a low potential to a high potential after a delay time d3. Comparing the magnitudes of the delay times d1, d2 and d3, d2>d3> d1.

Furthermore, waveform (E) shows the output signal _{V 0.} The potential of the node 450 is raised to a high potential, and the FET
When 430 is turned on, the potential of the output signal V ₀ is pulled to near ground potential. When the potential of the output signal _{V 0} begins to change once, it decreases rapidly by the function of the FETs 412. After the function of FET 412 is turned off, FET 411 functions alone. Thereby, change in the potential of the output signal V ₀ is delayed. However, the overall descent time is effectively reduced. Further, the ring-back is reduced in the output signal V _0. As a result, a high speed, low noise output buffer according to the present invention is obtained.

The driving element of the output buffer shown in FIG.
Includes T and diode. In actual manufacturing, another output buffer as shown in FIG. 6 is used instead of the more efficient output buffer as shown in FIG. Referring simultaneously to FIGS. 3 and 6, the FET 611 functions as the driving element 311, while the FET 612 functions as the driving element 312. Here, the FET 611 is a PMOS transistor, F
ET612 is an NMOS transistor. Further, F
The ET 621 functions as the driving element 321 and the FET 62
2 functions as the drive element 322. Here, FET6
21 is an NMOS transistor, FET 622 is a PMOS
It is a transistor. To achieve a similar goal, F
The driving capability of the ETs 612 and 622 needs to be much stronger than the driving capability of the FETs 611 and 621.

There are different control methods for NMOS and PMOS transistors. That is, the FET 611
And 621 receive the first input signal A, while FE
T612 and 622 receive a second input signal / A which is an inverted signal of the first input signal. Referring simultaneously to FIGS. 5 and 6, when the input signal A changes from a high potential to a low potential,
The second input signal changes from a low potential to a high potential.

First, only the FET 612 will be described. After the second signal is shifted to a high potential, the FET 61
2 begins to conduct. As is well known, the FET 612 has a threshold voltage. Thus, when FET 612 is fully turned on, the potential at node 650 is not pulled close to the positive power supply. That is, there is a constant voltage drop equal to the threshold voltage between the positive power supply Vcc and the node 650. Due to the transistor size, the threshold voltage will be higher than normal conditions. Therefore, the change in the potential of the node 650 is represented by the waveform (B) as shown in FIG. FET 612 has a very strong drive capability, but can only reduce the potential at node 650 to a potential equal to the positive power supply Vcc minus the voltage drop Vx. Here, the voltage Vx is equal to the FET 612.
Threshold voltage.

Next, a description will be given in consideration of only the FET 611. After the first input signal A changes to a low potential, the FET 61
1 begins to conduct. As can be seen from the waveform (C) in FIG. 5, although the switch speed of the FET 611 is slow,
The potential at 50 is raised to near the positive power supply Vcc. When FETs 611 and 612 operate simultaneously,
The change in the potential of the node 650 is represented by a waveform (D) shown in FIG.
It is clear that is represented by After the FETs 611 and 612 are turned on, the potential at the node 650 is quickly pulled up by the conducting FET 612 to a voltage equal to the positive power supply Vcc minus the voltage drop Vx. As a result, the potential of node 650 is further pulled closer to the positive power supply Vcc.

As before, in the operation of FETs 621 and 622, the potential at node 650 is quickly reduced to a potential equal to the voltage drop Vx that occurs on the ground voltage side. Here, the voltage drop Vx is the threshold voltage of the FET 622. After the function of FET 622 has been turned off, FET 621 still continues to operate, and node 650
Is lowered to near the ground potential.

As mentioned above, the function of the output buffer as shown in FIG. 6 is similar to that of FIG. This output buffer has a short delay time and low noise.

In the actual manufacture of a semiconductor circuit, each NMOS
The switch speed of the FET is directly proportional to the drive current.
In other words, the stronger the driving ability, the faster the switch speed. Further, the driving capability is proportional to the width of the gate of each FET and inversely proportional to the length. Therefore, the driving capability of each FET can be efficiently controlled by adjusting the ratio of the gate width to the length. For example, the ratio of the width to the length of each FET is determined as follows. FET 611 and FET 612:
7, 1: 621 for FET621 and FET622. PMOS
Since the mobility of the FET is lower than the mobility of the NMOS FET, the width-to-length ratio of the PMOS FET is twice the width-to-length ratio of the NMOS FET in a typical transmission gate. Based on that, PMOS FE
T can have the same drive capability as an NMOS FET. Therefore, the driving capability of the FET 612 is
It can be generalized that the driving capability of the FET 622 is larger than the driving capability of the FET 621. Further, the driving capability of the FETs 612 and 622 is F
It is much stronger than the driving capability of ET611 and 621. Therefore, the basic concept of the present invention is different from a general transmission gate. Further, since the FET 630 actually provides the output current to the outside, it has the strongest driving capability.

The present invention provides a high speed, low noise output buffer having a number of control functions equivalent to the GTL + signal specification. In this output buffer, the general purpose and speed drive elements actuate the last output element simultaneously. When the input signal changes from the first logic level to the second logic level, the general purpose and speed drive elements begin to function simultaneously. First, the speed drive element reduces the control voltage of the output element to a potential different from the expected final potential. Next, the universal drive element further reduces the control voltage to near the expected final potential. Therefore, the output potential of the output element changes quickly at first. When approaching the expected final potential, the change in output potential will be slow. Therefore, large ringback on the output signal is eliminated, the delay time of the output buffer is reduced, and a high-speed, low-noise output buffer can be obtained.

As compared with the prior art, the high speed of the present invention,
The low noise output buffer has the following advantages.

(1) When the general purpose and speed drive elements function simultaneously to turn on and off the output transistor, the control voltage of the output element changes quickly first and then slowly to the expected final potential. Thus, the switching speed of the output buffer is greatly improved, and the delay time is efficiently reduced to increase the operating frequency.

(2) The output signal changes quickly at first,
After that, it slowly changes to the expected final potential,
Large ringback is prevented, resulting in reduced noise.

Although the present invention has been described by way of examples and preferred embodiments, the scope of the present invention is not limited to the above embodiments. Rather, it covers the protection of various modifications or similar circuits. Accordingly, the claims should be interpreted broadly to include all such variations and similar circuits.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an output buffer according to a conventional technique.

FIG. 2 is a waveform diagram of input / output signals of an output buffer according to a conventional technique.

FIG. 3 is a block diagram illustrating a high speed, low noise output buffer according to the present invention.

FIG. 4 is a block diagram showing an equivalent circuit of the block diagram shown in FIG. 3;

FIG. 5 is a waveform diagram of input / output signals of the equivalent circuit shown in FIG.

6 is a circuit diagram of a practical example of the block diagram shown in FIG. 3;

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5J055 AX02 AX25 AX54 AX66 BX16 CX24 DX22 DX56 DX72 DX83 EX07 EX21 EY12 EY21 EZ07 FX12 FX17 FX35 GX01 GX04 5J056 AA04 BB02 BB24 DD13 DD29 DD55 FF08 KK01

Claims (3)

[Claims] A high-speed, low-noise output buffer that receives a first input signal including a first logic level and a second logic level and a second input signal that is an inverted signal of the first input signal, and transmits an output signal. A first general-purpose transistor having a gate receiving a first input signal, a source connected to a positive power supply, and having a drain and a source conducting when the first input signal is at a first logic level. The driving capability is much stronger than the first general purpose transistor, the gate receives the second input signal, the source is connected to the positive power supply, and when the first input signal is at the first logic level, the drain and A first speed transistor in which the source conducts, and then a first potential difference occurs between the drain and the source; a gate receiving the first input signal; a source grounded;
When the first input signal is at the second logic level, the second general-purpose transistor having a drain and a source that conducts, the driving capability is much stronger than the second general-purpose transistor, the gate receives the second input signal, and the source receives the second input signal. Is grounded, and when the first input signal is at the second logic level, the drain and source conduct, after which a second potential difference occurs between the drain and the source; and the gate is the first general purpose transistor. The drain, the drain of the first speed transistor, the drain of the second general-purpose transistor, and the drain of the second general-purpose transistor are connected, the source is grounded, the drain transmits an output signal, and the first general-purpose transistor and the first general-purpose transistor are conductive. The drain and source conduct, and the second general-purpose transistor and the second speed transistor When Njisuta conducts, output buffer comprising an output transistor having a drain and source does not conduct, the. 2. A high-speed, low-noise output buffer for receiving a first input signal including a first logic level and a second logic level and a second input signal which is an inverted signal of the first input signal and transmitting an output signal. Wherein the gate receives a first input signal, the source is connected to a positive power supply, and when the first input signal is at a first logic level,
A first general-purpose transistor in which a drain and a source conduct, a driving capability is much stronger than that of the first general-purpose transistor, a gate receives a second input signal, a source is connected to a positive power supply, and the first input signal is When at a first logic level, the drain and source are conducting, then a first speed transistor where a first potential difference occurs between the drain and source, an NMOS FET, the gate receives the first input signal, and the source is A second general-purpose transistor that is grounded and whose drain and source conduct when the first input signal is at the second logic level; and a PMOS FET, whose driving capability is much stronger than that of the second general-purpose transistor, and whose gate is A second input signal is received, the source is grounded, and when the first input signal is at a second logic level, the drain and source conduct and the second input signal is grounded. A second speed transistor in which a second potential difference is generated between the drain and the source; and a gate connected to the drain of the first general purpose transistor, the drain of the first speed transistor, the drain of the second general purpose transistor, and the drain of the second speed transistor. The source is grounded, the drain transmits an output signal, and when the first general-purpose transistor and the first speed transistor are conductive, the drain and the source are conductive, and when the second general-purpose transistor and the second speed transistor are conductive, the drain is And an output transistor whose source does not conduct. 3. A high speed, receiving first input signal including a first logic level and a second logic level and transmitting an output signal.
A low noise output buffer having a first terminal, a second terminal, and a third terminal, wherein the first terminal receives an input signal, the second terminal is connected to a positive power supply,
When the input signal is at the first logic level, the first general-purpose drive element in which the second terminal and the third terminal conduct, and the driving capability is much stronger than the first general-purpose drive element,
A first terminal, a second terminal, and a third terminal, wherein the first terminal receives an input signal, the second terminal is connected to a positive power supply,
When the input signal is at the first logic level, the second terminal and the third terminal conduct, and thereafter, a first speed driving element in which a first potential difference is generated between the second terminal and the third terminal; A second general-purpose driving element having a second terminal and a third terminal, wherein the first terminal receives an input signal, the third terminal is grounded, and the second terminal and the third terminal conduct when the input signal is at a second logic level; The driving capability is very strong compared to the second general-purpose driving element,
It has a first terminal, a second terminal, and a third terminal. The first terminal receives an input signal, the third terminal is grounded, and when the input signal is at a second logic level, the second terminal and the third terminal conduct. ,
Thereafter, a second speed driving element in which a second potential difference is generated between the second terminal and the third terminal, and a first terminal, a second terminal, and a third terminal, wherein the first terminal is a third terminal of the first general-purpose driving element Terminal, a third terminal of the first speed driving element, a second terminal of the second general-purpose driving element, and a second terminal of the second speed driving element, the third terminal is grounded, and the second terminal transmits an output signal. When the first general-purpose drive element and the first speed drive element conduct, the second terminal and the third
An output buffer including an NMOS transistor whose second terminal and third terminal do not conduct when the terminal conducts and the second general-purpose drive element and the second speed drive element conduct.