JP2001117863A - Serial bus deterministic mediation using mediation address - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for guaranteeing that a mediation phase is rapidly and deterministically completed on a serial data bus. SOLUTION: The mediation phase includes that a master device asserts respective mediation addresses onto the serial bus after a communication sequence is started through the use of a start state. After the mediation phase, a controlling master device transmits data transfer on the serial bus. The serial bus and a device connected to it are operated in accordance wit an I2 C interchangeable protocol. The mediation addresses correspond to a slave address related to a slave device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to computer systems, and more particularly, to a deterministic arbitration device for a serial bus, preferably in an I ² C environment.
Systems and methods.

[0002]

2. Description of the Related Art Serial communication is distinguished from parallel communication primarily by transmitting data at a rate of one bit at a time. Serial communication is also simpler to implement, since it requires only a single data channel, either a single data line or a single differential pair. Recently, serial communication has become increasingly popular with the introduction of technologies and protocols such as IEEE 1394, Universal Serial Bus (USB) and Inter IC (Integrated Circuit) bus or I ² C.

[0003] IEEE 1394 and USB are mainly targeted at the computer system level, but I ² C
Was designed for serial communication between integrated circuits. Examples of such integrated circuits include single chip microcontrollers, LCD drivers, random access memory (RAM), digital signal processors (DSP),
A tuner and DTMF generator are included. I ²
C protocol is an ACCESS.COM protocol for connecting peripheral devices to a computer. Note that it is also implemented by bus.

[0004] In addition to power, only ^two signal lines are required for an I ² C compatible bus: a serial data line (SDA) and a serial clock line (SCL). Each device is addressable by a unique address that can be set by software. This bus is controlled by a master device addressing the slave device, which issues clock pulses on the serial clock line while transmitting data bits on the serial data line. The data and clock lines are passively pulled high except when the device is actively asserting a low logic signal on the data or clock lines. The data bit is valid on the data line when the data bit is stable when the clock line is clocked high. In the I ² C protocol,
Only data changes while the clock line is low are allowed.

Referring to FIG. 1, a typical I ² C compliant system 100 is shown. Multiple master devices 1
10A to 110C and a plurality of slave devices 12
Each of 0A through 120C is coupled to serial data line 130 and serial clock line 140. Master device 110, also referred to as master transmitter
And a slave device 12, also referred to as a slave receiver.
Note that the total number of zeros can be varied as desired, up to the I ² C capacity limit for the serial bus, 400 pF. A master device, such as the first master device 110A, cannot act as a slave, while a master device, such as the second master device 110B, uses what is referred to as a master-receiver 112 to create a slave device. It can also work as a device. The master device 110B includes a master-receiver 112 and control logic 113 for controlling access to the serial bus via bus interface logic 111, as shown.

I^TwoC Connect to a serial bus such as a compatible bus
Each device that is paired has its own unique address.
Often associated with a vice. FIG.
And I ^TwoFor devices coupled to a C compatible serial bus
A complete set of addresses 200 is shown. address
Is transmitted on data line 130 as an 8-bit byte.
It is. The first seven bits are the actual device address
Yes, the eighth bit is a read / write bit, "1"
Indicates a READ cycle and “0” indicates a WRITE cycle.
You. Use 7-bit default addressing
And, theoretically, 128 in the complete set of addresses 200
Device addresses are available. These ads
Sixteen of the addresses are on hold 205. Any
Also in the example, some of the addresses are
210 assigned to the device connected to the
The remaining addresses are available 220.

It should be noted that in the I ² C protocol, the master device 110 is assigned an address in at least two cases. The first case is when the master device 110C issues a "hardware general call". This situation applies to a "dumb" master device 110C that does not know the address of the slave device 120 to which it wants to send data. Thus, the dumb master device 110C issues a hardware general call in the first byte and issues its address in the second byte. In the second case, the master device 110
B includes master-receiver 112, or master device 110B could otherwise become a master-receiver.

[0008] Communication sequence 300 on the serial bus
3 is shown in FIG. The master device 110
Under the ² C protocol, 299 when the serial bus is free, that is, the data transmission traffic from another communication sequence 300 only when not happening on the serial bus, for controlling the serial bus Allowed. The communication sequence 300 includes, as a minimum, a start state 310, an initial address phase 320, an initial data phase 330, and an end state 390. The communication sequence 300 may also optionally include one or more repeat start states 315, a repeat address phase 325, and a repeat data phase 335. The communication sequence 300 of the I ² C-compliant bus illustrated in the flowchart of FIG.
Includes decision blocks 340 and 345 for continuing or terminating the communication sequence 300.

The initial data phase 330 and the repetitive data phase 335
May include the transfer of a block of data consisting of data having one or more bytes. A slave device that receives a data block typically acknowledges each byte of data in the data block when receiving. The master device receiving the data block will usually have the exception of the last byte,
Acknowledge each byte of data in the data block upon receipt. This alerts the sending slave device that the data phase 330/335 has ended.

The start state 310 includes the master device 1
10 is the data line 1 while clock line 140 is logic high.
Changing 30 from a logic high to a logic low. Similarly, the end state 390 includes the master device 1
10 includes changing the data line 130 from a logic low to a logic high while the clock line is logic high. Address phase 320/325 and data phase 330/335
The address and data from are transmitted on data line 130 while clock line 140 is clocked to a logic high and are held stable at either a logic low or a logic high. The logic low or logic high of the data line 130 is changed only when the clock line 140 is at a logic low. Note that preferably a logic low represents a "0" and a logic high represents a "1".

In the I ² C environment, the master device 110
Generates its own clock signal on clock line 140. All devices connected to that serial bus are connected to clock line 140 in a wired AND configuration. If clocked low by master device 110, this wired AND
Clock line 1 until all devices communicating over that bus are ready for a logic high on the next clock.
40 is kept in a low logic state. One of the goals of wired AND is to prevent a fast master device 110 from transmitting too fast for a slow slave device 120. Slave device 120
Can extend the logic low for a clock cycle on clock line 140 until data line 130 can accept the next data bit. If necessary, master device 110 can enter a wait state until slave device 120 releases clock line 140 and the clock line changes to a logic high.

The arbitration of control of the bus in the I ² C environment is such that while the bus is free, some or all of the master devices 110 may initiate a new communication sequence 3 on the bus.
00 can be started. I ² C
Is arbitrarily non-deterministic. A plurality of masters 110 may use the same slave device 1 in the same communication sequence 300 without adversely affecting the I ² C system.
It is possible to transfer the same data byte to 20. In fact, all of the participating master devices 110 continue as if they were controlling master devices 110 on that bus.

A plurality of master devices 110X and 1
Whenever 10Y simultaneously generates start state 310 on data line 130 of the serial bus, each master device 110X / 110Y receives the initial address 32 addressed to its respective slave device 120X / 120Y.
0 is transmitted to the data line 130. These slave devices 120X / 120Y may become the same slave device 120X. Since the default state of data line 130 is a logic high, all bits transmitted as "1" on data line 130 are simply clocked on clock line 140. Master device 1
If 10Y conveys "1" and master device 110X conveys "0", then master device 110Y
Is “0” on the data line 130 while transmitting “1”.
Read. Therefore, the master device 110Y
Knows that another master device 110X is also on the bus, master device 110Y relinquishes control of the bus and gives it to master device 110X, which loses arbitration.

This arbitration method provides a method for assigning the priority of the serial bus to a master device 110 that transmits the numerically least significant bit on data line 130 during a given clock cycle.
It has the effect of giving. A master device 110 transmitting a 0 on data line 130 has a higher priority than a master device transmitting a 1. The I ² C protocol allows a master device 110 that has lost arbitration to continue to clock the bus until the end of the current byte being transmitted. The master device 110 that is the master device 110 remaining until the end after the arbitration phase ends is referred to as a controlling master device 110.

In a multiple master environment, several problems can arise due to the I ² C arbitration scheme. The simplest of these is the master device 11 that lost the arbitration.
0 is to lose the clock cycle that the master device 110 could do something else. For example, a microcontroller that instructs the arithmetic and logic unit (ALU) to send data over the serial bus, and subsequently loses the multi-byte arbitration, may have more than 16 clock cycles available for computation. Have lost.

When the losing master device 110 does not end cleanly from the incomplete communication sequence 300, a more conservative problem may arise. For example, the I ² C protocol is ambiguous with respect to the correct termination condition when one master device 110X issues a repeat start state 315 and another master device 110Y issues a termination state 390. In this situation, both master devices 110X / 110Y read the first data byte from the same slave device 120X, and the first master device 110X attempts to read the second data byte, This may occur if the second master device 110Y attempts to end the communication sequence 300. There can be many complex error conditions.

[0017]

What is needed is a way to ensure that the arbitration phase on the serial data bus ends quickly and deterministically. The arbitration preferably ends by the eighth clock cycle of the failed communication sequence. Therefore, it would be desirable to have an apparatus, system and method for speeding up arbitration in a multiple master environment. The apparatus, system and method is compatible with the I ² C protocol, the existing I ² C
Preferably, it can be used with the device. The present invention aims to achieve that.

[0018]

SUMMARY OF THE INVENTION The problems outlined above are primarily solved by an apparatus, system and method for arbitrating a serial bus in an efficient manner. By ending the arbitration of the bus quickly and deterministically, the system can advantageously become more stable,
The computation time lost by a master device that has lost arbitration can be reduced. The arbitration phase involves the master device asserting its associated arbitration address on the serial bus after initiating the communication sequence using the start state. After the arbitration phase, the controlling master device, the serial
The master device that has won the arbitration for controlling the bus
Assert one or more data transfers on the serial bus. In a preferred embodiment, a device connected to the serial bus and serial bus, operating according to I ² C compatible protocol.

According to one embodiment, the system includes data
A serial bus that includes
Includes a master device coupled to the bus. Master
The device determines the start state, arbitration phase and data transfer phase.
Data on the serial bus data line
Transfer data. During the arbitration phase, the master device
Communicate the relevant arbitration address on the real bus data line
Is included. I ^TwoIn the C environment, the mediation phase requires initial
Dress phase is included. The master device has an initial address
Arbitration address related to serial bus data line
Tell

Similarly, in embodiments where the master device and the slave device are coupled to a serial bus, the method also includes the master device initiating a communication sequence on the serial bus by signaling a start condition. suggest. The master device arbitrates for the serial bus in an arbitration phase that involves the master device transmitting an arbitration address associated with the master device on the serial bus. The controlling master device gains control of the serial bus at the end of the arbitration phase. The controlling master device communicates a repeat start status to the serial bus, and then communicates a slave address that addresses the slave device. The slave device will acknowledge this slave address. The controlling master device communicates the data block to the slave device, and the slave device acknowledges the data block. The controlling master device ends the communication sequence by signaling an end status on the serial bus.

Various embodiments of the arbitration address are contemplated. In one embodiment, the arbitration address is
Corresponds to the slave address associated with the device. With at least one slave device for each of the master devices, each arbitration address is:
Preferably, it relates to only one master device. Preferably, the arbitration address initiates a READ cycle and the slave device
Respond with bytes. This data byte can be stored, discarded or ignored by the master device as desired. This feature can advantageously provide for quick termination of the arbitration phase with only one controlling master device on the serial bus after the arbitration phase.

[0022] In another embodiment, the arbitration address is not associated with any of the slave devices coupled to the serial bus. The master device is configured to continue the communication sequence, either during or after the arbitration phase, without receiving an acknowledgment signal responsive to the associated arbitration address. The master device continues the communication sequence with a repeat start state, a repeat address phase, and a repeat data phase for data transfer. A master device that uses an unassigned arbitration address must read or write to the unassigned address.
ITE can be performed. This arbitration phase advantageously terminates quickly with only one controlling master device on the serial bus after the arbitration phase.

In another embodiment, each of the arbitration addresses is associated with an arbitration device coupled to the serial bus. The arbitration device acting as a slave device responding to the plurality of slave addresses accepts the WRITE data in response to receiving the arbitration address,
READ data can be sent, or both. The arbitration device correctly acknowledges all address and data transfers it involves. The arbitration device terminates the arbitration phase cleanly and quickly, with only one controlling master device on the serial bus after the arbitration phase.

[0024]

Other objects and advantages of the present invention are:
The following detailed description will be apparent upon reading the accompanying drawings.

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and will herein be described in detail. However, the drawings and detailed description thereto are not intended to limit the invention to the particular forms disclosed, which, on the contrary, falls within the spirit and scope of the invention, as defined by the claims. It is intended to cover all modifications, equivalents and alternatives.

FIG. 4 Arbitration Address A flow diagram of an embodiment of a communication sequence 400 that includes a deterministic arbitration address phase is shown in FIG. As can be seen, the communication sequence 400
Is compatible with the I ² C protocol. The master device 110 initiates a new communication sequence 400 on the bus only while the bus is free 299.
The communication sequence 400 includes, as a minimum, the start state 4
10, arbitration address phase 420, arbitration data phase 430, repetition start state 415, repetition address phase 425, repetition data phase 435 and end state 490. The communication sequence 400 can optionally include one or more start repeat states 415, a repeat address phase 425, and a repeat data phase 435. Decision block 44
0 indicates either continuation or termination of the communication sequence 400.

Note that the arbitrated address phase 420 replaces the initial address phase 320 of FIG. The form of the arbitration address makes the arbitration address indistinguishable from any other slave address carried on the serial bus. Various implementations and implementations of arbitration addresses are anticipated. Further, in one embodiment, no data is transferred in the arbitration data phase 430 or the arbitration data phase 43
Note that 0 is skipped completely. In this embodiment, the repetition start state 415 indicates that the arbitration address phase 4
Just after 20. The data block transferred during the repeating data phase 435 may include one or more data bytes.

In one embodiment, the arbitration address is the slave address 21 associated with the slave device 120.
Corresponds to 0. Preferably, with at least one slave device 120 for each master device 110, each arbitration address is associated with only one master device 110. The arbitration address preferably initiates a READ cycle, and slave device 120 responds with a data byte. This data byte can be stored, discarded or ignored by the master device as desired. Master device 110 continues communication sequence 400 with repeat start state 415, repeat address phase 425, and repeat data phase 435 for data transfer. This feature advantageously provides for quick termination of the arbitration phase with only one controlling master device on the serial bus after the arbitration phase.

Master Device 110 with Numerically Lowest Arbitration Address Implemented in an I ² C Compliant System
Remain on the serial bus as the controlling master device during arbitration on the serial bus. Preferably, controlling master device 110 acknowledges data bytes read from slave device 120 during arbitration data phase 430. Slave device 120 may control arbitration address phase 42
0, and the arbitration data phase 430 is
20/325/425 and the data phase 330/335 /
435.

If there are more master devices 110 than slave devices 120 connected to the serial bus, but less than twice that number, two master devices
It is expected that a device may be associated with each slave address used as an associated arbitration address. This is possible if the slave device 120 can both send and receive data bytes during the arbitration data phase 430 without causing unexpected behavior or error conditions. The first master device 110X is associated with a slave address as a READ cycle, and the second master device 110Y is
Associated with the slave address as a RITE cycle.

In another embodiment, arbitration address 2
20 is not associated with a slave device 120 coupled to the serial bus. The master device 110 is configured to continue the communication sequence 400 without receiving an acknowledgment signal from the slave device 120 during or after the arbitration phase 420/430. The master device 110 determines whether the transfer of data is in a repeat start state 415, a repeat address phase 425, and a repeat data phase 43.
5, the communication sequence 400 is continued. The master device 110 that uses the unassigned slave address 220 as the arbitration address may read or write the unassigned address 220.
It can be performed. This arbitration phase 420/430 can advantageously be terminated quickly with only one controlling master device on the serial bus after the arbitration phase 420/430.

When all master devices are serial bus
If the slave address attempting communication on the
In a deterministically arbitrated communication sequence 400,
But not I^TwoC Communication using the communication sequence 300
The address to which the master device being attempted is not assigned
Note that it does not generate 220. Therefore,
N master devices 110 are known slave addresses.
I address the address ^TwoIn the C environment, the existing slave
The address of device 120 is used as the arbitration address.
N-1 master devices 110 unless otherwise
Only a communication sequence 400 that is deterministically arbitrated
Must be implemented.

FIG. 5 Arbitration Device In another embodiment shown in FIG. 5, each arbitration address is associated with an arbitration device coupled to the serial bus. An alternative embodiment, master / slave arbitration device 510 and slave arbitration device 520, is shown in FIG.
Shown in The master / slave arbitration device 510 communicates with the master / slave through the bus interface logic 511.
Master device 1 capable of operating as a receiver
Included as part of 10B. Slave arbitration device 5
20 is coupled to and responds to the serial bus in a manner similar to other slave devices 120. Arbitration devices 510/520 are particularly useful in systems that include more master devices 110 than slave devices 120. Use of the arbitration device 510/520 also ensures correct acknowledgment of address and data transfer. This advantageously reduces master device error conditions associated with unacknowledged transfers on data line 130 of the serial bus.

Arbitration device 51 operating as slave device 120 responding to a plurality of slave addresses
0/520 responds to receipt of any of the arbitration addresses associated with the arbitration device 510/520.
It can accept data, send READ data, or both. Arbitration device 510/520
Correctly acknowledges all of the address and data transfers it involves. Arbitration device 510/520
Terminates the arbitration phase cleanly and quickly with only one controlling master device 110 on the serial bus after the arbitration phase. Master device 11
0 continues the communication sequence 400 with the repeat start state 415, repeat address phase 425, and repeat data phase 435 for data transfer.

In one embodiment, one or more master devices 110X-110Z are each associated with a plurality of arbitration addresses. Master device 110X
Communicates a first arbitration address on the serial bus to request a normal or lower priority data transfer. Master device 110X communicates a second arbitration address on the serial bus to request a higher priority data transfer. Additional arbitration addresses specified for higher priority data transfers may be associated with master device 110X if desired.
The arbitration device 510/520 is the master device 11
Respond accordingly to the arbitration addresses associated with 0X.

Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully understood. The claims are intended to be interpreted as including all such variations and modifications.

[Brief description of the drawings]

FIG. 1 is a block diagram of a typical I ² C compliant system including a device coupled to a two-wire serial bus.

FIG. 2 is a block diagram illustrating a normal division of an address space of an I ² C compliant system.

FIG. 3 is a flowchart of an embodiment of a communication sequence of a typical I ² C compliant system.

FIG. 4 is a flow diagram of an embodiment of a communication sequence that includes an arbitrated address phase compatible with an I ² C compliant system.

FIG. 5 is a block diagram of two embodiments of an arbitration device coupled to a two-wire serial bus.

[Explanation of symbols]

100 I ² C-compliant systems 110A~110C master device 111 bus interface logic 112 master - receiver 113 control logic 120A~120C slave device 130 serial data line 140 serial clock line 400 communication sequence 410 start state 415 repeats Start state 420 Arbitration address phase 425 Repetition address phase 430 Arbitration data phase 435 Repetition data phase 440 Decision block 490 End state 510 Master / slave arbitration device 511 Bus interface logic 520 Slave arbitration device

 ────────────────────────────────────────────────── ─── Continuation of the front page (71) Applicant 591064003 901 SAN ANTONIO ROAD PALO ALTO, CA 94303, US A. (72) Inventor Joseph James Elvin United States 01775 Massachusetts Stow Pine Point Road 62 62 Inventor Sandip P. Barua United States 01852 Lowell Massachusetts・ Bowden Street ・ 134 ・ Apartment 101 (72) Inventor John Michael Mulligan Jr. USA ・ 01844 ・ Massachusetts ・ Meshen Chippy Lane ・ 87 F-term (reference) 5B061 AA00 BA01 BB21 SS04 5B077 NN02

Claims (43)

[Claims] 1. A serial bus including a clock line and a data line, and a master device coupled to the serial bus, the master device having a start state communicated on the serial bus. , Configured to transfer data on the serial bus in a communication sequence initiated by a subsequent arbitration phase and a subsequent data transfer phase, wherein the master device transfers data on the serial bus during the arbitration phase. A master device to which an arbitration address associated with the master device is communicated. 2. The system of claim 1, wherein the start condition is communicated on the serial bus only while the serial bus is released. 3. The clock line and the data line,
2. The device of claim 1, wherein each of the devices is passively pulled up high except when each of the devices actively asserts a logic low signal on the clock line or the data line, respectively. system. 4. The system of claim 3, wherein said master device transfers data according to an I ² C compatible protocol. 5. The master device communicates the start condition on the serial bus by changing the data line from high to low while the clock line is high. 2. The system according to 1. 6. The master in which the arbitration phase includes an address portion and a data portion, the address portion generating a clock pulse on the clock line while transmitting the arbitration address on the data line. The system of claim 1, comprising a device. 7. The data bus of claim 1, wherein the data bit is valid on the data line of the serial bus when the data bit is stable when the clock line is clocked high. System. 8. The system of claim 1, wherein said communication sequence is terminated using a termination condition conveyed on said serial bus by said master device. 9. The system of claim 8, wherein the master device communicates an end status on the serial bus by changing the data line from low to high while the clock line is high. System. 10. The communication sequence if the arbitration address corresponds to a slave address that is not assigned to a slave device, and the master device does not acknowledge the slave address by the slave device. The system of claim 1, wherein the system is configured to continue. 11. The master device may further include, when the interface logic of the serial bus detects that the data line is low, when the interface logic of the serial bus is not driving the data line low. Wherein the communication sequence is configured to terminate on the bus, and the communication sequence terminates no later than the end of the current byte being transmitted on the serial bus. 2. The system according to 1. 12. The data transfer phase includes an address and a data block, and the system further comprises one or more slave devices coupled to the serial bus, wherein the one or more slave devices are one or more slave devices. Each of the slave devices has an associated slave address, and whenever the address of the data transfer phase corresponds to the associated slave address, using the acknowledge signal during the immediately following clock cycle. Cereal·
The system of claim 1, including the one or more slave devices configured to respond on a bus. 13. The system of claim 12, wherein the arbitration address corresponds to a slave address assigned to a slave device. 14. A WRITE cycle is indicated by a "0" as the least significant bit of the address of the data transfer phase, and each of the one or more slave devices further comprises: 13. The system of claim 12, wherein the system is configured to respond on the serial bus with the acknowledge signal in a clock cycle immediately after receipt of each byte of the data block. 15. A READ cycle is represented by a "1" as the least significant bit of the address of the data transfer phase, and the master device further comprises a final data
Configured to respond on the serial bus using the acknowledgment signal in a clock cycle immediately following receipt of each byte of the data block during the READ cycle, except for the bytes. Claim 12
System. 16. A second bus coupled to the serial bus.
A master device, wherein the second master device is configured to transfer data on the serial bus in the communication sequence, and wherein a second arbitration address associated with the second master device is: The system of claim 1, further comprising a second master device communicated on the serial bus by the second master device during the arbitration phase. 17. The method according to claim 17, wherein the master device and a second master
Devices simultaneously initiate respective communication sequences by communicating the start condition to the serial bus, and then while the second master device is communicating the second arbitration address to the serial bus, The master device communicates the arbitration address to the serial bus, and the master device and the second master device further have the data line low when not driving the data line low. Is configured to terminate the respective communication sequence on the serial bus when detecting the communication sequence, wherein the communication sequence is terminated without being later than the end of the current byte transmitted on the serial bus, Either the master device or the second master device performs respective communication sequences according to the data transfer phase. The system of claim 16, characterized in that to end the. 18. An arbitration device coupled to the serial bus, wherein the arbitration device is at least N-1 master devices of the N master devices coupled to the serial bus. The arbitration device has an associated slave address corresponding to one of the associated arbitration addresses, and the arbitration device ensures that when the address of the arbitration phase corresponds to any of the associated slave addresses, 18. The system of claim 17, further comprising an arbitration device configured to respond on the serial bus with a arbitration device. 19. The arbitration device further comprising: a clock signal immediately after the acknowledge signal during a subsequent clock cycle whenever the address of the arbitration phase corresponds to any of the associated slave addresses. Each master device is further configured to respond on the serial bus with a data byte in response to a READ cycle in the cycle, wherein each master device further initiates a repetition during a clock cycle immediately following the data byte. 19. The system of claim 18, wherein the system is configured to follow the data byte using a state. 20. One or more slave devices coupled to the serial bus, wherein each of the one or more slave devices has an assigned slave address, and The one or more slaves configured to respond on the serial bus with the acknowledge signal during a subsequent clock cycle whenever the address of the slave corresponds to the assigned slave address. -The system of claim 17, further comprising a device. 21. The controlling master device remaining on the serial bus after the arbitration phase further comprises:
To initiate the data transfer phase, to convey the assigned slave address of the target slave device on the serial bus, and to write data to the target slave device on the serial bus. It is configured to communicate a repeat start condition on the serial bus for either transmitting a block or receiving a read data block from the target slave device on the serial bus. The system according to claim 20. 22. The target slave device, in response to each byte of the write data block,
22. The system of claim 21, wherein the system is configured to respond on the serial bus with the acknowledge signal during a subsequent clock cycle. 23. The controlling master device further comprising, except for the last data byte,
22. The system of claim 21, wherein in response to each byte of the read data block, the system is configured to respond on the serial bus with the acknowledge signal during a subsequent clock cycle. 24. The system of claim 1, wherein each arbitration address is associated with a unique master device. 25. Each arbitration address is further associated with only one slave device.
5. The system according to 4. 26. includes a clock line and a data line, I ²
A serial bus for transferring data according to a C compatible protocol, and a master device coupled to the serial bus, wherein the master device transmits data on the serial bus in a communication sequence according to an I ² C compatible protocol. And an arbitration phase during an initial address phase and an initial data phase, followed by an arbitration address associated with the master device during the arbitration phase. A master device communicated on the serial bus by a device. 27. The arbitration address corresponding to a slave address not assigned to a slave device, wherein the master device further comprises:
27. The communication sequence of claim 26, wherein the communication sequence is configured to convey a repeat start condition on the serial bus if an address is not acknowledged or the initial data phase is not acknowledged. system. 28. The system of claim 26, further comprising one or more slave devices coupled to the serial bus and each configured to transfer data according to an I ² C compatible protocol. 29. The arbitration address corresponding to a slave address assigned to a slave device,
The least significant bit of the arbitration address is a "1" indicating a READ cycle, and the slave device transmits a data byte to the master device in response to receiving the arbitration address so that the slave device transmits the data byte to the master device. And the master device is further configured to continue the communication sequence in response to the slave device responding on the serial bus by transmitting the data byte. Item 30. The system according to Item 28. 30. An I ² coupled to said serial bus.
C. a second master device configured to transfer data on the serial bus in the communication sequence according to a C compatible protocol, wherein a second arbitration address associated with the second master device is the arbitration address. 27. The system of claim 26, further comprising the second master device communicated on the serial bus by the second master device during a phase. 31. The master device and a second master device
Devices simultaneously initiate respective communication sequences by signaling a start condition on the serial bus, and during the initial address phase, the second master device places the second arbitration address on the serial bus. The master device transmits the arbitration address on the serial bus while transmitting, and the master device and the second master device further transmit the data line when the data line is not driven low. Is configured to terminate each communication sequence on the serial bus according to the I ² C compatible protocol when detecting that the master device is low. End each communication sequence before the repeat start state, and only one master device The system of claim 30 that is left to remain active on the bus. 32. An arbitration device coupled to the serial bus, the arbitration device configured to transfer data according to an I ² C compatible protocol, the arbitration device coupled to the serial bus. Done N
31. The system of claim 30, further comprising an arbitration device having an associated slave address corresponding to an arbitration address of at least N-1 master devices of the plurality of master devices. 33. A method for operating a serial bus, wherein at least one master device and at least one slave device are coupled to the serial bus, wherein the master device is on the serial bus. Initiating a communication sequence on the serial bus by communicating a start state to the master device, and the master device participating in an arbitration phase by communicating an arbitration address associated with the master device on the bus. Controlling a master device having a numerically lowest arbitration address among all master devices participating in the arbitration phase to gain control of the serial bus at the end of the arbitration phase; The controlling master device is on the serial bus Signaling a first iterative STARAT state; the controlling master device signaling a slave address on the serial bus; and the slave device associated with the slave address comprising the slave device. Responding on the serial bus with an acknowledgment signal in response to an address, wherein the controlling master device transmits a data block addressed to the slave device associated with the slave address. Communicating on the serial bus; the slave device associated with the slave address responding on the serial bus with the acknowledge signal in response to the data block; The controlling master device But by transmitting the termination state on the serial bus, the method comprising the step of terminating the communication sequence on the serial bus. 34. A second slave device having a second associated slave address is coupled to said serial bus, and said controlling master device is configured to control said acknowledgment signal in response to said data block. Immediately after, transmitting another iteration start state on the serial bus; the controlling master device transmitting the second slave address on the serial bus; and the second slave. The second slave device associated with an address responding on the serial bus using the acknowledgment signal in response to the second slave address; and the controlling master device comprises: The second
Communicating a second data block addressed to the second slave device associated with a slave address on the serial bus; and wherein the second slave device associated with the second slave address comprises: Responding on said serial bus with said acknowledge signal in response to said second data block. 35. The second arbitration address having a second arbitration address numerically less than the second arbitration address.
A master device coupled to the serial bus, wherein the second master device initiates the communication sequence on the serial bus by communicating the start condition on the serial bus; Simultaneously initiating a second communication sequence on the serial bus by communicating the start state on the serial bus; and wherein the second master device communicates the arbitration address on the bus. Joining the arbitration phase by transmitting the second arbitration address on the bus at the same time as the device; and wherein the second master device is output on the serial bus by the master device. The second communication sequence on the serial bus in response to an arbitration address Comprising the steps of ending, the master
Terminating the communication sequence as the controlling master device to end the communication sequence. 36. The method of claim 33, wherein said serial bus transfers data according to an I ² C compatible protocol. 37. A method for operating a communication system including a serial bus and a plurality of devices connected to the serial bus, wherein each master device associates an arbitration address associated with the communication sequence with the master device. When configured to assert on the serial bus during the arbitration phase,
Associating an arbitration address with each master device connected to the serial bus; and associating a slave address with each slave device connected to the serial bus,
The slave device is configured such that one of the master devices of a plurality of master devices is the slave device.
Associating a slave address responsive to the one master device on the serial bus when outputting the slave address associated with the device, wherein one or more master devices are connected during an arbitration phase. Participating in the arbitration phase of the communication sequence by each of the master devices transmitting their associated arbitration address on the serial bus; and A controlling master device associated with the numerically lowest arbitration address gains control of the serial bus at the end of the arbitration phase; and wherein the controlling master device is a first slave device. The slave address associated with the serial bus on the serial bus. Communicating; the first slave device responding to the controlling master device by acknowledging receipt of the slave address associated with the first slave device; The master device is the first device
Communicating a block of data addressed to a slave device on the serial bus. 38. Serial bus interface logic configured for arbitration of a serial bus, the serial bus interface logic communicating by communicating a start condition on the serial bus. Serial bus interface logic configured to initiate a sequence and to communicate an arbitration address on the serial bus immediately after the start condition. 39. The serial bus interface
Logic is I ^TwoC According to the compatible protocol
39. The method according to claim 38, wherein data is transferred on a real bus.
Serial bus interface logic. 40. The serial bus interface according to claim 38, wherein the arbitration address corresponds to a slave address assigned to a slave device.
logic. 41. The communication sequence when the arbitration address corresponds to a slave address not assigned to a slave device and the serial bus interface logic further comprises the arbitration address is not acknowledged. 39. The serial bus interface logic of claim 38, wherein the serial bus interface logic is configured to continue processing. 42. The arbitration address is associated with an arbitration device configured to respond on the serial bus with an acknowledgment signal within a clock cycle immediately after receiving the arbitration address. Serial bus interface logic as described in. 43. The serial bus interface logic further comprising: when the serial bus interface logic detects that the data line is low when the serial bus interface logic is not driving the data line low.
39. The serial communication system according to claim 38, wherein the communication sequence is configured to terminate the communication sequence on the serial bus, and the communication sequence terminates no later than the end of the current block transmitted on the serial bus. ·bus·
Interface logic.