JP2001117610A - Programmable controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce transfer data by eliminating the need to define invalid data with respect to data to be transferred from a CPU module to a loader in a programmable controller. SOLUTION: In a CPU module 1, whether data are present is judged, and if it is judged that any data are present, a status is set so as to be valid, and valid data are prepared, and when it is judged that no data are present, the status is set so as to be invalid, invalid data are prepared, and transferred to a loader 2. In the loader 2, whether the status is valid is judged, and if it is judged that the status is valid, message display pertinent as the processing of the valid data for responding to the status is operated, and if it is judged that the status is invalid, data processing is not operated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a programmable controller.

[0002]

2. Description of the Related Art Programmable controllers (hereinafter referred to as P
The control contents in the process control field to which LC is abbreviated can be roughly classified into sequence control and numerical operation control. Initial PLCs, for example, only execute sequence control (so-called bit-based logic control), which is a function of a conventional relay board.
It has a numerical operation control function (so-called word amount control rather than word amount control), and from the viewpoint of economy, it has also added computer functions such as a data processing function.

As described above, as the control contents of the PLC are expanded and complicated, it is necessary to enhance the self-diagnosis function of the PLC so that a recovery operation can be performed in a shorter time when a failure occurs.

FIG. 1 shows the concept. 1 is a CPU,
Interface between memory and loader (I /
O) and the loader 2
In accordance with the program supplied from, a plurality of station number modules (# 1 to # 4) 3, which are other modules, are controlled. The memory in the CPU module 1 includes a power-on initialization program, a self-diagnosis program of its own module,
A storage area for a diagnostic program of another module, a program or the like supplied from the loader 2, a data storage area, C
It has a PU work area and the like. The station number module is, for example, a function module such as an input / output module (digital or analog), a communication module, and simple positioning. The loader 2 includes, for example, a personal computer, a workstation, or the like, and is connected to the CPU module 1 directly or via a network or the like. The CPU module 1 collects the self-diagnosis result of its own module and the diagnosis result of another module and delivers it to the loader 2, and the loader 2 displays the contents as a message.
Examples of the delivery data are shown in FIGS. Both cases are 4 data cases, the former case where each data is valid data, and the latter case where data 1 and 2 are valid and data 3 and 4 are invalid. Taking battery information as an example, valid data is a CPU module that can be loaded with a battery.
Indicates information such as "battery normal", "battery abnormal", and "battery not mounted". The invalid data indicates information that makes it unnecessary to display a message in the loader, such as “battery cannot be mounted”, for a CPU module without a battery mounting function.

The delivery data is created on the CPU module side and used on the loader side.

Referring to FIG. 4, the procedure for creating the above-described delivery data on the CPU module side will be described.
First, in step 1 (S1), N = 1 is set in a pointer N for data reference, and in S2, it is determined whether or not there is data at N = 1 with reference to the pointer N. If so, valid data is created in S3 and the process proceeds to S4, where S2
If there is no data, invalid data is created in S5 and the process proceeds to S4. In S4, the value of the pointer N is updated by one,
The above procedure is repeated until N = 4 (S6). Referring to FIG. 5, the processing procedure of the transfer data on the loader side will be described. First, in step S7, the same pointer N is set to N = 1, and in step S8, the data N is referred to by referring to the pointer N. It is determined whether or not the data is valid. If the data is valid, processing of the data is performed in S9, that is, a corresponding message is displayed and S1 is performed.
The process proceeds to S10, and if invalid in S8, the process proceeds to S10 without performing data processing. In S10, the value of the pointer N is updated by one, and the above procedure is repeated until N = 4 (S11).

[0007]

In the above-described conventional apparatus, invalid data as well as valid data is required to be transferred from the CPU module to the loader.
Therefore, invalid data other than valid data had to be defined.

It is an object of the present invention to provide a programmable controller which does not require the definition of invalid data and can further reduce the data to be transferred.

[0009]

According to a first aspect of the present invention, there is provided a CPU module for controlling a controlled device, wherein the CPU module and the CPU module can mutually transmit data. A programmable controller having a loader for loading a desired program into a module, wherein the CPU module includes means for adding information on the predetermined data to predetermined data to be transferred to the loader; A determination unit for determining information on the predetermined data transferred from the CPU module; and a unit for processing the predetermined data transferred from the CPU module based on the determination of the determination unit. I do.

Therefore, it is not necessary to define invalid data as the predetermined data.

According to a second aspect of the present invention, in the first aspect, the information on the predetermined data is a status indicating whether the predetermined data is valid or invalid.

Further, the invention according to claim 3 is characterized in that, in claim 2, the CPU module does not deliver invalid data to the loader.

For this reason, invalid data in the delivery data is reduced.

According to a fourth aspect of the present invention, in the first aspect, the information on the predetermined data is information indicating a size of the predetermined data.

For this reason, the invalid data portion of the delivered data is reduced, and the invalid data portion in one data is also deleted.

[0016]

FIG. 6 is a block diagram showing an embodiment of the present invention. The CPU module 1 has a CPU 1A
9, 13, and 17, a power-on initialization program, a self-diagnosis program of the own module, a diagnosis program of another module, a program supplied from the loader 2, and the like. And a system memory 1B having a data storage area, a CPU work area, and the like, and an interface (I / O) 1C between the loader 2 and the system memory 1B. These are connected via a bus 1D. On the 1D, other modules, that is, a plurality of station number modules (# 1 to # 4) 3 are connected. The CPU module 1 executes a self-diagnosis program of its own module and a diagnosis program of another module according to a program in the memory 1B, and further, a plurality of station number modules (# 1
~ # 4) 3 is controlled.

The loader 2 comprises, for example, a personal computer, a work station or the like, and has a CPU 2A.
And a ROM 2B storing a system-specific program
And an external storage device 2C such as a hard disk storage device storing programs to be supplied to the CPU module 1.
A RAM 2D having a work area for the CPU 2A, and a keyboard 2 as input means for inputting instructions, numerical values, and the like.
E, a display 2F as a display means, and an interface (I / O) 2G between the CPU module 1 and the I / O 2G and the I / O 1 on the CPU module 1 side.
C is connected directly or via a network or the like. The programs described in FIGS. 10, 14, and 18 are loaded into the RAM 2D at the time of execution, for example, and executed by the CPU 2A.

7 to 10 show the first embodiment. FIG. 7 corresponds to FIG. 2, FIG. 9 corresponds to FIG. 4, and FIG. 10 corresponds to FIG.

As shown in FIG. 7, the delivery data in the present embodiment has a status 8 indicating data valid / invalid,
FIG. 8 shows an example in which a part of the conventional delivery data is added.
As shown in FIG. 7, there are four statuses 8 corresponding to the four data shown in FIG. 7, and the validity is represented by 1 and the invalidity is represented by 0.

FIG. 9 shows the CP of the delivery data shown in FIG.
This shows the creation procedure on the U module side.
Except for S51, it is the same as FIG. At S2, it is determined whether or not there is data at N = 1, and if so, at S31, the status is set to valid, and valid data is created.
If no data is found in S2, the status is set to invalid in S51, and undefined data (any data such as valid data or invalid data) is created, and the flow proceeds to S4.

FIG. 10 shows the processing procedure on the loader side of the delivery data, and is the same as FIG. 5 except for S71 and S81. In S71, N = 1 is set in the pointer N for data reference and the pointer N for status reference. In S81, it is determined whether or not the status N is valid. Processing of valid data in response to the status, that is, displaying a corresponding message, proceeds to S10, and if invalid in S81, proceeds to S10 without performing data processing.

FIGS. 11 to 14 show the second embodiment. FIG. 11 corresponds to FIG. 2, FIG. 13 corresponds to FIG. 4, and FIG. 14 corresponds to FIG.

As shown in FIG. 11, the delivery data in this embodiment is only valid data, and a status 8 indicating data valid / invalid is added to a part of the delivery data. As shown in FIG. 12, there are four statuses 8 corresponding to a total of four pieces of valid and invalid data, and validity is represented by 1 and invalidity is represented by 0.

FIG. 13 shows the delivery data shown in FIG.
This shows the creation procedure on the CPU module side.
Other than 2 is the same as FIG. 4 and FIG. At S2, it is determined whether or not there is data at N = 1, and if so, at S31,
The status is set to be valid, valid data is created, and the process proceeds to S4. If there is no data in S2, the status is set to invalid in S52 and S is generated without creating data.
Proceed to 4.

FIG. 14 shows a processing procedure on the loader side of the delivery data, and is the same as FIGS. 5 and 10 except for S91. At S81, it is determined whether or not the status N is valid. If the status N is valid, at S9, processing of valid data responding to the status, that is, a corresponding message is displayed, and the process proceeds to S10. If there is S91
Without performing data processing (there is no data, so the pointer of the data position is not advanced), and the process proceeds to S10.

FIGS. 15 to 18 show the third embodiment. FIG. 15 corresponds to FIG. 2, FIG. 17 corresponds to FIG. 4, and FIG. 18 corresponds to FIG.

As shown in FIG. 15, the delivery data in the present embodiment is only effective data, and data effective size information 14 indicating the effective data size is inserted into the delivery data. As shown in FIG. 16, the data valid size information 14 has four data corresponding to a total of four valid and invalid data, and represents the data size for valid data 1 and 4, and invalid data, that is, Data 2 and 3
Represents a size 0.

FIG. 17 shows the delivery data shown in FIG.
This shows the creation procedure on the CPU module side.
2 is the same as FIG. 4 except for S53. In S2, it is determined whether or not there is data at N = 1.
Then, the data size is set, valid data is created, and the process proceeds to S4. If there is no data in S2, the process proceeds to S53.
Without setting the data size to zero and creating data
Proceed to 4.

FIG. 18 shows a processing procedure of the transfer data on the loader side, and is the same as FIGS. 5 and 14 except for S92, S93 and S94. In S92, it is determined whether or not the data size is zero from the data effective size information of the data N. If not, data processing (message display) for the data size is performed on the data N in S93, If so, the data processing is not performed in S94 (there is no data, so the pointer of the data position is not advanced), and
Go to 10.

[0030]

As described above, according to the present invention,
With respect to the data to be transferred from the CPU module to the loader, it is not necessary to define invalid data, and the transferred data can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the concept of a programmable controller.

FIG. 2 is a diagram showing an example of conventional delivery data.

FIG. 3 is a diagram showing another example of conventional delivery data.

FIG. 4 is a flowchart illustrating a procedure for creating delivery data on the CPU module side.

FIG. 5 is a flowchart illustrating a processing procedure on the loader side of delivery data.

FIG. 6 is a block diagram showing an embodiment of the present invention.

FIG. 7 is a diagram illustrating an example of delivery data according to the first embodiment.

FIG. 8 is a diagram illustrating an example of a status according to the first embodiment.

FIG. 9 is a flowchart showing a procedure for creating the delivery data shown in FIG. 7 on the CPU module side.

FIG. 10 is a flowchart showing a processing procedure on the loader side of the delivery data.

FIG. 11 is a diagram illustrating an example of delivery data according to the second embodiment.

FIG. 12 is a diagram illustrating an example of a status according to the second embodiment.

FIG. 13 is a flowchart showing a procedure for creating the delivery data shown in FIG. 11 on the CPU module side.

FIG. 14 is a flowchart showing a processing procedure on the loader side of the delivery data.

FIG. 15 is a diagram illustrating an example of delivery data according to the third embodiment.

FIG. 16 is a diagram illustrating an example of data valid size information.

FIG. 17 is a flowchart showing a procedure for creating the delivery data shown in FIG. 15 on the CPU module side.

FIG. 18 is a flowchart showing a processing procedure on the loader side of the delivery data.

[Explanation of symbols]

 1 CPU Module 1A CPU 1B Memory 1C I / O 2 Loader 2A CPU 2B ROM 2C External Storage 2D RAM 2G I / O

Claims (4)

[Claims] 1. A programmable controller comprising: a CPU module for controlling a controlled device; and a loader capable of mutually transmitting data between the CPU module and loading a desired program into the CPU module. The CPU module includes means for adding information on the predetermined data to the predetermined data to be transferred to the loader, wherein the loader has a determination unit for determining information on the predetermined data transferred from the CPU module. A means for processing the predetermined data transferred from the CPU module based on the judgment of the judgment means. 2. The programmable controller according to claim 1, wherein the information on the predetermined data is a status indicating whether the predetermined data is valid or invalid. 3. The programmable controller according to claim 2, wherein the CPU module does not pass invalid data to the loader. 4. The programmable controller according to claim 1, wherein the information on the predetermined data is information indicating a size of the predetermined data.