JP2001103503A - Digital costas loop circuit and control method for it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a digital Costas loop circuit that can decide a required frequency with high accuracy. SOLUTION: The digital Costas loop circuit 22 includes a phase difference detection circuit 22, which detects a phase difference on the basis of signals I', Q'. This digital Costas loop circuit first tentatively decides the frequency in the 8 PSK mode. That is, a synchronization detection circuit 30 detects presence of synchronization on the basis of a synchronous word signal included in a synchronizing signal part. When detecting the presence of synchornization, the synchronization detection detection circuit 30 sets a PBSK mode and decides the frequency on the basis of a TMCC signal included in the synchronizing signal part. That is, even when the presence of the synchronization is detected, the frequency is a little deviated from the accurate frequency, the deviation is corrected in the BPSK mode. Since the frequency is tentatively decided in the 8 PSK mode and then the frequency is decided in the BPSK mode, the frequency can accurately be decided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital Costas loop circuit, and more particularly to a digital Costas loop circuit for removing a residual carrier component contained in a digital reception signal.

[0002]

2. Description of the Related Art An example of a conventional control method in a digital Costas loop circuit of this type is disclosed in Japanese Patent Application Laid-Open No. Hei 9-186730 [H0] filed on Jul. 15, 1997.
4L27 / 22, H04L 7/00, H04L 27
/ 38]. In the absolute phase detector and the digital modulation wave demodulator, a carrier transmitted from the transmission side is demodulated by the 8PSK method, and a plurality of synchronization signal points on orthogonal coordinates are averaged. Then, when the averaged synchronization signal point is shifted, the position of the synchronization signal point is captured and the synchronization signal is detected.

[0003]

However, in this prior art, since the frequency is determined in the 8PSK mode, if the frequency is not determined accurately, for example, as shown by a point A11 in FIG. Frequency is Δ against frequency
It shifts by f11. That is, when a burst signal is transmitted from the transmission side at a frequency corresponding to the position of 000, the frequency is shifted by Δf11,
The phase difference θ11 corresponding to 1 is gradually accumulated.
For this reason, if the phase is shifted to the left area with respect to the axis of the Q signal, the burst signal cannot be detected, and the carrier cannot be reproduced. That is, the frequency accuracy was poor.

[0004] Therefore, a main object of the present invention is to provide a control method in a digital Costas loop circuit that can accurately determine a frequency in carrier reproduction using a burst signal.

[0005]

A first aspect of the present invention is a phase difference detecting means for detecting a residual carrier component as a phase difference from I and Q signals including a residual carrier component, and outputs frequency correlation data corresponding to the phase difference. Numerical control signal generating means, and multiplier data output means for outputting multiplier data for complex operation according to the frequency correlation data, a digital Costas loop circuit for performing carrier regeneration using a burst signal, PS of the maximum modulatable phase value n (n is a natural number of 2 or more) of digital data including
First frequency error generating means for outputting frequency error data in the K mode, second frequency error generating means for outputting frequency error data in the BPSK mode, synchronous detecting means for detecting the presence / absence of synchronization, When the first control means activates the phase difference detection means and the second frequency error generation means and activates the first frequency error generation means, and the presence of synchronization is detected, the phase difference detection means and the first frequency error detection means are disabled. A second control means for activating the second frequency error detection means, and a predetermined period after the activation of the second frequency error detection means, the first frequency error detection means and the second frequency error detection means are disabled. A digital Costas loop circuit comprising a third control means for turning on and activating the phase difference detection means.

A second invention is a control method in a digital Costas loop circuit for performing carrier regeneration using a burst signal. (A) The maximum modulatable phase value n (n is a maximum value) of digital data including a burst signal In the digital Costas loop circuit, the frequency is temporarily determined in the PSK mode of (2 or more natural numbers), (b) the frequency is determined in the BPSK mode in response to the detection of the synchronization pattern, and (c) the phase shifts to phase control. It is a control method.

[0007]

In the digital Costas loop circuit according to the first aspect of the present invention, the phase difference detecting means includes I, Q signals including residual carrier components.
The residual carrier component is detected as a phase difference from the signal. The frequency correlation data corresponding to the phase difference is output from the numerical control signal generating means, and the multiplier data output means outputs multiplier data for complex operation according to the frequency correlation data.
Therefore, residual carrier components included in the I and Q signals are removed. For example, a carrier (digital data) includes data of a plurality of different modulation schemes and is reproduced using a burst signal.

When the synchronization detecting means detects that there is no synchronization, the first control means disables the phase difference detecting means and the second frequency error generating means and activates the first frequency error generating means. Accordingly, the first frequency error generating means outputs frequency correlation data (data relating to the frequency difference) corresponding to the phase difference in the PSK mode having the maximum modulatable phase value n (n is a natural number of 2 or more) of the digital data. . For example, if the digital data is data in which 8PSK modulation, QPSK modulation, and BPSK modulation are mixed, the 8PSK mode having the maximum phase value is set. When the residual carrier component is almost removed based on the output from the first frequency error generating means, for example, a synchronous word signal is detected,
Synchronization detecting means detects the presence of synchronization. In other words, the frequency is provisionally determined.

When the synchronization detecting means detects the presence of synchronization, the second control means disables the phase difference detecting means and the first frequency error generating means and activates the second frequency error generating means. Therefore, the BPSK mode is set and the BPSK mode is set.
Frequency correlation data corresponding to the phase difference in the mode is output from the second frequency error generating means. Based on this output, the residual carrier component is removed, and an accurate frequency is determined.

When the correct frequency is determined, ie, the second
When a predetermined period elapses after the activation of the frequency error generating means, the third control means disables the first frequency error generating means and the second frequency error generating means and activates the phase difference detecting means. Therefore, frequency correlation data corresponding to the phase difference is output, and the residual carrier component is removed.
That is, the locked state of the phase is maintained.

[0011] In the digital Costas loop circuit of the second invention, carrier reproduction is performed using a burst signal. First, the digital Costas loop circuit detects, for example, a synchronization word signal in a PSK mode (n-valued PSK mode) having a maximum modulatable phase value n (n is a natural number of 2 or more) of digital data. In other words, the frequency is temporarily determined. When a sync word signal is detected, BPSK
The mode is set, and the frequency is determined based on the BPSK-modulated TMCC signal following the synchronization word signal. As described above, after the frequency is temporarily determined in the n-value PSK mode, the BP
Since the frequency is determined in the SK mode, an accurate frequency is determined. Subsequently, the process is shifted to the phase control. Specifically, the locked state of the phase is maintained using a loop filter.

[0012]

According to the present invention, the frequency is determined in the BPSK mode after the frequency is temporarily determined in the n-valued PSK mode, so that the frequency can be determined accurately.

The above objects, other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.

[0014]

Referring to FIG. 1, a BS digital broadcast receiver 10 of this embodiment includes a tuner 12 and a tuner 12.
Is connected to the antenna 14. The digital data of the BS digital broadcast received by the antenna 14 is given to the tuner 12, and the tuner 12 down-converts the digital data into a desired intermediate frequency signal (IF signal).

The digital data is, as shown in FIG.
One frame includes 39936 symbols, and the leading part of one frame is a synchronization signal part. Here, the symbol is
A signal received in synchronization with one clock. As can be seen from the figure, the synchronization signal portion is composed of a synchronization word signal and a TMCC signal (transmission multiplex control signal) following the synchronization word signal. The TMCC signal includes a slot control signal and a transmission system (BPSK system, QPSK system, and 8PSK system).
K) is control information. The number of symbols (signal points) of the synchronization word signal and the TMCC signal is 192, and the number of symbols of the synchronization word signal is 40 among them. The TMCC signal and the synchronization word signal are
Modulated in the K system and transmitted. That is, unless the TMCC signal is detected, the modulation method (transmission method) of the signal following the synchronization signal portion cannot be known, so that the signal is modulated by the BPSK method which is strongest against noise.

As described above, the data (video signal and audio signal) and the carrier lock burst signal are alternately arranged following the synchronization signal portion. The number of symbols of each data is 203, and the number of symbols of the burst signal is 4. Since the burst signal is also a signal necessary for synchronization, it is modulated by the BPSK method which is strongest against noise. The data is BPSK modulation, QPS
K modulation or 8PSK modulation is performed. In this embodiment, in the same frame, following the synchronization signal portion, the signals are arranged in the order of increasing number of phases, that is, 8PSK modulation, QPSK modulation, and BPSK modulation.

A set of data and a burst signal is one set, and a set of four consecutive sets is called one slot. Each slot is modulated by various modulation methods.
When the frequency (phase) is locked, the synchronization word signal is detected, the frame is synchronized, and then the content of the TMCC signal is demodulated to determine what modulation system data is transmitted and in what order. You can know.

Here, the digital data transmitted from the transmission side has eight frames in one cycle unit. The eight frames in one cycle unit are called a superframe.
Further, the synchronization word signal is added before and after the TMCC signal of each frame of the super frame, and a first synchronization word for synchronizing the transmission frame is added before the TMCC signal of each frame. In addition, a second synchronizing word for identifying a first frame among super frames is added. Further, a third synchronization word obtained by inverting all bits of the second synchronization word is added to the second to eighth frames.
The frame is identified by adding such a synchronization word.

Returning to FIG. 1, the IF signal output from the tuner 12 is supplied to a quadrature detection circuit 16 and subjected to quadrature detection. Therefore, baseband analog I and Q signals are obtained. The analog I signal and Q signal are converted into digital signals by the A / D converter 18 and supplied to the Nyquist filter 20. The Nyquist filter 20 removes unnecessary high frequency components included in the digital I signal and Q signal, and performs a filtering process for preventing intersymbol interference. The I signal and the Q signal via the Nyquist filter 20 are provided to a complex multiplying circuit 24 of the digital Costas loop circuit 22.

The complex multiplying circuit 24 executes a complex operation shown in Equation 1 using the sin data (sin θ) and the cos data (cos θ) output from the ROM 26 to remove residual carrier components.

[0021]

## EQU1 ## I '= I.times.cos .theta. + Q.times.sin .theta. Q' = Q.times.cos .theta.-I.times.sin .theta. The I 'and Q' signals thus generated by the arithmetic processing are output to a signal processing circuit (not shown) at the subsequent stage. And the phase difference detection circuit 28 and the synchronization detection circuit 3
0 is given.

A phase difference detecting circuit 28 detects a phase difference based on the I 'signal and the Q' signal, and supplies the detected phase difference to a loop filter (LF) 32 via a switch SW1 and a frequency for 8PSK. (F) It is given to the output circuit 34 and the BPSK f output circuit 36. The LF 32 removes high-frequency components included in the phase difference, and gives the NCO 36 a phase difference from which the high-frequency components have been removed. NCO36 is LF3
2 to generate a control signal θ for removing the residual carrier component. That is, si
Generate parameters for n data and cos data,
Give to OM26. Therefore, in the ROM 26, NC
The SINR based on the control signal θ given from O36
The sin data (sin θ) and the cos data (cos θ) are read from the OM 26a and the COSROM 26b. The sin data and the cos data are supplied to the complex multiplying circuit 24, and the operation shown in Expression 1 is executed. The phase difference detection circuit 28 also controls the on / off of the switch SW1, and keeps the switch S1 until the frequency is determined.
When W1 is turned off and the frequency is determined, switch SW1 is turned on.

Also, the 8PSK f output circuit 34 outputs a signal based on the phase difference given from the phase difference detection circuit 28 as shown in FIG.
A frequency difference is detected from a phase difference with respect to any one of eight synchronous positions (000 to 111) on the constellation plane as shown in FIG. The frequency pull-in range is a range (π / 4) determined by ± π / 8 of the synchronization position, and a frequency difference is detected based on the pull-in range. For example, the phase (θ1) between the point A1 and the nearby synchronous position (000) is detected. Similarly, the phase (θ2) of point A2 corresponding to the next data is detected. Then, a phase difference (θ2-θ1) between the points A1 and A2 is detected, and a frequency corresponding to the detected phase difference (θ2-θ1) is output. 8
The frequency output from the PSK f output circuit 34 is supplied to the LF 40 via the switch SW2. Therefore, the high frequency component of the frequency is removed and is provided to the NCO 36. The NCO 36 generates a control signal (θ2-θ1) for pulling the frequency difference to zero. That is, a parameter corresponding to the frequency shift is generated and given to the ROM 26. Then, the ROM 26 outputs sin data and cos data in the same manner as described above, and the complex multiplying circuit 24 executes arithmetic processing using the data.

Further, based on the phase difference provided from the phase difference detection circuit 28, the BPSK f output circuit 34 provides two synchronous positions (0 or 1) on a constellation plane as shown in FIG. Is detected. That is, the frequency pull-in range is divided into a right region and a left region around the axis of the Q signal, and the frequency difference is detected based on the pull-in range. For example, point A
3 and the phase (θ3) between the neighboring synchronous position (0). Similarly, the phase of point A4 corresponding to the next data (θ
4) is detected. Then, the phase difference (θ4−θ3) between the point A3 and the point A4 is detected, and the detected phase difference (θ4−θ3) is detected.
The frequency corresponding to 3) is output. The frequency output from the BPSK f output circuit 36 is supplied to the LF 40 via the switch SW3. Therefore, the high frequency component of the frequency is removed and is provided to the NCO 36. NCO36
Generates a control signal (θ4-θ3) for pulling the frequency to a nearby synchronous position. That is, a parameter corresponding to the frequency shift is generated and given to the ROM 26. Then, the ROM 26 stores the sin data and the c
The os data is output, and the complex multiplying circuit 24 performs an arithmetic operation using the os data.

Further, the synchronization detecting circuit 30 detects whether or not synchronization is established based on the I 'signal and the Q' signal. That is, when the synchronization word signal is detected, the presence of synchronization is detected, and when the synchronization word signal is not detected, the absence of synchronization is detected. Further, the synchronization detection circuit 30 turns on / off the switches SW2 and SW3 based on whether or not they are synchronized.
Control off. That is, when no synchronization is detected, the switch SW2 is turned on and the switch SW3 is turned off. On the other hand, when synchronization is detected, the switch 2 is turned off and the switch SW3 is turned on. Further, when a predetermined time elapses after detecting the presence of synchronization, the switches SW2 and SW3
Turn off.

For example, in the Costas loop circuit 22, a synchronous word signal is detected in the 8PSK mode. In other words, the frequency is provisionally determined, and the synchronization detection circuit 30 detects the presence of synchronization. Accordingly, an accurate frequency is determined in the BPSK mode. After that, the operation is shifted to the phase control. That is, the locked state is maintained using the LF 32.

More specifically, first, the synchronization detection circuit 3
0 turns on the switch SW2 and turns off the switch SW3. Note that, as described above, the switch SW1 is turned off until it is locked at the correct phase. Synchronous detection circuit 3
When 0 turns on the switch SW2 and turns off the switch SW3, the 8PSK mode is set, and the phase difference from the 8PSK f output circuit 34 based on the constellation plane corresponding to the 8PSK method as shown in FIG. θ2-θ
The frequency corresponding to 1) is output. In this embodiment, since the digital data of the BS digital broadcast is received, the maximum modulatable phase value of the digital data is 8. Therefore, an 8PSK f output circuit 34 is provided to temporarily determine the frequency in the 8PSK mode. As described above, since digital data is detected in the 8PSK mode, it is possible to reliably detect any modulation method. That is, on the constellation plane corresponding to 8PSK, four synchronous positions of QPSK and two synchronous positions of BPSK are included.

As described above, the 8PSK f output circuit 3
Based on the frequency output from 4, the residual carrier component is removed. When the residual carrier component is almost removed,
The synchronization detection circuit 30 detects a synchronization word signal. 8P
In the SK f output circuit 34, there are eight synchronous positions on the constellation plane, so that the SK f output circuit 34 does not always lock at a phase of 0 degrees. For this reason, although not shown, in the synchronization detection circuit 30, m (m is 8 to
The synchronization word signal is detected at (integer of 1) phases.

When the synchronization word signal is detected, the synchronization detection circuit 30 sets the switch SW to determine the correct frequency.
2 is turned off, the switch SW3 is turned on, and the BPSK mode is set. In the BPSK mode, the BPSK f output circuit 36 outputs the BPSK
The operation is performed only during the modulated TMCC signal period to determine the correct frequency. That is, the TMCC signal period is LF4
The time is sufficiently longer than the time constant of 0, so that the frequency difference (residual carrier component) can be reliably removed.
For example, the phase of point A3 shown in FIG.
Assuming that the phase of the point Aj corresponding to the j-th data from the data of the point A3 is θj, the frequency difference can be detected with an accuracy of (θj−θ3) / j, and the accurate frequency difference Δf
3 is detected. Also, assuming that the average of three points A (j-1), Aj and A (j + 1) is the data of Aj,
In other words, when the point corresponding to the data obtained by averaging several data before and after is determined, it is hard to be affected by noise, and a more accurate frequency difference can be detected.

As described above, four symbols are arranged in the burst signal after data of 203 symbols. For this reason,
If the frequency accuracy is poor, errors accumulate in the 203 symbol period, and in the worst case, a phase error of ± π / 2 or more occurs, making it impossible to perform normal phase detection. Therefore, accurate frequency detection is required.

When the correct frequency is determined, that is, when a predetermined time (time corresponding to the TMCC signal period) has elapsed, the synchronization detection circuit 30 turns off the switches SW2 and SW3, and the phase difference detection circuit 28 turns off the switch SW1. Turn on. That is, the process is shifted to the phase control. Therefore, based on the output of the phase difference detection circuit 28, the residual carrier component is removed, and the locked state is maintained. LF32
Is set to have a large time constant in order to reduce the influence of noise.

According to this embodiment, after the frequency is temporarily determined in the 8PSK mode, the accurate frequency is determined in the BPSK mode, so that the frequency can be determined accurately.

In this embodiment, the frequency is provisionally determined in the 8PSK mode in order to reproduce the digital data of the BS digital broadcast. However, the PSK mode of the maximum modulatable phase value (n) of the digital data is used. The frequency may be temporarily determined in (n-valued PSK mode). Here, n is a natural number of 2 or more.

In this embodiment, only the case where the digital Costas loop circuit is applied to a BS digital broadcast receiver has been described. However, other digital broadcast receivers that receive digital data of the type shown in FIG. Can also be applied.

[Brief description of the drawings]

FIG. 1 is an illustrative view showing one embodiment of the present invention;

FIG. 2 is a schematic diagram showing digital data transmitted from a transmission side.

FIG. 3 shows an 8PSK system and a BPS when a frequency is determined by the digital Costas loop circuit shown in FIG. 1 embodiment.
FIG. 4 is an illustrative view showing a constellation plane corresponding to the K system;

FIG. 4 is an illustrative view showing a constellation plane corresponding to an 8PSK method when a frequency is determined by a conventional digital Costas loop circuit;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... BS digital broadcast receiver 16 ... Quadrature detection circuit 20 ... Nyquist filter 22 ... Digital Costas loop circuit 24 ... Complex multiplication circuit 28 ... Phase difference detection circuit 30 ... Synchronization detection circuit 32, 40 ... LF34 ... 8PSK f output circuit 36… f output circuit for BPSK

 ──────────────────────────────────────────────────続 き Continued on front page F term (reference) 5C066 AA03 BA00 CA27 DB06 DC07 DD06 EB11 EG01 GA16 HA02 JA01 KC01 KE16 KE17 KF03 5J106 AA03 BB09 CC21 CC41 DD12 DD36 EE10 GG07 HH10 KK05 5K004 AA05 FA03 FA05 FA06 FG02

Claims (2)

[Claims] 1. A phase difference detecting means for detecting a residual carrier component as a phase difference from I and Q signals including a residual carrier component, a numerical control signal generating means for outputting frequency correlation data corresponding to the phase difference, and the frequency A digital Costas loop circuit comprising multiplier data output means for outputting multiplier data for a complex operation in accordance with correlation data, and performing carrier regeneration using a burst signal, wherein digital data including the burst signal can be modulated. First frequency error generating means for outputting frequency error data in a PSK mode having a maximum phase value n (n is a natural number of 2 or more); second frequency error generating means for outputting frequency error data in a BPSK mode; Synchronization detecting means for detecting the absence of the signal, detecting the absence of the synchronization, the phase difference detecting means and the second frequency First control means for disabling an error generating means and activating the first frequency error generating means; upon detecting the presence of synchronization, disabling the phase difference detecting means and the first frequency error detecting means; Second control means for activating the frequency error detection means, and when a predetermined period elapses after activating the second frequency error detection means, the first frequency error detection means and the second
A digital Costas loop circuit comprising third control means for disabling frequency error detection means and activating the phase difference detection means. 2. A control method in a digital Costas loop circuit for performing carrier regeneration using a burst signal, comprising: (a) a maximum modulatable phase value n (n is 2 or more) of digital data including the burst signal. A control method in a digital Costas loop circuit in which a frequency is temporarily determined in a PSK mode of (natural number), (b) a frequency is determined in a BPSK mode in response to detection of a synchronization pattern, and (c) a transition is made to phase control.