JP2001103486A - Video signal decoder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a video signal decoder, that receives a video stream signal compressed by a prescribed image compression system and decodes the signal with high resolution at a high-speed. SOLUTION: A video signal decoder 1000 includes a decoding processor section 1200 and a motion compensating section 1400. The decoding processor 1200 employs plurality of signal processors 1200.1 to 1200.m to conduct parallel processings. Each of the signal processors 1200.1 to 1200.m includes a decoding discrimination section 1210, that discriminates whether decoding processing is to be applied to each slice at its input stage and a decoding processing section 1220 that conducts the corresponding decode processing. A decode processing output buffer 1300 organizes received decode processing data into one of image data and provides an output of the data to a motion compensation section 1400.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a predetermined code compression method such as MPEG2 (Motion Picture coding).
The present invention relates to a video signal decoding device that decodes a video stream code-compressed by an Expert Group 2) and generates a digital video signal.

[0002]

2. Description of the Related Art Conventionally, an MPEG2 video signal decoding apparatus for decoding an MPEG2 video stream usually calculates difference data and macroblock information for each macroblock from a video stream, and stores these information and a frame buffer in advance. Using the stored decoded image data, a motion compensation process is performed to create a final digital video signal, which is sent to, for example, a display device (display). All of these processes are performed by one processor, or, depending on the processing content, are realized by sequentially processing the processors.

FIG. 11 is a schematic block diagram for explaining a configuration of a conventional video signal decoding apparatus 2000 based on the MPEG2 system.

[0004] The video signal decoding device 2000 uses MPEG.
A decoding processing unit 2010 for receiving the two video streams and performing a decoding process, and a motion compensation processing unit 2020 for receiving the output of the decoding processing unit 2010 and performing motion compensation and outputting a digital video signal. Prepare.

[0005] Here, the decryption processing unit 2010 uses MPEG
A variable-length code decoding unit 2100 for receiving the two video streams and performing variable-length code decoding; an inverse quantization unit 2200 for receiving the output of the variable-length code decoding unit 2100 and performing an inverse quantization process; An inverse discrete cosine transform unit 2300 for receiving the output of the inverse quantization unit 2200 and performing an inverse discrete cosine transform.

Further, a motion compensation processing unit 1020 performs a motion compensation process using the output from the inverse discrete cosine transform unit 2300 and the image data created before, and a motion compensation unit 2400 for outputting a digital video signal. And a frame buffer 2500 for storing and holding this digital video signal in frame units.

That is, the video signal decoding device 2000
Receives an MPEG2 video stream as an input signal, and finally converts and outputs the digital video signal.
An MPEG2 video stream as an input signal is a digital data input from a storage medium such as a video disk or a hard disk device, or a digital broadcast signal input from a broadcast medium such as a satellite digital broadcast or a digital cable television. is there.

The output digital video signal is D / A-converted and output to an analog television screen or RGB-converted and output to a monitor of a personal computer depending on the application.

In some cases, the input signal is multiplexed with an audio stream, a multi-channel video stream, or the like, and is input. In this case, a stream to be demultiplexed and subjected to decoding processing is extracted in advance. There is a need to.

The input video stream is 16 × 1
In a unit called a macroblock of 6 pixels, variable-length code decoding, inverse quantization, inverse discrete cosine transform, motion compensation, and the like are performed, and the final image data is output as a digital video signal.

At this time, the processes from variable-length code decoding to inverse discrete cosine transform are performed as closed processes in units of macroblocks, but with respect to motion compensation, decoded images stored in the frame buffer 2500 in advance are used. It is performed in frame units using data.

[0012]

The MPE as described above
In an application that decodes a G2 video stream, it is general that both the decoding processing unit 2010 and the motion compensation unit 2020 are collectively processed by one processor. There is a type of video that can be decoded by a one-chip processor as long as the video can be reproduced on a home television.

However, in recent years, for example, in a video apparatus for business use, encoding / decoding of a video signal with higher resolution has been demanded in terms of time and space, and a single processor cannot keep up with the processing time. The case is coming.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and its object is to solve the problem in time,
An object of the present invention is to provide a video signal decoding device capable of decoding a spatially higher resolution video signal at a high signal rate.

[0015]

In order to achieve the above object, according to the present invention, the entire code processing apparatus is divided into a decoding processing section and a motion compensation section, and the decoding processing section is composed of a plurality of processors. Then, a means for detecting a slice header at the preceding stage of each processor and determining whether or not to perform decoding based on the information is provided.

That is, a video signal decoding apparatus according to claim 1 is a video signal decoding apparatus for receiving a video stream signal and converting it into a digital video signal.
A decoding unit that performs a division process corresponding to spatially dividing the image on a video stream signal that corresponds to an image formed by a digital video signal and that is sequentially input; Includes a plurality of decoding processors for respectively receiving the corresponding divided video stream signals among the divided video stream signals obtained by dividing the divided video stream signals and performing decoding processing in parallel, receiving an output from the decoding unit, and outputting a video stream corresponding to an image. The apparatus further includes a motion compensation unit for performing a motion compensation process on the signal.

According to a second aspect of the present invention, in addition to the configuration of the video signal decoding apparatus according to the first aspect, the video stream signal includes a plurality of divided images obtained by dividing an image along a predetermined direction. Are respectively divided into a plurality of slice signals included in any one of the divided images, the slice signal includes a slice header indicating which of the divided images is included, and each of the plurality of decoding processors includes A decoding determination unit that determines, for each slice signal, whether or not to perform the decoding process according to the header; and a decoding unit that performs the decoding process on the slice signal detected by the decoding determination unit to perform the decoding process. Including.

According to a third aspect of the present invention, in addition to the configuration of the video signal decoding apparatus of the second aspect, the image is divided into first to m-th divided images (m: When the decoding unit is divided into (natural numbers), the decoding unit includes m decoding processors, and the decoding determination unit of the i-th (i: natural number, 1 ≦ i ≦ m) decoding processor determines the i-th decoding processor. The decoding process of the slice signal included in the divided image is permitted.

According to a fourth aspect of the present invention, in addition to the configuration of the video signal decoding apparatus of the second aspect, the decoding unit includes m decoding processors, and the i-th (i: The decoding determination unit of the decoding processor (natural number, 1 ≦ i ≦ m) permits the decoding processing of the slice signal in which the remainder with respect to m in the input order is i among the sequentially input slice signals.

According to a fifth aspect of the present invention, in addition to the configuration of the video signal decoding apparatus of the second aspect, the video signal decoding apparatus receives and stores outputs from a plurality of decoding processors, and converts the output into a decoded signal corresponding to an image. It further includes a decoding processing output buffer that outputs the integrated processing to the motion compensation unit.

According to a sixth aspect of the present invention, in addition to the configuration of the video signal decoding apparatus according to the fifth aspect, a plurality of decoding processors output to a decoding output buffer sequentially with a delay of one clock. The decoding processing output buffer has m banks when the number of decoding processors included in the decoding unit is m, and outputs from a plurality of decoding processors. A buffer memory for storing data corresponding to pixels adjacent in a predetermined direction of an image from a plurality of banks designated by one address when reading stored data. Are read from the plurality of decoding processors.

According to a seventh aspect of the present invention, in addition to the configuration of the video signal decoding apparatus according to the second aspect, each of the plurality of decoding processors includes a differential data and a motion compensator from a corresponding slice signal. Separates the absolute address of the reference position of the image referred to by the motion compensation unit, receives the difference data from the decoding processor, and performs a motion compensation process for performing a motion compensation process, and the reference image data after the motion compensation. Store and according to the absolute address of the reference position,
Image memory for providing corresponding data to the motion compensation processor.

According to a video signal decoding apparatus of the present invention, in addition to the configuration of the video signal decoding apparatus of the present invention, an absolute address is calculated for each line constituting an image and is provided to a motion compensating unit. A reference address calculation unit is further provided.

According to a ninth aspect of the present invention, in addition to the structure of the video signal decoding apparatus of the seventh aspect, the image memory sequentially stores a plurality of motion-compensated reference image data corresponding to a plurality of images. And a reference address calculation unit for storing, as an absolute address, data indicating the reference image data and data indicating a position in the reference image data to the motion compensation unit.

A video signal decoding apparatus according to claim 10 is
In addition to the configuration of the video signal decoding device according to claim 7, for each macroblock in the corresponding slice signal, data for specifying an image to be referred to by the motion compensation unit is provided to the motion compensation unit as command data. A command calculation unit is further provided.

The video signal decoding apparatus according to claim 11 is
In addition to the configuration of the video signal decoding device according to the tenth aspect, the command includes data indicating the presence / absence of horizontal and vertical half-cells.

A video signal decoding apparatus according to claim 12 is
In addition to the configuration of the video signal decoding device according to the seventh aspect, the image memory sequentially stores a plurality of pieces of motion-compensated reference image data corresponding to the plurality of images, and uses any one of the reference image data as an absolute address. A reference address calculation unit that gives data indicating whether the motion compensation unit and the data indicating the position in the reference image data to the motion compensation unit, and an image referred to by the motion compensation unit for each macroblock in the corresponding slice signal. And a command calculating unit that gives the data of the above as command data to the motion compensating unit.
Includes data indicating the presence or absence of each of the forward and backward references.

A video signal decoding apparatus according to claim 13 is
In addition to the configuration of the video signal decoding device according to claim 12,
The command includes data indicating one of the field prediction and the frame prediction.

A video signal decoding apparatus according to claim 14 is
In addition to the configuration of the video signal decoding device according to any one of claims 1 to 13, the video stream signal is an MPEG signal.
2 video stream signal.

[0030]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [Configuration of Video Signal Decoding Apparatus 1000] FIG. 1 is a schematic block diagram showing a configuration of a video signal decoding apparatus 1000 compatible with the MPEG2 system of the present invention.

In the following, the structure of a video signal decoding device when code compression according to the MPEG2 system is performed as the compression coding of a video signal will be described as an example.

However, as will be apparent from the following description, the present invention is not necessarily limited to such a case. Like MPEG2, a spatially dividable video stream structure described later is used. The present invention can be generally used for a decoding device for a video signal that has been compression-encoded by an image compression method.

The video signal decoding apparatus 1000 uses the MPEG
An input unit 1100 for receiving two video streams;
A decoding processor unit 1200 for dividing an output from the input unit 1100 into m (m: natural number) parallel stream data and performing decoding processing in parallel;
A decoding output buffer 1300 for receiving the output from the buffer 200 and performing a buffering process, and a motion compensating unit 1400 for receiving the output of the decoding processing output buffer 1300 and performing a motion compensation process to output a digital video signal.
And

Here, the input buffer unit 1100 receives the serially supplied MPEG2 video stream, performs buffer processing on each of them, and outputs the buffered output. m.

The decoding processor unit 1200 includes input buffers 1100.1 to 1100. m for receiving buffered MPEG2 video streams respectively output from m and selectively decoding macroblock data corresponding to each of the video streams in the video stream. 1-120
0. m.

Decryption processors 1200.1-120
0. m each have a corresponding input buffer 1100.1-
1100. m, a decoding determination unit 1210 for detecting whether or not the video stream data given from one of the m.
And a decoding processing unit 1220 for receiving the output of the decoding determination unit 1210 and performing decoding processing.

Each of the decryption processors 1200.1-12
00. The decoded data output in parallel from m is received by the decoding output buffer 1300, combined into one picture data, and supplied to the motion compensation processor 1410 in the motion compensation unit 1400.

The motion compensation processor 1410 sequentially stores the decoded data for each frame in the frame buffer 1420, and then stores the data in the frame buffer 1420.
A digital video signal is generated and output by performing a motion compensation process on data that is decoded based on the data stored therein and provided from a decoding process output buffer 1300.

That is, as described above, the decoding process is performed in parallel by a plurality of processors, and thereafter, motion compensation is performed to generate a digital video signal.

[Operation of Video Signal Decoding Device 1000] The operation of the video signal decoding device 1000 shown in FIG. 1 will be described in more detail.

In order to perform parallel processing in the decoding processor 1200, as described above, the decoding processing unit 121 which performs decoding processing such as variable length decoding and inverse quantization.
A decoding determination unit 1210 that determines whether or not to perform a decoding process is provided at a stage preceding 0.

The MPEG2 video stream is simultaneously input to an input buffer provided in the preceding stage of each decoding processor.

That is, at this stage, no division has been performed, and all the decoding processors 1200.1 to 120.1
00. The same stream is input to m at the same time.

In the following, first, the structure of an MPEG2 video stream will be described as a premise for describing such a video stream division operation. FIG.
FIG. 3 is a conceptual diagram illustrating a structure of a G2 video stream.

The MPEG2 decoding process is performed in units of macroblocks of 16 × 16 pixels. That is, for example, image data of 640 pixels in width and 480 pixels in height is
It is divided into 0 macroblocks and 30 vertical macroblocks, and processing is performed in order from the leftmost macroblock. When decoding of the lower right macroblock ends, image data for one screen is completed.

Referring to FIG. 2, an MPEG2 video stream is an aggregate of GOPs (Groups of Pictures), and the GOPs are aggregates of pictures.

A picture is data of one image.
In the above example, it is an aggregate of 40 × 30 macro blocks.

A picture is further divided into units called slices. A slice is a collection of several macroblocks. According to the MPEG2 standard,
One slice does not always cross the line. In other words, when one horizontal row is composed of 40 macroblocks, it is possible to divide this 40 rows into any number of slices. No.

Although each macroblock does not have absolute position information, the slice header SH inserted at the beginning of each slice contains the individual slice at any vertical position on one screen. Header information for indicating whether the block is a set of macro blocks is included.

In other words, by looking at the slice header SH, it is possible to know the vertical position of the macroblock that follows, so that this slice header can be a means to know the position information for spatially dividing one screen. Will be.

Therefore, in the video signal decoding apparatus 1000, as described above, the decoding of MPEG2 is first separated into the decoding processor 1200 and the motion compensator 1400, and the decoding processor 1200 is further divided into a plurality of processors 1200.1 to 1200. 1200. Execute in parallel with m.

The parallelization of the decoding processing unit is realized by spatially dividing the image data of one screen and assigning different decoding processors to each of the divided image areas.

Referring again to FIG. 1, the stream is shown in FIG.
Are input to the video signal decoding apparatus 1000 according to the structure of
00. Each of m first detects a sequence header, and then detects a picture header and a slice header SH in this order.

When the slice header SH is detected, each of the decoding processors determines whether or not to perform the decoding process on the slice. If the processing is not to be performed, the decoding processor inputs the data until the next slice header SH is found. You will ignore the data in the buffer.

The specific procedure for determining whether or not to perform the decoding process is described in the following section.
There are different ways.

First, in order to spatially divide this image, the first horizontal row, that is, 40 macroblocks are decoded by the first processor, and the next horizontal horizontal row, 40 macroblocks, are decoded. A scheme in which the next processor decodes the macroblock may be considered.

FIG. 3 is a flowchart for explaining a method for determining whether or not to perform decoding processing using the vertical position information included in the slice header.

For example, assuming that parallel processing is performed by four decoding processors, the first processor 1
200.1 is 4 where the slice position information is 1, 5, 9, etc.
The macroblock of the part where the remainder obtained by dividing by 1 becomes 1 is processed, and the rest is ignored.

Similarly, the second processor 1200.2
The third processor 1200.3 decodes the portion where the remainder divided by 4 is 2 and the third processor 1200.3 decodes the portion where the remainder divided by 4 is 4. If the determination is made in the procedure of decoding the part where the remainder obtained by dividing by 0 becomes 0, one picture can be processed in parallel by a plurality of processors.

In the following, it is assumed that decoding determination section 1210 includes a memory (not shown) for temporarily storing a stream in order to make such a determination.

Referring to FIG. 3, first, decoding determination section 121
0 reads the stream into the memory (step S10
0), and a slice header is detected (step S10).
2).

Subsequently, the decoding judgment unit 1210 calculates the slice vertical position S from the slice header (step S1).
04), the remainder value n when the slice vertical position S is divided by m (for example, 4) is calculated (step S10).
6).

For example, the decoding determination unit 1210 determines that the n-th decoding processor 1200. If it is included in n, it is determined whether or not the surplus value obtained by dividing the slice vertical position S calculated as described above by m matches the value of n (step S106), and does not match. In this case, the process returns to step S102.

On the other hand, if the remainder obtained by dividing the slice vertical position S by m is equal to n (step S106), the sign determination unit 1210 sends the corresponding decoding processing unit 1220
The slice data is output, and the decoding processing is performed in the decoding processing unit 1220 (step S108), and the process returns to step S102.

As a second method, it is conceivable to allocate a processor for each slice. FIG. 4 is a flowchart showing a method of allocating a processor for each slice as described above.

In the case of this method, each time a slice header is detected, a different processor performs a decoding process. How to determine the unit of the slice is left to the encoding apparatus, but, for example, the encoding apparatus uses slices such that one slice contains approximately the same amount of information. When the unit is dynamically determined, this method allows each processor to perform decoding processing in parallel with a uniform amount of work in the decoding device.

That is, depending on the picture part, it is common that an area where image data exists densely and an area where image data exists sparsely exist together.

Therefore, the coding processing apparatus sets the number of macroblocks included in a slice to be large in a region where the image data is sparse, and conversely, in a region where the image data is dense. It is also possible to set so that the number of macroblocks included in a slice is reduced. In this case, as described above, for each slice,
About the same amount of information will be included.

Referring to FIG. 4, first, when a video stream is read into the memory of decoding determining section 1210 (step S200), decoding determining section 1210 determines the order of slices in the input video stream. The value of the variable S for indicating is initialized to 1 (step S20).
2).

Subsequently, decoding determination section 1210 detects a slice header and determines whether the slice header is slice data to be decoded (step S20).
4).

That is, the decoding determination unit 1210 determines that the n-th decoding processor 1200. n
It is determined whether or not the value of the variable S is equal to n (Step S206). If the value of the variable S is equal to the value of n (Step S206), the decoding determination unit 1210 determines whether the corresponding decoding processing unit Slice data is output to 1220, and decoding processing is performed in decoding processing section 1220 (step S208). Subsequently, the value of the variable S is incremented by 1 (step S210).

On the other hand, in step S206, the variable S
Is not equal to the value of n, the process proceeds to step S210 without performing the decoding process.

Subsequently, it is determined whether or not the value of the variable S is greater than the number m (for example, 4) of decoding processors (step S212). If the value of the variable S is not larger than the value of m, the process returns to step S2
Return to 04.

On the other hand, if the value of the variable S is larger than the value of m (step S212), the value of the variable S is initialized to 1 again (step S214), and the process proceeds to step S20.
Return to 4.

The data of each slice processed in parallel in the decoding processing as described above is once combined into one picture in the decoding processing output buffer 1300 and transferred to the motion compensation processing unit 1400.

In the motion compensation processing section 1400, the picture data thus decoded is stored in the frame buffer, and a final digital video signal is generated by referring to the picture data stored in the frame buffer 1420. . At this time, based on the motion vector information given for each macroblock, the data of each macroblock is subjected to a motion compensation process by referring to data in a range of 16 × 16 pixels at an arbitrary position of the picture data to be referenced. Do.

In the decoding processing unit, picture data can be spatially divided and processed in parallel. However, in the motion compensation unit 1400, each macroblock needs to refer to an arbitrary location of reference image data. For this reason, it is difficult to perform parallel processing.

Therefore, as shown in FIG. 1, each slice data processed in parallel before performing motion compensation is
It is necessary to put together the picture data.

[Data Processing in Decoding Process Output Buffer 1300] FIG. 5 shows the data decoded in parallel in this way via the decoding process output buffer 1300.
FIG. 39 is a timing chart for describing a data flow from a decoding processing output buffer 1300 when outputting as one piece of picture data.

In the example shown in FIG. 5, the four decoding processors 120
0.1 to 1200.4 perform processing in parallel, and each of the decoding processors 1200.1 to 1200.4 outputs data for one pixel in one time unit (hereinafter referred to as a clock). And

Assuming that the pixel data output from one processor during one clock is 8 bits, when the four data are put together, data of 32 times the width of 4 times is output, or the data of 8 bits width is output. Data may be output at four times faster clock intervals.

In the example shown in FIG. 5, a timing chart in the case of outputting data in the former of 32 bits width is shown.

As shown in FIG. 5, when outputting four pieces of pixel data collectively, when outputting each piece of pixel data collectively into 32 bits per clock, an 8-bit data having the following properties is used. Consider using a buffer memory of width in decoding output buffer 1300.

That is, this buffer memory is designed to read and write 8-bit data by designating the bank and address of data to be written in one clock period and the bank and address of data to be read. .

For each of writing and reading, an arbitrary address of each bank can be specified at the same time, but data cannot be simultaneously written or read to a plurality of addresses of the same bank.

Using such a buffer memory, FIG.
In order to realize input and output like
Only one buffer memory having two addresses is required.

First, pixel data A1-D1 output from each processor in the first clock period are written into addresses 0 of four banks.

In the next cycle, while reading the address 0 of each bank, the next pixel data A2-D2 is simultaneously written to the address 1 of each bank.

In the next cycle, address 0 is overwritten with pixel data A3-D3 while address 1 is read. In this way, by reading and writing while alternately designating two addresses of the four banks, data input / output as shown in the timing chart of FIG. 5 can be realized in the decoding output buffer 1300. is there.

However, actually, the pixel data Ai to Di (i: natural numbers) output from the decoding processors 1200.1 to 1200.4 are pixel data of different slices and are not adjacent data. . The data is transferred to the frame buffer
When writing data in units of 2 bits, four 8-bit data consecutive in terms of address, for example, specifically A1-A4
Are written at the same time, the efficiency of the motion compensation processing and the like is higher.

Therefore, the decoding process output buffer 130
As shown in FIG. 6, the outputs from 0 are A1-A4, B1
Output in the order of -B4 is more convenient when data stored in the frame buffer is later processed by a motion compensation processor or the like.

When data is output in such an order,
If a buffer memory having the same properties as in FIG. 5 is used, a buffer memory having 16 banks and two addresses is required as shown in FIG.

That is, unless the data from A4 to D4 is output from each processor at the fourth clock counting from the beginning, the decoding processing output buffer outputs A
Since the data of 1-A4 cannot be output, A1-D1 to A4-D
It is necessary to store data for 16 pixels up to 4 in different banks. In order to perform reading and writing using two addresses alternately as in the case of FIG. 5, two addresses are stored in each bank. Is required.

Generally, a memory has several banks and many addresses, and there is no memory having such many banks. That is, if a memory configuration having a large number of banks as shown in FIG. 6 is to be realized, a plurality of buffer memories must be actually used, and hardware restrictions are strict. Also, in the case of FIG. 5, all banks should always be read and written to the same address in each cycle, but in the case of FIG. 6, different banks must be accessed for each clock, which complicates the procedure.

FIG. 7 shows a buffer memory having a smaller number of banks for solving such a problem, and a buffer memory for enabling the operation of the decoding output buffer 1300 as described in FIG. FIG. 3 is a conceptual diagram showing the configuration of an address and its operation.

That is, the output from each decoding processor is shifted by one clock, and the pixel data to be read out is written to the same address in a different bank at the same clock.

More specifically, data A1 is stored at address 0 of bank 0 at the first clock, data A2 is stored at address 0 of bank 1 at the next clock, and data A2 is stored at address 1 of bank 0 at the next clock.
Write 1

When this procedure is continued, similar to the case of FIG.
Data A1 to A4 can be extracted at the fourth clock after the first data A1 is input. 4 addresses
Instead of doubling, the number of banks is reduced to 1/4, and the hardware configuration can be simplified.

Further, when reading, the same address is always accessed, and the procedure is simplified as compared with the case of FIG.

FIG. 8 is a schematic block diagram showing the configuration of a circuit for supplying a synchronization signal from the decoding processors 1200.1 to 1200.4 as shown in FIG. 7 to the decoding processor for realizing the pixel data output timing. FIG.

That is, the synchronization signal delay circuit 1500
Receiving the synchronization signal from synchronization signal generation circuit 1510 and the output from clock signal generation circuit 1520 for generating the clock signal for designating the clock operation shown in FIG. .4
To supply an operation clock.

Decoding processor 1200.1-120
0.4 corresponds to the decoding process output buffer 1300 in accordance with the synchronization clock from the synchronization signal delay circuit 1500.
Output the decrypted data.

The output of pixel data from each processor is:
In this manner, since the synchronization is performed in synchronization with the synchronization signal from synchronization signal delay circuit 1500, synchronization signal delay circuit 15
In 00, the synchronization signal may be delayed by one clock and supplied to each of the processors 1200.1 to 1200.4.

This is generally because the decoding processor is m
If there are any of them, the m synchronization signals are similarly delayed by one clock, and
What is necessary is just to supply to 20.1 to 1200 m.

[Operation of Motion Compensation Processing Unit 1400] The picture data combined into one picture in the decoding output buffer is subjected to motion compensation processing in the motion compensation unit 1400 to become a final digital video signal.

At the time of the motion compensation processing, a 16 × 16 pixel range to be referred to is extracted from the reference picture in the frame buffer 1420 based on the motion vector given for each macroblock as described above. Then, a difference from pixel data (hereinafter, referred to as difference data) obtained as a result of the decoding processing by the decoding processor is calculated to generate final image data.

The motion vector is the relative position in the horizontal and vertical directions from the position of the macroblock currently being decoded. To calculate the relative position of the range to be referred from the motion vector, , The absolute position of the reference block is also required.

The prediction types include frame prediction, field prediction, and dual-prime prediction. Since there are forward and backward predictions, each macro block has up to four motion vectors. Become.

In order for the motion compensator 1400 to output a digital video signal, macroblock information MBI such as the above-described prediction type, block position, and motion vector is required in addition to the difference data.

Further, from the relationship of referring to a plurality of images,
The frame buffer 1420 usually stores a plurality of pictures for each bank. For this reason, when calculating the reference address RAD, information as to which bank in the frame buffer 1420 the reference image is stored is also required.

Normally, the motion compensation unit 1400 calculates the absolute position of the image to be referred to for each difference data.

However, since the macro block information MBI is independent information for each macro block, when one image is spatially divided and processed in parallel as in the present invention, these calculations are also performed. If the calculation is performed by the decoding processor unit 1200, the efficiency can be improved because the parallel processing can be performed.

If the decoding processor 1200 calculates the absolute address of the reference image, the motion compensator mechanically converts the digital video signal based on the reference address RAD and the difference data without performing complicated calculations. It becomes possible to output.

FIG. 9 is a schematic block diagram for explaining a configuration for calculating the absolute address (reference address RAD) of the reference image based on the data extracted by the decoding processor 1200 as described above.

Referring to FIG. 9, decoding processor unit 120
0 has m decoding processors, and MPEG2
Upon receiving the video stream, the decoding process is performed in parallel.
The command calculation circuit 1240 provides the motion compensation processor 1410 with common information such as a prediction type corresponding to the macroblock being decoded, which is output from each of the m decoding processors, as a command for each macroblock. The reference address calculation circuit 1250 calculates a reference address RAD to be referred to in the motion compensation processing for each line of the macro block and supplies the calculated reference address RAD to the frame buffer 1420 in parallel with the operation of the command calculation circuit 1240.

That is, in the frame buffer 1420, based on the reference address given from the reference address calculation circuit 1250, reference image data corresponding to the reference address RAD is given from any of the banks to the motion compensation processor 1410.

That is, when the decoding processor of the decoding processor 1200 decodes the video stream for each macroblock, difference data and macroblock information are obtained. Therefore, the difference data is directly passed through the decoding processing output buffer 1300. Motion compensation processor 141
0, and for the macroblock information, the command calculation circuit 1240 and the reference address calculation unit 1250 calculate the command and the reference address based on the macroblock information, and send them to the motion compensation processor 1410 and the frame buffer 1420, respectively. Output.

For example, in MPEG2, an I-picture I1 to be intra-coded is decoded, and subsequently, a P-picture P1 coded by forward prediction is decoded. The decoding process of the predicted B pictures B1, B2, B3 is performed. The data values of I picture I1 and P picture P1 are stored in frame buffer 1420. In addition, B of bidirectional prediction
The data values of pictures B1, B2, B3 need not be stored in frame buffer 1420.

As a result of these processes, the I video I1, the B pictures B1, B2, B
3, P pictures are output in the order of P1.

In the decoding process of the P picture P1, the I picture I1 which has been decoded as the preceding stage is already stored in the frame buffer 1420.
Motion compensation is performed based on the reference image data in the picture I1.

In the decoding process of each of the B pictures B1 to B3, the decoding process has already been performed and the frame buffer 14
The reference image data in the I picture I1 and the P picture P1 stored in the
0 will be read and provided to the motion compensation processor 1410.

Of the macroblock information, the one that can be calculated from the motion vector and the block position is the absolute position of the upper left pixel of the area to be referred to by the macroblock.

In the case of frame prediction, only one position is calculated, and the remaining pixels are calculated based on their relative positions. In the case of field prediction, the absolute position of the upper left is different between the odd field and the even field, and the remaining pixels are calculated based on the relative position of each field from the upper left.

Therefore, the reference address calculation circuit 1250 may arbitrarily calculate only the reference address of the upper left pixel based on the data from the decoding processing unit 1210 and output it to the motion compensation unit. Since the reference addresses of the pixels are different between the frame prediction and the field prediction, it is better to output the reference addresses of the other pixels as well.
Burden is reduced.

At this time, the reference addresses of all the pixels may be transmitted. However, since it is known that the reference addresses of each line are continuous, it is most efficient to transmit the reference addresses for each line. It is a target. The reference address from which the macroblock information can be calculated is an absolute address starting from the upper left of the reference image. However, information indicating where the reference image is stored in the frame buffer 1420, for example, the bank and the information in the bank It is more efficient to calculate including the information of the position and output the absolute address in the frame buffer.

As described above, the motion compensator 1400 receives the difference data and the reference address and calculates the digital signal using the reference image in the frame buffer, but complete motion compensation is performed only with the difference data and the reference address RAD. Can not. This is because the spatial resolution of the relative position indicated by the motion vector is 1/2 pixel, and it is not possible to indicate a reference address with that resolution.

Further, not all pixels are the difference from the reference image, and there are macroblocks that make reference only in the forward direction and macroblocks that make no reference at all.

Further, when the reference destination is shifted by 1/2 pixel (hereinafter, this case is referred to as a case where there is a half pel), when the reference destination is a vertical half pel, the motion compensation unit
In the case of frame prediction, the average of the pixel value of the pixel at the position indicated by the reference address and the pixel immediately below it is calculated. The output value needs to be obtained from the data and the value.

Therefore, even when a reference address is transmitted for each line, whether there is a forward or backward reference, whether there is a horizontal or vertical half-pel at each reference address, whether frame prediction or field prediction is performed. Such information is needed.

The motion compensation unit 1400 calculates
The digital video signal can be transmitted only after receiving the reference address and the differential data value.

As shown in the configuration of FIG. 9, in the present invention,
Such information is calculated as a command CMD separately from the reference address and sent to the motion compensation unit 1400.

FIG. 10 is a conceptual diagram showing the configuration of a command including such information. Referring to FIG.
In the command consisting of bit data, data indicating which of frame prediction and field prediction is stored in the 0th bit, data indicating presence / absence of backward reference is stored in the second bit, and The bits include data indicating the presence or absence of forward reference.

Hereinafter, from the third bit to the tenth bit, the third bit is a backward reference, and data indicating the presence or absence of a vertical half pel for an even field, and the fourth bit is a forward prediction. And whether or not there is a vertical half pel in the even field, whether the fifth bit is backward prediction and whether or not there is a vertical half pel in the odd field, and whether the sixth bit is forward prediction and Contains data indicating whether the field has a vertical half pel.

Further, the seventh bit is backward prediction, and data indicating whether or not there is a horizontal half-pel in an even field. The eighth bit is forward prediction.
Whether the even field has a horizontal half-pel, the ninth bit is for backward prediction, and whether the odd field has a horizontal half-pel, the tenth bit is for forward prediction, and Contains data indicating whether or not there is a horizontal half pel.

Such command data may be configured such that a command is transmitted for each line together with a reference address. However, since the information included in the command CMD is invariable information in a macro block, It may be configured to transmit once for each block.

The embodiments disclosed this time are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[0137]

As described above, the use of the video signal decoding apparatus of the present invention makes it possible to perform parallel processing by a plurality of processors in decoding a video signal by an image compression coding method such as MPEG2. In addition, it is possible to perform higher-speed and higher-resolution decoding processing using hardware with limited performance.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram illustrating a configuration of an MPEG2 video signal decoding device 1000 according to the present invention.

FIG. 2 is a diagram showing a structure of an MPEG2 video stream.

FIG. 3 is a flowchart showing a first decoding determination process according to the present invention.

FIG. 4 is a flowchart showing a second decoding determination process according to the present invention.

FIG. 5 is a diagram showing an input / output time chart of a decoding process output buffer and a first memory configuration for realizing the time chart;

FIG. 6 is a diagram showing an input / output time chart of a decoding process output buffer and a second memory configuration for realizing it.

FIG. 7 is a diagram showing another input / output time chart of a decoding process output buffer and a third memory configuration for realizing the same;

FIG. 8 is a schematic block diagram showing a configuration of a decoding process delay process.

FIG. 9 is a schematic block diagram illustrating a configuration of a device that calculates difference data, a command, and a reference address.

FIG. 10 is a diagram illustrating a configuration example of a command.

FIG. 11 shows a conventional MPEG2 video signal decoding device 20.
It is a schematic block diagram which shows the structure of 00.

[Explanation of symbols]

1100 input unit, 1100.1 to 1100. m input buffer, 1200 decoding processor unit, 1200.1 ~
1200. m decoding processor, 1240 command calculation circuit, 1250 reference address calculation circuit, 130
0 decoding processing output buffer, 1400 motion compensator, 1
410 Motion compensation processor, 1420 frame buffer, 1500 synchronization signal delay circuit, 1510 synchronization signal generation circuit, 1520 clock signal generation circuit.

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Hiroki Taniguchi 2-5-5 Keihanhondori, Moriguchi-shi, Osaka F-term (reference) in Sanyo Electric Co., Ltd. 5C059 KK13 MA05 MA23 ME01 NN01 NN21 PP04 RA01 RA04 RB01 RC02 RC12 RC32 SS02 SS03 UA05 UA31

Claims (14)

[Claims] 1. A video signal decoding device for receiving a video stream signal and converting the video stream signal into a digital video signal, wherein the video stream corresponds to an image constituted by the digital video signal and is sequentially input The signal, further comprising a decoding unit that performs a dividing process corresponding to spatially dividing the image, the decoding unit, among the divided video stream signals obtained by dividing the video stream signal, the corresponding divided video stream signal A plurality of decoding processors for respectively receiving and decoding in parallel, receiving a output from the decoding unit, and a motion compensation unit for performing a motion compensation process on a video stream signal corresponding to the image; A video signal decoding device further provided. 2. The video stream signal is divided into a plurality of slice signals respectively included in any one of a plurality of divided images obtained by dividing the image along a predetermined direction. Includes a slice header indicating which of the divided images is included, and each of the plurality of decoding processors determines, for each of the slice signals, whether to perform a decoding process according to the slice header. The video signal decoding device according to claim 1, further comprising: a decoding determination unit configured to determine; and a decoding unit configured to perform a decoding process on the slice signal detected to perform the decoding process by the decoding determination unit. 3. When the image is divided into first to m-th divided images (m: natural number) along a predetermined direction, the decoding unit includes m decoding processors, 3. The decoding determination unit of the i-th (i: natural number, 1 ≦ i ≦ m) decoding processing processor according to claim 2, wherein the decoding determination unit permits decoding processing of the slice signal included in the i-th divided image. 4. Video signal decoding device. 4. The decoding unit included in the decoding unit includes m decoding processors, and the decoding determination unit of the i-th (i: natural number, 1 ≦ i ≦ m) decoding processor is sequentially input. The remainder of the slice signals with respect to m in the input order is i
3. The video signal decoding device according to claim 2, wherein a decoding process of the slice signal is performed. 5. The image processing apparatus according to claim 1, further comprising a decoding processing output buffer that receives and stores outputs from the plurality of decoding processors, integrates the decoded signals into the decoded signals corresponding to the images, and outputs the integrated signals to the motion compensation unit. 3. The video signal decoding device according to 2. 6. The decoding processing output buffer further comprises: a timing control circuit for providing an output from the plurality of decoding processing processors to the decoding processing output buffer with a delay of one clock at a time. When the number of decoding processors to be included is m, a buffer memory having m banks for storing outputs from the plurality of decoding processors is included, and the buffer memory includes stored data. At the time of reading, outputs from the plurality of decoding processors are read so that data corresponding to pixels adjacent to the image in the predetermined direction is read from a plurality of banks designated by one address. The video signal decoding device according to claim 5, wherein the video signal is stored. 7. Each of the plurality of decoding processors separates, from a corresponding slice signal, difference data and an absolute address of a reference position of an image referred to by the motion compensation unit, and the motion compensation unit A motion compensation processor for receiving the difference data from the processing processor and performing a motion compensation process, storing the reference image data after the motion compensation, and converting the corresponding data to the motion according to the absolute address of the reference position. 3. The video signal decoding device according to claim 2, further comprising: an image memory provided to a compensation processor. 8. The video signal decoding apparatus according to claim 7, further comprising: a reference address calculating unit that calculates the absolute address for each line constituting the image and supplies the calculated absolute address to the motion compensation unit. 9. The image memory sequentially stores a plurality of motion-compensated reference image data corresponding to a plurality of the images, and stores, as the absolute address, data indicating which reference image data is the reference image data and the reference data. The video signal decoding device according to claim 7, further comprising a reference address calculation unit that supplies data indicating a position in image data to the motion compensation unit. 10. A command calculation unit for providing data for specifying a picture referred to by the motion compensation unit as command data to the motion compensation unit for each macroblock in a corresponding slice signal. Item 7
The video signal decoding device according to claim 1. 11. The video signal decoding apparatus according to claim 10, wherein said command includes data indicating the presence or absence of a horizontal and vertical half-level. 12. The image memory sequentially stores a plurality of pieces of motion-compensated reference image data corresponding to a plurality of the images, and stores, as the absolute address, data indicating which reference image data is the reference image data and the reference data. A reference address calculator for providing data indicating a position in image data to the motion compensator; and for each macroblock in the corresponding slice signal,
A command calculating unit that gives data for specifying an image referred to by the motion compensation unit as command data to the motion compensation unit, wherein the command indicates whether or not there is a reference in each of a forward direction and a backward direction. 8. The video signal decoding device according to claim 7, including data. 13. The video signal decoding device according to claim 12, wherein said command includes data indicating one of field prediction and frame prediction. 14. The video stream signal has an MPE
The video signal decoding device according to claim 1, wherein the video signal decoding device is a G2 video stream signal.