JP2001103472A - Method and device for executing fixed point for mpeg-4 inverse dc/ac prediction - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an exclusive hardware unit for round-off that employs a variable bit length pseudo-reciprocal and shift, depending on a value of a devisor as to a method and a device that apply inverse DC/AC prediction for MPEG-4 video decoding without a round-off errors and without using division by employing fixed point execution in a minimum bit lookup table and a minimum bit length multiplier. SOLUTION: This method and device exclude a round-off arithmetic operation, by using simple integration and accumulation and proposes an execution algorithm for MPEG-4 inverse DC/AC prediction, where inverse quantization procedure is simplified. These methods can reduce complicatedness and the hardware cost in the execution face for real-time MPEG-4 decoding.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an MPEG-4 inverse D
A method and apparatus for fixed point implementation of C / AC prediction,
Still image coding and moving image coding, in particular M in multimedia communication and digital television systems
It can be used for encoding video using PEG-4.

[0002]

2. Description of the Related Art MPEG-4 Video Final Com
V in mittee draft (FCD) [1]
The video texture decoding process for the OP is shown in FIG. Variable length decoding (101) and inverse scan (10
2) After that, the video texture encoded data is decoded into quantized spatial difference DCT coefficients, and inverse DC / AC prediction (103)
After further decoding the above coefficients using inverse quantization (104) and inverse DCT (105) and motion compensation (1
06) is performed. The first procedure of inverse DC / AC prediction (IP) and inverse quantization (IQ) in FCD is as follows.

[0003] As shown in FIG. 2 for DC / AC prediction direction determination, the DC / AC prediction
Using the value F [0] [0], the DC / AC prediction direction is determined as follows. (| F _A [0] [0] F _B [0] [0] | <| F _B [0] [0] F _C [0] [0] |), (1) Prediction, otherwise predict from block A.

[0004] Any of blocks A, B or C is VO
If they are outside the P boundary or video packet boundary or do not belong to an intra-coded macroblock, the F [0] [0] values of these blocks are 2 ^{(
bits_per_pixel + 2 )} . Where b
its_per_pixel ∈ [4,12] is defined as the number of colors used to represent one pixel.

As shown in FIG. 2 for the inverse DC prediction, the value of the DC coefficient QF [0] [0] is determined by the predicted quantization coefficient PQF [0] [0] and the predictor F [0] [0]. From the following equation. If (predicted from block C), QF _X [0] [0] = PQF _X [0] [0] + F _C [0] [0] // dc_scalar _x (2), otherwise QF _X [0] [0] = PQF _X [0] [0] + F _A [0] [0] // dc_scalar _x (3) Here, the operation // is defined as integer division to round to the nearest integer, and dc_scaler can be obtained from Table 1 according to the corresponding quantizer_scale.

Table 1 dc_scaler values for various quantizer_scale

This process is repeated independently for each macroblock using the appropriate block "A" immediately next to the horizontal and the appropriate block "C" next to the vertical. DC prediction is similarly performed for the luminance and each of the two chrominance components.

As shown in FIG. 3 for inverse AC prediction, when block "A" is selected as a predictor for a block for performing coefficient prediction, A in the first row is selected.
The C inverse prediction is calculated as follows. QF _X [0] [i] = PQF _X [0] [i] + (QF _A [0] [i] * QP _A ) // QP _X (4) where QP = 2 * quantiser_scale (5) is there. When the block “C” is selected as a predictor for a block for which coefficient prediction is to be performed, the first row of AC prediction is calculated as follows. QF _X [j] [0] = PQF _X [j] [0] + (QF _C [j] [0] * QP _C ) // QP _X (6) Predicted block (block “A” or block “C”) )
Is outside the VOP boundary, i.e., outside the video packet, the prediction coefficients for that block are assumed to be all zeros.

[0009] Figure 4 for inverse quantization is an overall inverse quantization process. After an appropriate inverse quantization operation (401), the obtained coefficients, ie,
F '' [v] [u] is subjected to a saturation process (402) to obtain F '[v] [u], and then a mismatch control operation (403) is performed to obtain a final reconstructed DCT coefficient F [ v] [u]. In the intra block, F _X ″ [0] [0] = QF _X [0] [0] * dc_scaler _X (7) If quant_type == 1, all the coefficients except the intra DC coefficient are Dequantization is performed as shown in the equation. F "[v] [u] = ((2xQF [v] [u] + k) xW [w] [v] [u] × quantiser_sca
ler) / 32 where Although the weight matrix W [w] [v] [u] (w = 0,1) has default settings, the above settings can be overwritten by downloading a user-defined matrix. W [0] [v] [u] is used for intra macroblocks, and W [1] [v] [u] is used for non-intra macroblocks. qu
When ant_type == 0, all coefficients other than the intra DC coefficient are inversely quantized as represented by the following equation. F "[v] [u] = Sign (QF [v] [u]) * | F" [v] [u] | (9)

Regarding the prior art of integer division In the prior art of integer division, reciprocal multiplication is generally used instead of division operation. Assuming multi-precision arithmetic, the prior art can be summarized as follows. Z = F / X = F * 1 / X = (F * ^2k / X) / ^2k = (F * ^2k / X) >> k where ^2k / X is the reciprocal value to be multiplied Yes, >> indicates the right shift of k bits of the operation result,
Equivalent to 2 ^k . However, the above formula does not always give the same result as the first division, since the reciprocal can only be represented with finite precision depending on the resolution used to represent it.

[0011]

With the round-off division (//) in MPEG-4, inverse DC / AC prediction is difficult, and an error may occur in real-time use of a fixed-point DSP or ASIC. When performing DSP, a simple approximation of the equation given in section 3.2.5 is not enough.
There is an error due to rounding.
This is because it is not allowed in the conformant decoder. Furthermore, to handle a large reciprocal of the range that must be handled by the MPEG-4 specification, a large dynamic range is required, and special processing and architecture are required. Therefore, it can be said that the problem to be solved is how to perform the rounding division without generating an error due to rounding. In addition, this should be done with the smallest possible dynamic range and without using a divide function.

[0012]

According to the present invention, there is provided a dynamic precision reciprocal value lookup table and a dedicated process capable of eliminating errors due to rounding division and rounding. A particular number of bit precisions and reciprocal values are optimized for each case according to the minimum bit length and ease of implementation. The invention also provides a low-cost hardware architecture for the above method. Embodiment 2 of the present invention also describes a new algorithm that corrects DC / AC prediction and uses multiplication and accumulation (MAC) to eliminate round-off division.

The prior art utilizes a single dynamic range for reciprocal multiplication and shift operations. this is,
This means that the dynamic range must be large enough to satisfy the reciprocal range. The present invention solves the above problem by separating the dynamic range of the operand of the reciprocal multiplication from the shift operation. The denominator of the rounding division to be implemented is 1-4
This is possible because it is within the range of 6. Therefore, the reciprocals of these denominators are 1-0.021739 ...
Within the range. In binary notation, this is 1.0-
0.00000101100100001011 ...

Therefore, the inventive step in the present invention is to signal that the reciprocal significant figure in the fixed point operation using rounding is less than the dynamic range required to represent this reciprocal. Second
Can be multiplied by significant figures without using rising and falling zeros, and the shift operation to the right can be increased to adjust for fixed points. Thus, different right shift coefficients are used for different divisors. The following is a binary representation of this. If Z = round off (F * 0.000001010000 _b ) = (round off '(F * 101 _b )) >> 8

FIG. 5 shows the operation of the present invention. A round-off division is performed by a look-up table (501) having two fields in which the pseudo reciprocal value is stored together with a right shift k. The multiplier (502) multiplies the pseudo reciprocal value by the operand F. The result obtained by the multiplier is passed through a rounding process (503), and the least significant digit is checked to determine a rounding factor. The result obtained by the multiplier is sent to a shifter (504), where the value is shifted to the right by k bits, and the bits shifted to the right are discarded. Finally, the truncated value is added to the adder (50
In 5), the result is added to the rounding coefficient to obtain a result Z by rounding.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiment 1 The round-off division operations in (2), (3), (4) and (5) can be redefined as follows. F _C [0] [0] // dc_scaler _X = F _C [0] [0] * (1 / dc_scaler _X ) + E1 (9) F _A [0] [0] // dc_scaler _X = F _A [0 ] [0] * (1 / dc_scaler _X ) + E2 (10) (QF _A [0] [i] * QP _A ) // QP _X = (QF _A [0] [i] * quantiser_scale _A ) * (1 _{/ quantiser_scale X) + E3 (11} ) (QF C [j] [0] * QP C) // QP X = (QF C [j] [0] * quantiser_scale C) * (1 / quantiser_scale X) + E4 ( 12)

Here, the rounding division (//) by dc_scaler _X or QPx in (2), (3), (4) and (5) is performed by reciprocal values (1 / dc_scaler _X ) and (1 / quantiser_scal
e _X ) and rounding remainders E1, E2, E3 and E4
Replace with multiplication. (9) (10) (11) (1
The rounding division operation in 2) can be modified as follows. F // X = F * (1 / X) + E (13) where F is F [0] [0] ∈ [-2048,2047] and (QF * qua
ntiser_scale) ∈ [-63488, 63457], where X is dc_scal
er _X ∈ [8, 46] and quantizer_scale _X ∈ [1, 31], and E represents E1 to E4. In the fixed-point implementation, if Z = F * (1 / X) (14), then ΔE = Z-F // X (15) For a particular X∈ [1, 46], a special k and pseudo inverse Numerical value (P
IV: Assuming that there is a pair of (k, PIV) tables representing (1 / X) containing values (integers around 2 ^k / X), the proposed algorithm satisfies (14) as follows:

1) Lookup table: temp1 = PIV (X is used as EPROM address) (16) 2) Multiplication: temp2 = F * (temp1) (17) 3) Rounding processing: Z = Rounding (temp2, k, X) (18) Here, the rounding function (temp2, k, X) is defined as follows. ([(Temp2 <0) & (temp2 && (2 k -1))> 2 k-1)] or where [(temp2> 0) & ( temp2 && (2 k -1))> (2 k- ¹ -1))]) If (19), then Z = temp2 >> k + 1 (20); otherwise, Z = temp2 >> k (21). If (X = 1), Z = temp2 (22).

In the above algorithm, the minimum bit length (k, k) shown in Table 2 is such that for all possible combinations of (F, X), the corresponding rounding / division error ΔE in (15) is zero. PIV) A table is built. This table can be stored in a 19-bit data bus and a 6-bit address bus ROM, which is used to construct a DSP system as shown in FIG. 6 and perform round-off division, as shown in FIGS. 7 and 8. The inverse DC / AC prediction of MPEG-4 can be performed by the routine of the flowchart.

The operation of the flowcharts of FIGS. 7 and 8 is as follows. Step S1: dc_scaler is input Step S2: Address calculation and ROM reading (k, PIV) (look-up table) Step S3: k and PIV are stored in different registers Step S4: Direction target is predicted. (F _A [0] [0] F _B [0] [0]
| And | F _B [0] [0] F _C [0] [0] |) Step S5: Address calculation and DC prediction F [0] [0]
Step S6: temp2 = F [0] [0] * PIV Step S7: temp2 <0? Step S8: temp2 && (2 ^k -1)> 2 ^k-1 ? Step S9: temp2 && (2 ^k -1)> ? 2 ^k-1 -1 step S10: Z = (temp2 >> k ) +1 step S11: Z = (temp2 >> k ) step S12: PQF [0] enter [0], QF [0] [0 ] = PQF [0]
[0] + Z Step S13: I = 0 Step S14: Input quantizer_scale _x Step S15: Address calculation and ROM reading (k, PIV) (lookup table) Step S16: k and PIV are stored in different registers Step S17: AC prediction (QF [i] and its quantizer_
Enter scale (qs) Step S18: qs = 1? Step S19: temp1 = QF [i] * qs Step S20: temp2 = temp1 * PIV Step S21: temp2 <0? Step S22: temp2 && (2 ^k -1)> ? 2 ^k-1 step ^{S23: temp2 && (2 k -1} )> (2 k-1 -1) step S24:? Z = QF [i ] step S25: Z = (temp2 >> k ) +1 step S26: Z = (temp2 >> k) Step S27: Input PQF, New QF = PQF + Z Step S28: I ++ i = 8? Step S29: End

Table 2 (k, PIV) ROM table

Table 2 (k, PIV) ROM table (continued)

As shown in FIG. 6, (603) is a fixed point DSP in which the input bit length of the multiplier is 17 bits or more.
It is. (601) is a RAM for storing video data
It is. (602) is a (k, PIV) ROM in which addresses are indexed by X. The DSP implements the algorithm as outlined in this embodiment in the block diagram shown in FIG.

The same algorithm and the same (k, PI
V) Using a table, round-off division (F // X) (F∈ [-63
488, 63457], X∈ [1, 46]). A dedicated hardware device or architecture is shown in FIG. (801) is a (k, PIV) ROM addressed by X. (802)
Is a multiplier having an input bit length of 17 bits or more for implementing (17). (803) is 1 to determine whether 16 LSB of the multiplier output is greater than 1.
It is a 6-input OR gate. (804) is 2 for determining whether 17 LSB of the multiplier output is greater than 1.
Input OR gate. (805) is 1 of the multiplier output.
It is a three-input OR gate for determining whether 9LSB is greater than one. (806) is the multiplier output 20
This is a two-input OR gate for determining whether the LSB is greater than one. (807) is a 1/4 multiplexer controlled by k. (808) is 16 bits, 17 bits, 19 bits, 2 bits,
This is a 4-row barrel shifter that can be shifted right by 0 bits. (809) is logic for making a logical determination as to whether or not the result should be rounded in (19). (810) sets one input to F >> k and the other input to the remaining 0/1 after rounding (20) and (21)
Is an adder for obtaining Z. (812)
Input is X = x ₅ x ₄ x ₃ x ₂ x ₁ x ₀ and output is "= 1" logic gate. That is, if the input is X =
When it is 1, the logic becomes true (= 1), and when it is other input, it becomes false. (811) is a マ ル チ プ レ ク サ multiplexer for executing equation (22).

Embodiment 2 In Embodiment 2 of the present invention, MPEG4 for reducing the complexity of processing, reducing errors, and reducing memory space.
Another method for texture decoding is obtained. First,
Looking at (2), (3), (4) and (5), the function AF [v]
[u] is defined as follows. AF [v] [u] = QF [v] [u] * Scaler [v] [u] (23) where Scaler is defined as follows. Therefore, a general-purpose procedure (GI
P) and a simplified inverse quantization (SIQ) procedure can be derived as follows.

Adaptive DC / A for intra macroblock
The C prediction direction will be described. For intra macroblocks, the adaptive selection of DC and AC prediction directions is still based on a comparison of the horizontal and vertical DC gradients around the block to be decoded. In FIG. 2, blocks "X", "A", "B", and "C" indicate the current block, the left block, the upper left block, and the block immediately above, respectively.

Inverse quantization DC of previously decoded block
Using the value AF [0] [0], DC and A
The C prediction direction is determined. (| AF _A [0] [0] AF _B [0] [0] | <| AF _B [0] [0] AF _C [0] [0] |) If (25), predict from block C Otherwise, prediction is made from block A. If any of blocks A, B, or C is outside the VOP boundary, ie, the video packet boundary, or does not belong to an intra-coded macroblock, the AF [0] [0] value of these blocks is 2 ^(
It can be assumed that the value of ^{bits_per_pixel + 2 )} is taken, and is used for calculating a predicted value.

Next, the inverse prediction of the DC coefficient will be described. For intra macroblocks, after determining the adaptive DC / AC prediction direction, the inverse DC prediction process is as follows.
(Predicted from block C) AF _X [0] [0] = PQF _X [0] [0] * dc_scaler _X + AF _C [0] [0] (26), otherwise AF _X [0] [0] = PQF _X [0] [0]] * dc_scaler _X + AF _A [0] [0] (27) In the case of non-intra macroblocks, the _{AF X [0] [0]} = PQF X [0] [0] * quantizer_scale X [0] [0] (28). "Short_" in the MPEG4 bit stream
video_header = 1 ", dc_scaler is a fixed value dc_sc
Since aler = 8, AF _X [0] [0] = PQF _X [0] [0] * 8 (29) This inverse prediction process is repeated independently for each block of the macroblock using the appropriate block "A" immediately to the left and the appropriate block "C" immediately above for each of the luminance and two chrominance components. .

Next, the inverse prediction of the AC coefficient will be described. AC prediction scheme (MPEG4
When using ac_pred_flag = 1 ′ in the bitstream, the current block of the current block is used with either the coefficients obtained from the first row or the first column of the previously encoded block. Predict co-sited coefficients. The best direction (left or top) for DC coefficient prediction is also used on a block basis, and a direction for AC coefficient prediction on the first row / first column is selected as shown in FIG. When block "A" is selected as a predictor, the inverse AC in the first column
The prediction procedure is as follows. AF _X [0] [i] = PQF _X [0] [i] * quantizer_scale _X + AF _A [0] [i] where i = 1 to 7 (30) When block “C” is selected as a predictor The AC inverse prediction procedure in the first row is as follows. AF _X [j] [0] = PQF _X [j] [0] * quantizer_scale _X + AF _C [j] [0] where j = 1 to 7 (31)

If a prediction block (block "A" or block "C") is outside of a VOP boundary, ie, a video packet, all AC predictor coefficients for that block are assumed to be zero. Other AC that is not predictive
For other cases as coefficients or non-intra macroblocks, ac_pred_flag = 0 or "short_video_head
er = 1 ”: AF _X [v] [u] = PQF _X [v] [u] * quantizer_scaler _X (32) Therefore, during the newly defined GIP processing, the coefficient PQF [v] is used in any case. From [u] to the appropriate inverse quantization coefficient AF [v]
[u] is generated.

Next, the inverse quantization will be described. Coefficient AF [v] [u]
Are further quantized to generate reconstructed DCT coefficients as shown in FIG. After an appropriate inverse quantization operation, the obtained coefficient (901), that is, F ″ [v] [u] is saturated, and F ′ [v] [u] (902) is obtained. The final reconstructed DCT coefficient F [v] [u]
(903). Further, since there is an AF function, F '' [v] [u] can be calculated as follows.
In the intra block, it is necessary to obtain F '' [0] [0] directly from AF [0] [0]. When quant_type == 1, all coefficients other than the intra DC coefficient are inversely quantized as represented by the following equation. F '' [v] [u] = (2 * AF [v] [u] + k * quantiser_scale) * W [w] [v] [u] / 32 (33) where When quant_type == 0, all coefficients other than the intra DC coefficient are inversely quantized as represented by the following equation. F "[v] [u] = Sign (AF [v] [u]) * | F" [v] [u] | (36)

Therefore, the MPEG-4 texture decoding procedure can be modified as shown in FIG. In FIG. 10, (1003) executes new inverse DC / AC prediction as shown in (25) to (32), and (1004) executes FIG.
Execute the operation of (1001) (1002) (100
5) Other blocks such as (1006) are (10) in FIG.
1) Same as (102), (105) and (106).

[0033]

The present invention is extremely efficient in reducing the complexity and numerical errors and hardware costs of performing DC / AC coefficient inverse prediction and inverse quantization for MPEG4 video texture decoding. The present invention also relates to any existing DSP (Digital Signature Processor).
Alternatively, the present invention can be applied to an ASIC (application-specific integrated circuit) design.

[Brief description of the drawings]

FIG. 1 is a process diagram of a video texture decoding according to the prior art.

FIG. 2 is a block diagram of neighbors used in DC prediction.

FIG. 3 is an explanatory diagram showing adjacent blocks and coefficients used in AC inverse prediction;

FIG. 4 is a block diagram of a conventional inverse quantization process.

FIG. 5 is a block diagram of a rounded integer division.

FIG. 6 is a block diagram of a fixed point DSP for MPEG4 inverse DC / AC prediction without error due to rounding.

FIG. 7 is a first half of a flowchart of a DSP program routine for MPEG4 inverse DC / AC prediction;

FIG. 8 is the second half of a flowchart of a DSP program routine for MPEG4 inverse DC / AC prediction.

[Figure 9] Rounding / dividing Z = F // X (F∈ [-63488, 63457],
Block diagram of the device for X∈ [1, 46])

FIG. 10 is a block diagram of the inverse quantization process of the present invention.

FIG. 11 is a block diagram of a video texture decoding process using the function AF of the present invention.

[Explanation of symbols]

 101 variable length decoding 102 inverse scan 103 inverse DC & AC prediction 104 inverse quantization 105 inverse DCT 106 motion compensation 401 inverse quantization operation processing 402 saturation processing 403 mismatch control 501 lookup table 502 Multiplier 503: Rounded processor 504: Shifter 505: Adder 801: (k, PIV) ROM 802: Multiplier 807: Multiplier 808: Shifter 810: Adder 811: Multiplier 812: = 1 logic 901: Inverse quantum Conversion processing 902: Saturation processing 903: Mismatch control 1001 ... Variable length decoding 1002 ... Inverse scan 1003 ... Inverse DC & AC prediction 1004 ... Inverse quantization 1005 ... Inverse DCT 1006 ... Motion compensation

 ──────────────────────────────────────────────────の Continued on the front page (72) Inventor Tio Ken Tan Singapore 534415 Singapore, Thai Sen Avenue, Block 1022, 04-3530, Thai Sen Industrial Estate, Panasonic Singapore Research Institute, Inc. F term (reference) 5B056 AA01 BB11 FF02 HH03 5C059 KK15 MA00 MA04 MA05 MA23 MC33 MC35 ME01 UA05 5C078 AA09 BA21 BA57 CA25 DA00 DA02 DA12

Claims (9)

[Claims] A DCT transform coefficient uses a scaling factor that requires integer division using rounding, and performs integer division using rounding using fixed point integration using a pseudo reciprocal value (PIV) and variable length shift (k). A method in digital hybrid transform video decoding, wherein a prediction process is performed by a predictor that requires integer division performed by the method. 2. A method for performing integer division using rounding by fixed point integration using a pseudo inverse value (PIV) and a variable right shift (k), comprising: (a) a first operand of a multiplier; (B) obtaining a pseudo-inverse value and a right shift from a look-up table based on a denominator as an index to the look-up table; and (c) obtaining a pseudo-reciprocal value as a second operand of the multiplier. (D) checking the k least significant bits of said integration result;
Determining the rounding coefficient; (e) efficiently shifting the integration result to the right by k bits; (f) truncating the k least significant bits; and (g) determining the rounding coefficient as required. Adding to the shift result. 3. The look-up table, comprising a pair of a pseudo-inverse value (PIV) and a right shift (k),
The method of claim 1, wherein the look-up table includes the values shown in Table 2. 4. A method for checking a k least significant bit of the integration result and determining a rounding coefficient, comprising: (a) determining a sign of the integration result; and (b) determining a positive integration result. Means that the k least significant bits are 2 ^k-1
If greater than, set the rounding factor to "1"; otherwise, set the rounding factor to "0"; and (c) for negative integration results, the k least significant bit is 2 ^{k -1-}
If greater than 1, set the rounding factor to "1"
Otherwise, setting the rounding factor to "0". 5. An apparatus for performing integer division using rounding by pseudo point reciprocal value and fixed point integration using variable shift, comprising: (a) a pair of pseudo reciprocal values (PIV) using a denominator as an index. ) And a read-only memory lookup table including right shift (k); (b) a multiplier that takes the numerator as the first operand and a pseudo-reciprocal value as the second operand; A rounding logic for generating a rounding coefficient, (d) a shifter for truncating the k least significant bits and efficiently shifting the integration result to the right by k bits, and (e) a rounding coefficient for the shift result. An adder for adding as necessary. 6. An apparatus for rounding logic, comprising: (a) means for determining whether any of the k-1 least significant bits is "1"; and (b) an integration result. And a means for setting the rounding coefficient to "1" when the (k-1) th bit is "1", and for a positive integration result, Means for setting the rounding coefficient to “0”; and (c) for the negative integration result, the k−1th bit is “1” and any of the k−1 least significant bits is “1”. The method according to claim 5, further comprising: means for setting the rounding coefficient to "1" when ".", And (d) means for setting the rounding coefficient to "0" otherwise. apparatus. 7. A method for performing inverse DC / AC prediction and thereby performing inverse quantization of MPEG-4 video decoding, comprising: (a) determining an adaptive DC / AC prediction direction; (B) a general-purpose procedure for inverse DC / AC prediction, and (c) a simplified inverse quantization procedure. 8. A correction procedure for determining an adaptive DC / AC prediction direction, comprising: (a) selecting a block diagonally and left of a current block as a reference block; and (b) The first between the DC coefficient of the approximate quantized DCT coefficient of the block to the left of the current block and the reference block
Evaluating the absolute difference of: c) the second block between the DC coefficient of the approximate quantized DCT coefficient of the block above the current block and the reference block;
(D) comparing the first absolute difference with the second absolute difference; and (e) if the first absolute difference is smaller than the second absolute difference. The method of claim 7, comprising: selecting a vertical prediction direction; and (f) otherwise selecting a horizontal prediction direction. 9. A general-purpose procedure for inverse DC / AC prediction, comprising: (a) calculating a product of a predicted quantization coefficient and a quantizer scale of a current macroblock; and (b) approximating quantization. The DCT coefficient is calculated as the sum of the product and the predictor, and (c) the predictor is the first column of the block on the left or the upper block, depending on whether the prediction direction is horizontal or vertical. The method of claim 7, wherein the quantized DCT coefficients from the first row are approximated.