JP2001103356A - High-speed video camera - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a low cost video camera that can pick up an image of an object at high speed and output a standard composite video signal. SOLUTION: The high-speed video camera 1 is provided with a CCD sensor 11 that outputs the video signal of the object at a speed being a multiple on N of that of a standard video signal, an A/D converter circuit 17 that applies A/D conversion to its output signal, a memory 21 that cyclically stores the video signal at a speed being a multiple of N of that of the standard video signal, and a D/A converter circuit 23 that applies D/A conversion to the video signal read from the memory 21 and provides an output of the result as the standard video signal. The camera 1 is further provided with a memory control section 6 that generates a write/read address and supplies it to the memory 21, and receives an internal or external trigger signal to switch a raw video mode where the digital image data stored in the memory 21 are skippingly reproduced by aborting data not matching the read timing among the digital image data into a slow reproduction mode where all the digital image data stored in the memory 21 are read and reproduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-speed video camera, and more particularly, to a high-speed video camera that automatically switches to slow reproduction in response to a change in an image or an external signal.

[0002]

2. Description of the Related Art In a conventional high-speed video camera, a general-purpose solid-state imaging device such as a CCD image sensor device or a MOS image sensor device is driven by a high-speed clock. By using a solid-state imaging device, imaging of a phenomenon operating at high speed has been realized.

[0003] Some of these high-speed video cameras output digital signals and others output analog signals. However, since each signal is a signal in a dedicated system by each manufacturer, it is necessary to obtain an image. A dedicated digital processing circuit and a dedicated video recorder were separately required.

[0004]

However, these devices are extremely expensive, which has been a hindrance to the widespread use of high-speed video shooting technology.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a video camera capable of high-speed imaging and outputting a standard composite video signal at low cost.

[0006]

The present invention solves the above-mentioned problems by the following means.

That is, a high-speed video camera according to the present invention comprises an image pickup means for picking up an image of a subject in a first cycle, and an A / D conversion means for converting each of the subject images picked up by the image pickup means into digital image data. Storage means for storing each of the digital image data; and a general-purpose signal for reading out the digital image data stored in the storage means at a second cycle longer than the first cycle and converting it into a general-purpose composite video signal Generation means and whether to supply all of the digital image data stored in the storage means to the general-purpose signal generation means or to supply a part of the digital image data stored in the storage means to the general-purpose signal generation means And a reproduction mode selecting means for switching the digital image data, wherein the storage means has no empty area for storing new digital image data. If that, and to update the order new digital image data from the old digital image data.

Preferably, the storage means stores each of the digital image data at the first cycle.

Further, the reproduction mode selection means includes a first mode for reading out the digital image data stored in the storage means at a predetermined interval and a second mode for reading out all the digital image data stored in the storage means. It is desirable to select one of the second mode and a third mode in which the digital image data stored in the storage means is read out with a delay corresponding to the capacity of the storage means.

Further, the reproduction mode selection means selects the first mode in an initial state, selects the second mode when a predetermined trigger signal is input, and selects the second mode when the second mode is selected. It is preferable to select the third mode when there is no free space in the storage means.

[0011] The high-speed video camera further comprises a motion detecting means for comparing a plurality of digital image data stored in the storage means with each other to detect a portion where the motion amount of the image exceeds a predetermined reference amount. It is preferable that the trigger signal be supplied to the reproduction mode selection means when the movement detection means detects the location.

It is desirable that the motion detecting means has a learning function of optimizing the reference amount in accordance with a desired motion of a desired subject.

When a predetermined reset signal is input after selecting the third mode, the reproduction mode selection means deletes all digital image data stored in the storage means and deletes the digital data. It is good to select mode 1.

[0014] The high-speed video camera may further include time measuring means for measuring a lapse of time from the time when the reproduction mode selecting means selects the third mode, and the time measured by the time measuring means. It is preferable that the reset signal be supplied to the reproduction mode selection means when a predetermined time has elapsed.

In the high-speed video camera, when the reproduction mode selection means selects the third mode, a time interval for storing new digital image data in the storage means, and a digital image data stored in the storage means, Further comprising a free space adjusting means for adjusting a time interval for reading image data and gradually increasing the free space of the storage means,
It is more preferable that the reproduction mode selection means selects the first mode at the time when the free space adjustment means makes all storage areas of the storage means free after selecting the third mode. is there.

In the high-speed video camera, the general-purpose signal generating means converts the digital image data into an analog video signal compatible with the composite video signal.
/ A conversion means, or digital video signal generation means for converting the digital image data into a digital video signal compatible with the composite video signal.

[0017]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a schematic configuration of an embodiment of a high-speed video camera according to the present invention. The high-speed video camera 1 shown in FIG. 1 includes an imaging unit 4, a digital signal processing unit 5, a timing generation circuit 2, a synchronization signal generation circuit 3, and a memory control unit 6.

The image pickup section 4 includes a CCD sensor 11, a high-speed drive circuit 13, an amplifier 15, and an AD conversion circuit 17. The high-speed driving circuit 13 generates a high-speed clock signal of a standard video signal screen refresh rate, for example, N times (N is a natural number) 60 Hz in the case of the NTSC system, and drives the CCD sensor 11 based on this clock signal. . It is desirable that the clock signal be practically 2 to 10 times the refresh rate of the standard video signal.

The CCD sensor 11 is driven by a high-speed drive circuit 13 to shoot a subject at a high speed at the above-described speed, and outputs a video signal.

The video signal output from the CCD sensor 11 is amplified by an amplifier 15 and then digitized by an AD converter.

The digital signal processing unit 5 includes a memory 21, a DA conversion circuit 23, an image compression circuit 31, and a DV (Digital
Video) interface 33.

The timing generation circuit 2 includes a high-speed drive circuit 1
3 and supplies the same high-speed clock signal to the AD conversion circuit 17 to control the timing of the signal conversion. Further, the timing generation circuit 2
Supplies a high-speed clock signal to the memory 21 and controls writing and reading of a video signal according to an address supplied by the memory control unit 6 described later. The timing generation circuit 2 also
The high-speed clock signal is supplied to the synchronization signal generation circuit 3, and the synchronization signal generation circuit 3 generates a clock signal having a refresh rate of a standard video signal (hereinafter, referred to as a standard speed clock signal) based on the high-speed clock signal. D
The signal is supplied to the A conversion circuit 23 to control the signal conversion timing.

The memory 21 receives a supply of a write address from the memory control unit 6 described later, and receives a supply of a write / read control signal from the timing generation circuit 2, and has the same drive cycle as that of the CCD sensor 11. Digital image data is stored periodically. The memory 21 has a capacity capable of storing a plurality of images, for example, a capacity of at least about 10 images,
If possible, a semiconductor memory having a capacity of about 200 is desirable. The digital image data is stored cyclically in the storage area of the memory 21, and when the storage capacity is reached, the digital image data is overwritten and stored, for example, in the first storage area.

The digital image data read from the memory 21 is converted into an analog standard video signal by a DA converter, amplified through an amplifier 8, and output. At this time, if all the images read and converted from the memory 21 are continuously played back, slow playback is performed. However, if digital image data that does not match the read signal cycle is discarded and played back discretely, playback at normal speed is performed. Is also possible.
If the normal speed is selected for both the recording and the reproduction, the recording in the memory 21 can be performed step by step, and the stepped video can be continuously reproduced.

As described above, the high-speed video camera 1 of the present embodiment can simultaneously perform photographing and reproduction with different periods.

In addition to the analog interface described above,
The high-speed video camera 1 according to the present embodiment also includes a digital interface 7. When outputting as a digital signal, the digital signal read from the memory 21 is supplied to the image compression circuit 31 as it is, supplied to the DV interface 33 through a predetermined compression process, and output to a display device or a recording device. That is, when the analog output is selected, the DA conversion circuit 23 constitutes a general-purpose signal generation means, while when the digital output is selected, the image compression circuit 31 and the DV interface 33 constitute the general-purpose signal generation means. . In this embodiment, the case where both the analog interface and the digital interface 7 are provided has been described. However, the present invention is not limited to this, and only one of them may be provided according to the required specification.

The memory control unit 6 corresponds to the reproduction mode selection means in this embodiment, and includes the motion detection circuit 19, the two multiplexers 41 and 51, the state control circuit 43, the write counter 45, the read counter 47, and the collision detection circuit. 49 and a reset counter 55.

The motion detection circuit 19 generates an internal trigger signal for switching a reproduction mode, which will be described later, based on the video signal supplied from the AD conversion circuit 17.

The multiplexer 41 selects either an external trigger signal supplied from an external trigger generation circuit (not shown) or an internal trigger signal supplied from the motion detection circuit 19 and supplies the selected signal to the state control circuit 43.

The state control circuit 43 includes a multiplexer 41
In response to an external or internal trigger signal supplied from the controller or a reset signal supplied from a counter (not shown), a reproduction mode described later is switched, and a corresponding control signal is supplied to the write counter 45 and the read counter 47.

Write counter 45 and read counter 47
Generates a write address and a read address based on a control signal supplied from the state control circuit 43 and supplies the write address and the read address to the multiplexer 51. The multiplexer 51 alternately selects a write address and a read address and
To supply. Further, the collision detection circuit 49 receives the supply of the write address and the read address from the write counter 45 and the read counter 47, monitors the generation timing of these addresses, and when supplied at the same timing, the addresses collide. This is transmitted to the state control circuit 43 as such. The reset counter 55 corresponds to a time measuring unit in the present embodiment. The collision detection circuit 49 and the reset counter 55 will be described later in detail.

In the high-speed video camera 1 of the present embodiment, the imaging and the writing of the image data to the memory 21 are always processed in the cycle of the high-speed clock signal. On the other hand, the reading of the image data and the digital processing thereof are always standard. Processing is performed at the cycle of the speed clock signal. Therefore, a timing shift occurs between the imaging timing and the video reproduction timing. In the high-speed video camera 1 according to the present embodiment, the memory control unit 6 processes the timing shift by appropriately switching the playback state between a plurality of playback modes.

The specific processing procedure of the memory control unit 6 will be described in detail with reference to the drawings.

FIG. 2 is a schematic diagram showing an example of write / read control to / from the memory 21 by the memory control unit 6. In the same figure, the screen described in the upper part of the paper schematically shows an image of the subject captured by the imaging unit 4. The number described in each screen is a stamp indicating the recorded time.
In the figure, the memory has a storage area for three images.
As described above, the capacity of the memory 21 is at least
The number of sheets is necessary, and about 100 sheets are desired effectively,
It is desired that the imaging speed is three times or more that of the standard video signal. However, in order to simplify the description below, the memory capacity is only three images, and the shooting speed is twice that of a normal video signal. Is assumed to have a recording capacity for one screen. Further, for convenience of explanation, FIG.
, Addresses 0 to 2 are assigned to the respective storage areas of the memory. This address corresponds to the upper address in the actual memory 21, and the lower address is counted at high speed at the timing of the image corresponding to the dot of the image. Is simply called the street address. Further, the reproduced standard video image is schematically shown on the screen described below the page of FIG.

First, the specific contents of the reproduction mode selected by the memory control unit 6 will be briefly described with reference to FIG. In the initial setting state, all images shot at high speed are written to the memory. Memory is used cyclically, and old videos are discarded. Since the reproduction side reproduces at a normal speed (one in two in this example), the read image is skipped with respect to the original operation of the subject. This state is referred to as “raw video state (first mode)”. In other words, the video captured in the same manner as a normal video camera having a normal imaging speed is reproduced as it is.

Next, in this state, when a trigger signal generated externally or internally is supplied to the state control circuit 43 via the multiplexer 41 (see FIG. 1), the skipped reproduction is stopped and the reproduction is continuously performed. I do. That is, all the recorded images are reproduced. This state is referred to as the “slow playback state (second
Mode). In the slow playback state, the memory 21
Since the writing speed to the memory 21 is faster than the reproducing (reading) speed, the free area of the memory 21 runs out after a certain period of time.
Cannot write. On the other hand, if one image is reproduced by slow reproduction, the digital image data may be discarded from the memory 21. Therefore, new digital image data is written at a high speed into the discarded and empty storage area. In this case, since the reproducing operation is slower than the recording operation, the recordable moment is skipped. Memory 21
Is recorded at the moment when the storage area is empty, and as a result, it looks like the recording / reproduction at the normal speed. However, in terms of time, there is a delay from recording to reproduction by the number of videos that can be stored in the memory 21 in one cycle. This state is referred to as a “delayed reproduction state (third mode)”. In this state, the next trigger signal cannot be accepted,
Upon receiving a reset signal at an appropriate time, the system forcibly shifts to a raw reproduction state. The reset signal is generated by a reset counter 55 (see FIG. 1) included in the memory control unit 6, counts the time elapsed since the transition to the third mode, and generates a reset signal when a predetermined time has elapsed. State control circuit 4
Supply 3 State control circuit 43 receiving reset signal
Deletes all the digital image data stored in the memory 21, whereby the reproduction mode shifts to the raw reproduction state.

As shown in FIG. 2, the imaging screen 1 is stored at the memory address 0, and the subsequent imaging screen 2 is stored at the memory address 1.
And the imaging screen 3 is written to the memory address 2.
In this time zone, the reproducing side reads the screen 1 from the memory address 0 and reproduces it. However, since the reading speed is lower than the recording speed, the memory address 1 on which the imaged screen 2 is recorded is discarded without reading. When the screen 1 is displayed to the end, the memory address 2 on which the screen 3 is recorded is read out and reproduced.
An algorithm for discarding an image that does not match the read timing can be created very easily, and it is only necessary to copy the address of the memory currently written on the writing side at the timing when the reading side updates the address on a new screen. More specifically, the copy is processed by the write counter 45 supplying the read value to the read counter 47 in the control circuit unit 5 shown in FIG. As described above, in the live video state, the recording operation of all the captured videos and the skipping reproduction operation are repeated.

The raw video state is shifted to a slow reproduction state by a trigger signal. In the slow reproduction state, the entire screen of the captured video is recorded, and the recorded entire screen is reproduced. That is,
In FIG. 2, high-speed photographed images 4 to 7 are sequentially recorded in a memory, and in parallel with this, recorded screens 4 to 7 are sequentially read from a memory 21 and reproduced at a standard speed. Here, screen 7
Is recorded at the memory address 0.
The memory address 0 originally recorded the screen 4, but at the time of writing the screen 7, it has already been reproduced and the contents can be discarded.
Overwrite.

On the other hand, at the timing of writing the screen 8, since no data can be discarded, the screen 8 cannot be written (write disabled). The photographed video 8 requests writing to the memory address 1 in order, but since the memory address 1 is reproducing the recorded image 5, writing is not possible and writing is not permitted. As a result, the image 8 is not recorded.

The algorithm for determining whether or not writing can be performed is simple. If the address being reproduced at present is equal to the address to be recorded next, it is sufficient to determine that writing is not performed. More specifically, the collision detection circuit 49 compares the counter value supplied from the write counter 45 with the counter value supplied from the read counter 47 in the control circuit unit 5 shown in FIG. When the values are equal, the fact is supplied to the state control circuit 43. The state control circuit 43 invalidates the count value of the write counter 45 in response to the detection result of the collision detection circuit 49.

Returning to FIG. 2, at the next timing of the screen 8 where writing is not possible, the high-speed photographed image 9 requests writing to the memory address 1 again. At this time, since the reproducing side has shifted to the recorded image 6 at the memory address 2, writing of the image 9 at the address 1 is permitted. Similarly, writing of the image 10 is not permitted, and writing of the next image 11 is permitted. That is, when the memory 21 becomes full during slow reproduction, images are sequentially recorded at addresses that have become empty after reproduction.

Here, the recorded video is reproduced.
The time has been delayed by the slow playback.
For example, as shown in FIG. 2, the reproduction of the high-speed photographed video 9 is the time when the image 13 is recorded when viewed from the recording time, and there is a delay of four frames (delayed reproduction state). This delay depends on the writing speed to the memory 21 and the memory 21
It is determined from the relationship with the reading speed from the memory, and a certain delay occurs. The following three methods can be considered to eliminate this delay. That is, (1) a method of forcibly resetting externally,
(2) a method of automatically resetting by counting a predetermined time, and (3) a method of thinning out the recorded images to be recorded, gradually increasing an empty memory, and taking time to make all of them empty.

Of these three methods, the method (1) is simple and clear, and the method (2) uses the above-described reset counter 55, so that the description is omitted, but these two methods are omitted. Is adopted, all the digital image data already stored in the memory 21 is erased by the reset, and the mode immediately shifts to the raw video mode, so that the video for the delay time is skipped.

The method (3) performs the following processing. First, when there is no free space in the memory 21 in the slow reproduction state, the state immediately shifts to the delay reproduction state described above, and this state is continued for a certain period of time. After that, even if the storage area for one screen is free, writing permission to the memory is not given, and writing is not yet performed at this stage. Writing is permitted only when the storage area for another frame, that is, a total of two frames, becomes empty. Next, permission is not given until there is a room area for three screens in the storage area of the memory. With such a procedure, the free area of the memory 21 is increased, the delay time is gradually reduced, and the entire storage area of the memory 21 is made empty over time. This algorithm can be realized by the state control circuit 43 receiving the detection result of the collision detection circuit 49 and controlling the write counter 45. That is, the state control circuit 43 also constitutes an empty capacity adjusting unit in the present embodiment. When observing the third method from the playback side, it appears that the standard video is played back after the slow playback, followed by fast-forward playback (thinned recording state), and then returns to the raw video. According to this method, there is an advantage that continuous reproduction can be obtained without a sudden jump as in the case of resetting. However, it takes a relatively long time to eliminate the delay.

FIG. 3 is a state transition diagram for explaining the switching of the reproduction mode by the above-described delay eliminating method. That is, FIG. 7A shows the delay eliminating method by only resetting (1) and (2), and FIG. 8B shows the delay eliminating method including fast-forward reproduction of (3).

As shown in FIG. 3 (a), according to the delay elimination method using only resetting, a transition is made from a raw video state to a slow reproduction state by an external or internal trigger signal. Here, if the forced reset is performed by the method (1) described above, the display returns to the live video state. However, the slow reproduction state may be continued, the memory 21 may be full, and the transition to the delayed reproduction state may be performed. In the method (2) described above,
After the memory 21 becomes full and the state shifts to the delay reproduction state, it is automatically reset.

According to the delay elimination method shown in FIG. 3B, first, a transition is made from a raw video state to a thinned-out recording state (fast-forward reproduction state) through a slow reproduction state and a delayed reproduction state. Here, the forced reset can be performed in any of the slow reproduction state, the delayed reproduction state, and the thinned recording state. However, according to the method (3), the thinned recording state is continued and the entire storage area of the memory 21 is stored. Is returned to the raw video state after the is empty.

As a modified example of the trigger operation, the address of the memory 21 for recording in the live video state and the memory 21 for reproduction are
When an offset (displacement) is added to the address, the user will see the already delayed raw video in the raw video state. In this state, when a trigger signal is input, it is possible to slowly reproduce the video up to the moment immediately before the input of the trigger signal.
If the displacement between the memory address to be recorded and the memory address to be reproduced is set over the entire memory capacity, the slow reproduction is completely performed before the trigger. Similarly, by setting about half of the memory capacity, the video before and after the trigger signal is input can be slowly reproduced. This function is similar to the play post trigger function found on oscilloscopes and is useful for analyzing phenomena.

The trigger signal includes, besides an external signal,
From the video being shot, digital image processing
It is also possible to detect a fast-moving object or the like and generate it internally. Since the CCD sensor 11 continuously shoots at high speed, its movement can be easily detected only by comparing two temporally consecutive images.

In the high-speed video camera 1 shown in FIG. 1, the motion detection circuit 19 of the memory control unit 6 generates an internal trigger based on the video signal supplied from the imaging unit 4.

FIG. 4 is a schematic diagram for explaining an example of the operation of the motion detection circuit 19. A small area is set at the center of the imaging screen, and when an object passes through this small area, this is detected and a trigger signal is generated. As a calculation method for detection, subtraction is performed between two consecutive screens for the luminance in the small area. For example, as shown in FIG. 4A, when the movement of the object (ball) is slow and passes through a small area at a low speed, (luminance of video (T + 1)) − (luminance of video T),
(Luminance of video (T + 2))-(luminance of video (T + 1))
In both cases, the result of the subtraction is not so large, and there is little change in the image. On the other hand, as shown in FIG. 3B, when the movement of the object (ball) passes fast and at high speed, the subtraction result is large and the amount of change in the image is large. In this way, with a simple process, a slow change can be removed and a trigger signal can be generated only in response to a fast change.

Although the simplest method has been described here, it is of course possible to generate a trigger with strict conditions if more advanced image processing is employed. Furthermore, if a special operation mode called “learning mode” is prepared in advance, the trigger position can be automatically set. The learning mode can be entered from a live video state by a push switch (not shown) or the like. When the switch is released, the display returns to a normal live video state. First, the image is divided into about 4 × 4, and the motion of the subject is detected in each area. Next, the learning mode is set (by pressing the switch), the subject is photographed by the camera, and the movement to be actually triggered is simulated. For example, FIG.
In the case of the ball, the ball is actually crossed in front of the CCD sensor 11. In the learning mode, which of the divided areas shows the largest change is learned and stored. Further, the change amount of the image immediately before entering the learning mode is also stored. The amount of change immediately before this corresponds to a so-called noise level. By calculating an appropriate threshold value from the amount of change in the learning mode and the amount of change immediately before the learning mode, and learning a plurality of trials, it is possible to optimize the regional spread.
After exiting the learning mode, a trigger signal is generated using the parameters calculated from the learning mode. The features of this learning method are as follows: (1) No troublesome area or level setting is required; (2) Therefore, switches can be greatly reduced.
(3) The circuit is simple and easy to realize.

As an output format of the high-speed video camera 1 of the present embodiment, in an analog format, an NTSC compatible signal or PA
An L compatible signal or the like is suitable, and the digital system is DV (Digital Video) of the IEEE 1394 standard.
Terminals are suitable. Even in the digital case, NTS
The compression operation from the C-compatible digital signal can be performed very easily because the integrated circuit of the commercial (home) video camera already exists, and the subsequent recording can be performed by using a commercially available inexpensive device.

As an embodiment of the high-speed video camera according to the present invention, a CCD sensor such as ICX054, AD
An apparatus was prototyped using an AD9224 manufactured by Analog Devices as a converter, a XC4010E manufactured by Xilinx for a digital signal processing unit, a HM628511 manufactured by Hitachi as a memory, and an AD9760 manufactured by Analog Devices as a DA converter. According to the prototype, an image of 256 x 240 dots is about 5 msec.
, And the video was played back in a 6 × slow playback state and converted to an NTSC video signal. The volume of this prototype is about 450 cm ³ and its weight is about 300
g, its power consumption was 5W.

As described above, according to the present invention, a high-speed video camera which is clearly smaller, lighter, and consumes less power than conventional products, and which is inexpensively inexpensive as compared with conventional products even when considering the number of components. It was verified that it could be realized.

[0057]

As described in detail above, the present invention has the following effects.

That is, according to the present invention, it is possible to provide an inexpensive video camera which can capture images at high speed and output a standard composite video signal, and has an excellent user interface. Accordingly, in various research fields requiring high-speed video shooting, it will be adopted as a method for easily shooting and will be widely used. As a result, previously unknown scientific and technical questions will be elucidated, and it will contribute to the development of science and technology. The main applications that can be used immediately are: recognition of running cars, high-speed shooting of sports, etc., automation of slow playback, shooting in research departments such as biological motion, visual inspection of high-speed moving objects on factory production lines And so on.

[Brief description of the drawings]

FIG. 1 is a block diagram schematically showing an embodiment of a high-speed video camera according to the present invention.

FIG. 2 is a schematic diagram showing an example of an operation of a memory control unit provided in the high-speed video camera shown in FIG.

FIG. 3 is a state transition diagram illustrating a method for eliminating a delay of a reproduced video with respect to a captured video.

FIG. 4 is a schematic diagram illustrating an operation of a motion detection circuit included in the high-speed video camera shown in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 High-speed video camera 2 Timing generation circuit 3 Synchronization signal generation circuit 4 Imaging part 5 Digital signal processing part 6 Memory control part 7 Digital interface 8,15 Amplifier 11 CCD sensor 13 High-speed drive circuit 17 AD conversion circuit 19 Motion detection circuit 21 Memory 23 DA conversion circuit 31 Image compression circuit 33 DV interface 41, 51 Multiplexer 43 State control circuit 45 Write counter 47 Read counter 49 Collision detection circuit 55 Reset counter

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[Procedure amendment]

[Submission date] October 13, 1999 (1999.10.
13)

[Procedure amendment 1]

[Document name to be amended] Drawing

[Correction target item name] All figures

[Correction method] Change

[Correction contents]

FIG.

FIG. 3

FIG. 2

FIG. 4

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5C022 AA14 5C052 AA17 AC02 DD10 GA01 GB01 GC02 GD01 GD05 GD06 GE04 GF01 GF04 5C053 FA27 FA30 GA10 HA23 KA04 KA08 KA19 KA20 LA01

Claims (11)

[Claims] 1. An image pickup means for picking up an image of a subject at a first cycle; A / D conversion means for converting each of the subject images picked up by the image pickup means into digital image data; and storing each of the digital image data. A general-purpose signal generating unit that reads digital image data stored in the storage unit at a second period longer than the first period and converts the digital image data into a general-purpose composite video signal; Reproduction mode selection means for switching whether to supply all of the obtained digital image data to the general-purpose signal generation means or to supply a part of the digital image data stored in the storage means to the general-purpose signal generation means. The storage means sequentially stores the old digital image data when free space for storing new digital image data is exhausted. A high-speed video camera characterized by updating to new digital image data. 2. The high-speed video camera according to claim 1, wherein said storage means stores each of the digital image data at the first cycle. 3. The reproduction mode selection means comprises: a first mode for reading out digital image data stored in the storage means at predetermined intervals, and a second mode for reading out all the digital image data stored in the storage means. 2. A method according to claim 1, further comprising selecting one of a second mode and a third mode for reading out the digital image data stored in said storage means with a delay corresponding to a capacity of said storage means. Or the high-speed video camera according to 2. 4. The reproduction mode selection means selects the first mode in an initial state, selects the second mode when a predetermined trigger signal is input, and selects the second mode when the second mode is selected. 4. The high-speed video camera according to claim 3, wherein the third mode is selected when there is no free space in the storage unit. 5. A motion detecting means for comparing a plurality of digital image data stored in said storage means with each other to detect a portion where a motion amount of an image exceeds a predetermined reference amount, wherein said motion detecting means 5. The high-speed video camera according to claim 4, wherein when the position is detected, the trigger signal is supplied to the reproduction mode selection unit. 6. The high-speed video camera according to claim 5, wherein said motion detecting means has a learning function of optimizing said reference amount according to a desired motion of a desired subject. 7. When a predetermined reset signal is input after selecting the third mode, the reproduction mode selection means erases all digital image data stored in the storage means and deletes the digital image data. 7. The high-speed video camera according to claim 4, wherein one mode is selected. 8. The apparatus according to claim 1, further comprising a time measuring means for measuring an elapsed time from a point in time when said reproduction mode selecting means selects said third mode, wherein a time measured by said time measuring means reaches a predetermined time. The high-speed video camera according to claim 7, wherein the reset signal is supplied to the reproduction mode selection unit. 9. A time interval for storing new digital image data in said storage means and a time interval for reading out digital image data stored in said storage means when said reproduction mode selection means selects said third mode. And a free space adjusting means for gradually increasing the free capacity of the storage means, wherein the reproduction mode selection means selects the third mode, and then the free space adjustment means sets the storage capacity to the storage means. 9. The high-speed video camera according to claim 7, wherein the first mode is selected when all of the storage areas are empty. 10. The apparatus according to claim 1, wherein said general-purpose signal generation means includes a D / A conversion means for converting said digital image data into an analog video signal compatible with said composite video signal. A high-speed video camera according to any of the above. 11. The apparatus according to claim 1, wherein said general-purpose signal generating means includes digital video signal generating means for converting said digital image data into a digital video signal compatible with said composite video signal. A high-speed video camera according to any of the above.