JP2001101900A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the number of processes of a memory integrated circuit on which logics are mixedly loaded and the like incorporated in plural DRAM macro-cells DRAM0-DRAM7 without increasing the manufacturing cost and obstructing its high speed operation and to improve the accuracy of test. SOLUTION: An individual identification numbers are given to DRAM marco- cells DRAM0-DRAM7 incorporated in a memory integrated circuit loading logics mixedly and the like, while a DFT circuit of each DRAM marco-cell is provided with a function recognizing an identification number given to a corresponding DRAM marco-cell based on marco-cells identification signals TDID0-TDID2, and a function in which a row address strobe signal RASN and a column address strobe signal CASN being a start control signal are selectively taken in a marco-cell, keeping a marco-cell active signal TMATMT selectively to a valid level, or fixing it substantially to an invalid level.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly, to a semiconductor integrated circuit device having a plurality of DRAM macrocells each having a DFT circuit and a logic embedded memory integrated circuit. It concerns particularly effective technologies.

[0002]

2. Description of the Related Art Information storage capacitor and address selection M
A basic structure of a memory array in which dynamic memory cells each including an OSFET (metal oxide semiconductor type field effect transistor; in this specification, a MOSFET is generally referred to as an insulated gate type field effect transistor) is arranged in a lattice. Dynamic RAM as an element
(Random access memory). In addition, a logic unit including a gate array and the like, and a dynamic RAM
There is a semiconductor integrated circuit device of a logic embedded memory integrated circuit in which a plurality of DRAM macrocells each having a basic component are mounted.

On the other hand, as one means for increasing the efficiency of functional tests of dynamic RAMs and the like which are increasing in capacity and shortening the TAT (Turn Around Time) at the time of their development, DFT (Design Forecast) has been proposed.
Test) technology, and a dynamic RAM or the like incorporating a DFT circuit is being studied.

[0004]

Prior to the present invention, the present inventors engaged in the development of a logic-mixed memory integrated circuit having a plurality of DRAM macrocells having a DFT circuit, and noticed the following problems. . In other words, as shown in FIG.
DRAM macro cells DRAM0 to DRAM7 are provided, and each DRAM macrocell is provided with a DFT circuit (DFT). DRAM macro cells DRAM0 to DRAM7
Is a row address strobe signal RASN which is an output signal of the logic unit LC (here, for a so-called inverted signal which is selectively set to a low level when it is made valid,
The name is indicated by adding N to the end. Further, for example, an inverted internal signal such as an internal row address strobe signal rasn generated based on the row address strobe signal RASN is denoted by n. The same applies to the following) or the column address strobe signal CASN is set to the low level to selectively and simultaneously select eight pieces, thereby executing access to the specified address.

As the technology for miniaturization and high integration of integrated circuits advances, the above-mentioned logic-mixed memory integrated circuit is also increasing in size and capacity, and the number of required chip terminals (pins) is correspondingly increased. It is getting. As is well known, the increase in the number of chip terminals increases the chip size of a logic-mixed memory integrated circuit or the like, and hinders cost reduction.

[0006] On the other hand, as the scale and capacity of a logic-mixed memory integrated circuit and the like increase, it becomes necessary to more efficiently and accurately perform functional tests on a plurality of DRAM macrocells and the like to be mounted. It is an essential condition that each DRAM macro cell can be individually accessed and tested. However, a DRAM mounted on a conventional DRAM macrocell
Since the FT circuit is used for testing a dynamic RAM or the like originally formed as a single unit, it does not have an individual identification function.

In the above-mentioned logic-mixed memory integrated circuit,
At the time of normal access, eight DRAM macro cells are simultaneously selected. To test each DRAM macro cell individually, as shown in FIG.
The test row address strobe signals TRAS0N to TRAS7N for testing and the test column address strobe signals TCAS0N to TC correspond to the M macro cells.
A chip terminal for inputting AS7N is added, and these test row address strobe signal and test column address strobe signal or the row address strobe signal RASN and column address strobe signal CASN generated by the logic unit LC are added to the DRAM macro cells DRAM0 to DRAM7. MXR0-MXR7 and MXC0-MX for selectively transmitting to
C7 is required.

However, the addition of a new chip terminal increases the chip size of the logic embedded memory integrated circuit, as described above, and causes an increase in cost. In addition, the multiplexers MXR0 to MXR7 and MXC0 to MXC
7 are added at start-up control signals that regulate the operation speed of the logic-mixed memory integrated circuit, that is, the row address strobe signal RASN and the column address strobe signal C.
Since this corresponds to the signal path of the ASN, the number of logic stages in the signal path increases by several steps, and the high-speed operation of the logic embedded memory integrated circuit aiming at, for example, several hundred MHz (megahertz) is restricted.

An object of the present invention is to provide means for efficiently and accurately testing a plurality of DRAM macrocells and the like mounted on a logic embedded memory integrated circuit and the like. Another object of the present invention is to reduce the number of test steps for a logic embedded memory integrated circuit having a plurality of DRAM macrocells without increasing the cost and without hindering the high-speed operation, thereby improving the test accuracy. To increase.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0011]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, in a logic-mixed memory integrated circuit or the like in which a plurality of DRAM macro cells each having a DFT circuit are mounted, an individual identification number is assigned to each DRAM macro cell, and the DF of each DRAM macro cell is assigned.
For example, a function of recognizing an identification number given to a corresponding macro cell based on a macro cell identification signal input at a fixed level to the T circuit, and a function of D input as a DFT signal
When a corresponding macro cell is designated by the FT entry signal, the corresponding macro cell active signal is selectively set to an effective level, and a row address strobe signal and a column address strobe signal serving as an activation control signal are taken into the macro cell. Is not specified, the macro cell active signal is set to the invalid level, and the function of fixing the row address strobe signal and the column address strobe signal to the substantially invalid level is provided.

According to the above-mentioned means, the logic-embedded memory can be implemented without adding a new chip terminal to the logic-embedded memory integrated circuit or the like, and without adding a circuit such as a multiplexer to a signal path that regulates the operation time. A functional test of a DRAM macro cell etc. mounted on an integrated circuit
The DFT circuit incorporated in the RAM macro cell or the like can be implemented individually and efficiently. As a result, the cost increases and the plurality of DRs can be
It is possible to reduce the number of test steps for a logic embedded memory integrated circuit or the like on which an AM macro cell is mounted, and to improve the test accuracy.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a board layout of an embodiment of a logic embedded memory integrated circuit (semiconductor integrated circuit device) to which the present invention is applied. First, an outline of a block configuration and a board arrangement of the logic-mixed memory integrated circuit of this embodiment will be described with reference to FIG. The logic-mixed memory integrated circuit of this embodiment is not particularly limited, but is mounted on a predetermined board of a computer system capable of operating at a high speed of, for example, several hundred megahertz machine cycles, and constitutes, for example, its cache memory. Further, in the following description regarding the substrate arrangement of the logic-mixed memory integrated circuit, FIG.
Represents the top, bottom, left and right on the semiconductor substrate CHIP surface.

In FIG. 1, although the logic embedded memory integrated circuit of this embodiment is not particularly limited, the semiconductor substrate CHIP
DRAM macro cells D arranged along the upper side of
RAM0 to DRAM3, and four DRAM macrocells DRAM4 to DRAM7 arranged along the lower side. As will be described later, these DRAM macrocells each include a DFT circuit (DFT) serving as a test circuit, and have a storage capacity of, for example, 64 KW (kiloword) × 292b (bit).

The logic-mixed memory integrated circuit further includes
8 S arranged inside the RAM macro cell
It includes RAM macro cells SRAM0 to SRAM7 and another SRAM macro cell SRAM8 arranged at the center of the semiconductor substrate CHIP. SRAM macro cell S
RAM0 to SRAM3 and SRAM4 to SRAM7
Inside, a number of input / output cells IOC are arranged in a row along a horizontal center line of the semiconductor substrate CHIP, and between these input / output cells IOC and the SRAM macro cell,
A logic unit LC including a number of gate arrays (not shown) and bumps BUMP corresponding to chip terminals is arranged. Needless to say, the bump BUMP is connected to each input / output cell IOC.
It is also placed inside. In addition, the gate arrays of the logic unit LC are combined based on user specifications to form a predetermined logic circuit.

FIG. 2 is a block diagram showing one embodiment of a DRAM macro cell mounted on the logic-integrated memory integrated circuit of FIG. Based on the drawing, DRAM macro cells DRAM0 to DR mounted on a logic embedded memory integrated circuit
An outline of the configuration and operation of the AM 7 will be described. In addition,
All the DRAM macro cells DRAM0 to DRAM7 have the same configuration except that assigned identification numbers are different.

In FIG. 2, a DRAM macro cell has a memory array MARY arranged so as to occupy most of the required layout area as its basic component. The memory array MARY includes, but is not limited to, substantially 4,096 word lines arranged in parallel in the horizontal direction of the figure and substantially 1,168 sets of complementary bits arranged in parallel in the vertical direction of the figure. Including lines. At the intersections of these word lines and complementary bit lines, a total of 19,136,512 dynamic memory cells each including an information storage capacitor and an address selection MOSFET are arranged in a grid.

A word line constituting the memory array MARY is coupled to a row address decoder RD on the left side of the drawing, and is alternatively set to a high level selection level. The row address decoder RD includes a row address buffer RB.
Supplies a 12-bit internal row address signal (not shown). The row address buffer RB has a 12-bit row address RA0-RAB (here, for example, a row address or the like having more than ten additional addresses) from an access unit (not shown) of the logic-mixed memory integrated circuit via macro cell input terminals RA0-RAB. The number may be represented by an alphabet. The same applies hereinafter). Further, the input buffer IB is connected to the macro cell input terminal CLKN.
1, the clock signal CLKN, that is, the internal clock signal clkn, is supplied, the scan-in data SID, that is, the internal scan-in data sid is supplied from the macro cell input terminal SID, and the scan is performed from the macro cell input terminal SCK via the input buffer IB2. The clock signal SCK, that is, the internal scan clock signal sc
k is supplied.

The internal clock signal clkn and the internal scan clock signal sck are supplied to an output data latch OL, an input data latch IL, a column address buffer CB, a control signal buffer SB, a DFT signal buffer DB, and a macro cell active signal buffer TB, which will be described later. Supplied in common. In addition, internal scan-in data si
d is connected in a manner that the scan-in terminal and scan-out terminal of the flip-flops constituting these buffers are chain-coupled, and constitutes a scan path for test diagnosis. The end of the scan path is connected to a macro cell output terminal SOD, which will be described later, and scan-out data S
OD. The configuration of each buffer, the scan path, its use, and the like will be described later in detail.

When a DRAM macro cell is selected in a normal access mode, the row address buffer RB receives a signal from a macro cell input terminal R from a preceding access unit.
Row addresses RA0 input through A0-RAB
RAB is taken according to the internal clock signal clkn,
In addition to the holding, based on these row addresses, an internal row address signal composed of a non-inverted signal and an inverted signal is generated and supplied to the row address decoder RD. When the DRAM macro cell is selected in a predetermined test mode, the macro cell input terminal SID
The scan-in data SID input serially from the device is sequentially taken in according to the internal scan clock signal sck, shifted, and transmitted to the output data latch OL.

The row address decoder RD decodes a 12-bit internal row address signal supplied from the row address buffer RB, and selectively sets a corresponding word line of the memory array MARY to a high selection level. Thereby, substantially 1, 1 coupled to the selected word line
The minute read signals of the 68 memory cells are output to the corresponding complementary bit lines, and are converted into high-level or low-level binary read signals by a sense amplifier (not shown) of the memory array MARY.

Next, the complementary bit lines forming the memory array MARY are connected to the main amplifier MA and the write amplifier WA at the bottom of the figure. The main amplifier MA and the write amplifier WA are not particularly limited.
A 16-bit read or write bit line selection signal (not shown) is supplied from the column address decoder CD. The read data of a total of 292 bits output from the main amplifier MA are divided into four groups of 72 bits each and supplied to the output data latch OL. The write amplifier WA receives the input data latch I
Write data is supplied from L in units of 72 bits.
The column address decoder CD is supplied with a 4-bit internal column address signal from a column address buffer CB, and the column address buffer CB is supplied with 4-bit column addresses CA0 to CA3 via macro cell input terminals CA0 to CA3. You.

As described above, the internal clock signal clkn, the internal scan-in data sid, and the internal scan clock signal sck are supplied to the output data latch OL, the input data latch IL, and the column address buffer CB.
Is supplied. Further, the read data of 292 bits in total held by the output data latch OL is supplied to the multiplexer MX while being divided into groups of 73 bits, and the multiplexer MX is connected to the multiplexer MX via the macro cell input terminals MS0 to MS3. Output selection signal M
S0 to MS3 are supplied. The 73-bit read data selected by the multiplexer MX is supplied to one input terminal of the output selector OS. Output selector O
The other input terminal of S is supplied with 73-bit write data held by an input data latch IL, and its control terminal is supplied with a test output control signal DWMC via a macro cell input terminal DWMC.

Note that the test output control signal DWMC is DR
When the AM macro cell is set to the normal read or write mode, it is set to the low level invalid level, and when set to the predetermined test mode, it is set to the high level valid level. The write amplifier WA has internal write enable signals we0n-w (not shown) generated based on 4-bit write enable signals WE0N-WE3N input via the macro cell input terminals WE0N-WE3N.
e3n is supplied.

The column address buffer CB captures and holds the column addresses CA0 to CA3 input via the macro cell input terminals CA0 to CA3 in accordance with the internal clock signal clkn, and respectively non-inverts based on these column addresses. And an internal column address signal comprising an inverted signal and an inverted signal. The column address decoder CD decodes the internal column address signal supplied from the column address buffer CB, and outputs a read bit line selection signal to the main amplifier MA or a write amplifier WA.
Is alternatively set to a high-level selection level.

The main amplifier MA is connected to the selected word line of the memory array MARY when the DRAM macro cell is selected in the normal read mode.
Read signals output from the eight memory cells via the corresponding complementary bit lines are selected and amplified 288 bits at a time in accordance with the read bit line select signal, and transmitted to the output data latch OL. At this time, the output data latch O
L captures and holds the read data output from the main amplifier MA according to the internal clock signal clkn, divides the read data into four groups of 72 bits each, and transmits the groups to the multiplexer MX. Multiplexer M
X selects 72 bits of read data transmitted from the main amplifier MA according to the output selection signals MS0 to MS3, and transmits the selected data to the output selector OS. Output selector OS
Receives the low level of the test output control signal DWMC, selects 72-bit read data transmitted from the multiplexer MX, and selects the macro cell output terminals DO0 to DO71.
Output via.

On the other hand, the input data latch IL is
When the macro cell is selected by a normal write MOSFET, 72-bit write data input from an external access unit via the macro cell input terminals WD0 to WD71 is captured and held in accordance with the internal clock signal clkn, and written. The signal is transmitted to 72 unit write amplifiers specified by the write bit line selection signal among the 288 unit write amplifiers constituting the amplifier WA. At this time, each unit write amplifier of the write amplifier WA outputs the internal write enable signal we0n.
Ｗwe3n are selectively activated in response to the high levels of 72 to 72, each holding 72 bits, for a total of 28
The 8-bit write data is written to 72 to 288 memory cells coupled to the selected word line of the memory array MARY.

The DRAM macro cell further includes a memory control circuit CTL and a DFT circuit (DFT), a control signal buffer SB, a DFT signal buffer DB, and a macro cell active signal buffer TB. this house,
The control signal buffer SB has a macro cell input terminal RAS
N, CASN, RESN (and input buffer IB4) and WE0N to WE3N, a row address strobe signal RASN, a column address strobe signal CASN, and a reset control signal RESN serving as start-up control signals.
In addition, the write enable signals WE0N to WE3N are supplied, and the internal macrocell active signal tment is supplied from the DFT circuit. Further, the memory control circuit CTL receives, from the control signal buffer SB, an internal row address strobe signal rasn, an internal column address strobe signal casn, an internal reset control signal resn, and an internal write enable signal we0n. We3n are supplied.

On the other hand, the DFT signal buffer DB has a DFT signal via macro cell input terminals TDMS0 to TDMS5.
6-bit DFT entry signal TDM as part of signal
S0 to TDMS5 are supplied, and macro cell identification signals TDID0 to TDID2 and a DFT clock signal TDCKN are supplied via macro cell input terminals TDID0 to TDID2 and TDCKN. Further, the DFT circuit includes the DFT entry signals TDMS0 to TDMS5, macro cell identification signals TDID0 to TDID2, and DF via the DFT signal buffer DB.
The T clock signal TDMCKN is supplied, and the macro cell active signal buffer TB is supplied with the internal macro cell active signal tmaent from the DFT circuit.

Control signal buffer SB, DFT signal buffer DB and macro cell active signal buffer TB
Is supplied with the internal clock signal clkn, the internal scan-in data sid, and the internal scan clock signal sck, as described above. Also, the internal macro cell active signal tmaint generated by the DFT circuit
Is an output buffer OB1 and a macro cell output terminal TMA.
After passing through ENT, the macro cell active signal TMAEN
The scan-out output signal SOD of the macro cell active signal buffer TB is output to the outside as T, and the macro cell output terminal SOD is output as scan-out data SOD.
Output from

The control signal buffer SB is supplied from an external access unit to macro cell input terminals RASN, CASN,
RESN (and input buffer IB4) and WE0N
To WE3N, the row address strobe signal RASN and the column address strobe signal CAS
N, the reset control signal RESN and the write enable signals WE0N to WE3N to the internal clock signal clkn.
And the internal row address strobe signal ras based on these activation control signals.
n, an internal column address strobe signal casn, an internal reset control signal resn, and internal write enable signals we0n-we3n, and supply them to the memory control circuit CTL. Note that the internal write enable signal w
e0n to we3n are write amplifiers WA as described above.
Is also supplied.

The memory control circuit CTL includes an internal row address strobe signal rasn and an internal column address strobe signal cas supplied from the control signal buffer SB.
n, the internal reset control signal resn, and the internal write enable signals we0n to we3n.
The operation mode of the macro cell is identified, an internal control signal (not shown) is selectively generated, and supplied to each section of the DRAM macro cell.

On the other hand, the DFT signal buffer DB, for example, during a probe test of the logic embedded memory integrated circuit performed in a wafer state, is provided from an external tester to the logic part LC of the logic embedded memory integrated circuit and the DFT signal buffer D.
B, the DFT entry signals TDMS0 to TDMS5 and the macro cell identification signals TDID0 to TDID2 are input to the DFT clock signal T
The data is captured according to DMCKN and transmitted to the DFT circuit.
Further, the DFT circuit performs a predetermined test operation based on these DFT signals, and reports the result to an external test device.

In this embodiment, eight DRAM macrocells DRAM0 mounted on a logic embedded memory integrated circuit are provided.
ＤＲＡＭDRAM7 are respectively assigned identification numbers of 0 to 7 corresponding to the serial numbers, and macro cell input terminals TDID0 to TDID2 of each DRAM macro cell correspond to the binary value of the identification number given to the corresponding DRAM macro cell. Then, it is selectively coupled to the power supply voltage supply point VDD or the ground potential supply point GND. In the test mode specified by DFT entry signals TDMS0 to TDMS5, DRAM macro cells DRAM0 to DRAM7
Is selectively activated, whereby a functional test can be individually performed while designating a specific DRAM macro cell. A specific configuration of the control signal buffer SB and the DFT signal buffer DB, a test mode of the DFT circuit, a method of specifying the test mode, and the like will be described later in detail.

FIG. 3 is a circuit diagram showing one embodiment of the control signal buffer SB included in the DRAM macro cell of FIG. The specific configuration and operation of the control signal buffer SB of the DRAM macro cell of this embodiment will be described with reference to FIG.

In FIG. 3, the control signal buffer SB includes:
Although not particularly limited, macro cell input terminals RASN, C
A total of seven flip-flops FF1 to FF provided corresponding to ASN, RESN and WE0N to WE3N
7 inclusive. These flip-flops are both edge-triggered, and have their clock input terminals CKN and SC
The internal clock signal clkn and the internal scan clock signal sck are commonly supplied to K. The reset input terminals RESN of the six flip-flops FF1 to FF2 and FF4 to FF7 excluding the flip-flop FF3 are connected to the internal reset control signal r from the macro cell input terminal RESN via the input buffer IB4.
esn is commonly supplied. Further, the scan-in terminal SID and the scan-out terminal SOD of the flip-flops FF1 to FF7 are sequentially chain-coupled, thereby forming a scan path for test diagnosis.

The data input terminals IN of the flip-flops FF1 and FF2 constituting the control signal buffer SB are
Output signals of OR gates OG1 and OG2 are supplied, respectively, and a non-inverted output signal at a data output terminal DOUT is an internal row address strobe signal ra.
It is supplied to the subsequent memory control circuit CTL as sn or an internal column address strobe signal casn. One input terminal of each of the OR gates OG1 and OG2 is coupled to a corresponding macro cell input terminal RASN or CASN, respectively, and the other input terminal is commonly supplied with an inverted signal of the internal macro cell active signal tmaint by an inverter V1. .

Thus, the OR gates OG1 and OG2
Is an internal macrocell active signal tmae.
nt is set to a valid level, that is, a high level, and the corresponding row address strobe signal RASN or column address strobe signal CASN is set to a valid level, that is, a low level. In other words, the output signals of the OR gates OG1 and OG2 are fixed to the high level when the internal macrocell active signal tmaint is at the invalid level, that is, the low level, regardless of the logical level of the row address strobe signal RASN or the column address strobe signal CASN. At this time, the row address strobe signal RASN or the column address strobe signal CAS
N has a form that is fixed to a substantially invalid level, that is, a high level.

The high level and low level of the output signals of the OR gates OG1 and OG2 are not particularly limited. , Internal row address strobe signal rasn or internal column address strobe signal casn. The conditions for generating the internal macro cell active signal tmaint will be described later.

As is well known, a row address strobe signal RASN and a column address strobe signal CASN
Is a start control signal for selectively bringing a dynamic RAM, which is a basic component of the DRAM macro cell, into an operating state. The memory control circuit CTL at the subsequent stage is configured to control the internal row address strobe signal rasn and the internal column address strobe signal. The DRAM macro cell is selectively activated in response to the low level of casn. When the internal macro cell active signal tmain is set to the low level, the DRAM macro cell performs row address strobe signal RASN and column address strobe signal CASN.
Irrespective of the logic level of, the access from the access unit or the test apparatus is not accepted.

Next, the reset control signal RESN is supplied to the data input / output terminal IN of the flip-flop FF3 constituting the control signal buffer SB via the input buffer IB4, and the data output terminal OUT is opened. . The output signal of the input buffer IB4 is used as it is as the internal reset control signal resn,
It is supplied to each buffer while being supplied to the TL.

That is, the flip-flop FF3 is not for synchronizing the corresponding reset control signal RESN with the internal clock signal clkn like the above-mentioned flip-flops FF1 and FF2, but for the reset control signal REFF.
The SN is taken into the scan path and used for test diagnosis of the DRAM macro cell.

On the other hand, the data input / output terminals IN of the flip-flops FF4 to FF7 forming the control signal buffer SB
Are the corresponding write enable signals WE0N to WE3N
, And the non-inverted output signals at the data output terminal OUT are the internal write enable signals we0n to we3n, respectively. These internal write enable signals we0n to we3n are supplied to a subsequent memory cell control circuit CTL, and the write amplifier WA
Is also supplied.

FIG. 4 is a partial circuit diagram of one embodiment of the DFT signal buffer DB and related parts included in the DRAM macro cell of FIG. The specific configuration and operation of the DFT signal buffer DB and the macro cell active signal buffer TB of the DRAM macro cell of this embodiment will be described with reference to FIG.

In FIG. 4, DFT signal buffer DB
Is not particularly limited, but the macro cell input terminal TDMS
0 to TDMS5, TDID0 to TDID2 and TD
The macro cell active signal buffer TB includes ten edge trigger type flip-flops FF21 provided corresponding to the MCKN, and the edge trigger type flip-flop FF21 provided corresponding to the macro cell output terminal TMAENT. Including. These flip-flops, like the flip-flop FF3, are used only at the time of test diagnosis using a scan path and do not include a reset input terminal. The clock input terminals CKN and SCK have internal clock signals cl
kn and the internal scan clock signal sck are supplied in common, and their scan-in terminal SID and scan-out terminal SOD are sequentially chain-coupled to form a scan path for test diagnosis.

Data input terminal IN of flip-flops FF11-FF20 constituting DFT signal buffer DB
Are the corresponding macro cell input terminals TDMS0 to TDMS
5, TDID0 to TDID2 or TDMCKN, respectively, and all the data output terminals OUT are open. Therefore, DFT entry signals TDMS0-TDMS5, macro cell identification signal TDID
0 to TDID2 and DFT clock signal TDMCK
N is transmitted directly to the subsequent DFT circuit without passing through the corresponding flip-flop of the DFT signal buffer DB. Note that the DFT clock signal TDMCKN is also supplied to the clock input terminal SCK of the flip-flop constituting each buffer as described above.

On the other hand, the data input terminal IN of the flip-flop FF21 forming the macro cell active signal buffer TB is supplied with the internal macro cell active signal tment from the logic unit LC, and its data output terminal O
The UT is in an open state. The internal macro cell active signal tmaint is further supplied directly to the input terminal of the output buffer OB1, and is output from the macro cell output terminal TMAENT to the test apparatus as the macro cell active signal TMAENT.

In the logic integrated memory integrated circuit of this embodiment, as will be described later, a DRAM macro cell DRAM
0 to 7 corresponding to the serial number of the DRAM 7
And the macro cell input terminals TDID0 to TDID2 of each DRAM macro cell are selectively coupled to the power supply voltage supply point VDD or the ground potential supply point GND in a combination corresponding to the logical value of the identification number. .

The DFT circuit of each DRAM macro cell generates a corresponding D based on macro cell input terminals TDID0 to TDID2, that is, macro cell identification signals TDID0 to TDID2 input via these macro cell input terminals.
The identification number given to the RAM macro cell is recognized. Then, the logic embedded memory integrated circuit is set to a predetermined test mode, and DFT entry signals TDMS0 to TDMS are set.
When the identification number of the corresponding DRAM macro cell is designated by 5 predetermined bits, the function test can be individually performed for the corresponding DRAM macro cell.

On the other hand, the DFT circuit of each DRAM macro cell sets the internal macro cell active signal tmain, which is the output signal thereof, to a low level when the logic-mixed memory integrated circuit is set to the normal operation mode, and receives this signal at the macro cell output terminal TMAENT. Outputs a low-level macro cell active signal TMAENT. When the logic-mixed memory integrated circuit is set to a predetermined test mode and the DFT entry signals TDMS0 to TDMS5 specify the corresponding DRAM macrocell identification number, the internal macrocell active signal tmain is selectively set to a high level. In response to this, a high-level macro cell active signal TMAENT is output to the macro cell output terminal TMAENT. At this time, other DRAMs are supplied by DFT entry signals TDMS0 to TDMS5.
When the identification number of the macro cell is designated, the internal macro cell active signal tmain, that is, the macro cell active signal TMAENT is kept at the low level.

As shown in FIG. 3, when the macro cell active signal TMAENT is set to the high level, the row address strobe signal RA supplied from the logic unit LC is output.
The SN and the column address strobe signal CASN are directly used as the internal row address strobe signal rasn or the internal column address strobe signal casn.
The signal is transmitted to the memory control circuit CTL of the AM macro cell, and each DRAM macro cell is selectively activated in response to the low level. Also, the macro cell active signal T
When MAENT is at a low level, the row address strobe signal RASN and the column address strobe signal CASN are substantially fixed at a high level, and each DRA is
The M macro cell is fixed in a non-operation state.

FIG. 5 shows DRAM macro cells DRAM0 to DRAM7 included in the logic-mixed memory integrated circuit of FIG.
1 is a connection diagram of the first embodiment. FIG. 6 shows a logical condition diagram of one embodiment of the macro cell identification signals TDMS0 to TDMS5 input to the DRAM macro cells DRAM0 to DRAM7, and FIG. 7 shows an embodiment of the DFT entry signals TDID0 to TDID2. A partial logic condition diagram is shown. Based on these figures, the connection form of the DRAM macro cells DRAM0 to DRAM7, the logical conditions of the DFT entry signals TDMS0 to TDMS5 and the macrocell identification signals TDID0 to TDID2 and the outline of the test operation and The features and the like will be described. FIG. 5 shows a plurality of macro cell input terminals and macro cell output terminals provided in each DRAM macro cell.
Only those relevant to the present invention have been illustrated.

In FIG. 5, the DRAM macro cell DRA
Macro cell input terminals RASN and C of M0 to DRAM7
The row address strobe signal RASN and the column address strobe signal CASN are commonly supplied to the ASN from the logic unit LC of the logic-mixed memory integrated circuit. As is well known, the row address strobe signal RAS
N and the column address strobe signal CASN are DR
This is a start control signal for selectively bringing a dynamic RAM, which is a basic component of the AM macro cells DRAM0 to DRAM7, into an operating state. Therefore, all DR
Row address strobe signal R common to AM macro cells
In the logic-mixed memory integrated circuit of the present embodiment to which the ASN and the column address strobe signal CASN are supplied, in the normal read or write mode, the eight DRAM macro cells DRAM0 to DRAM7 are simultaneously activated or inactive. It is said.

Next, the DRAM macro cells DRAM0-D
Macro cell input terminals TDMS0 to TDMS5 of RAM7
Are respectively coupled to corresponding lower right input / output terminals of an input selector SL provided in a preceding stage of the logic unit LC. The upper right input / output terminal of the input selector SL is coupled to the logic unit LC. The left input / output terminals are respectively coupled to the corresponding chip input / output terminals PB0 to PBj, and the selection control terminal is supplied with the selection control signal PSL via the chip input / output terminal PSL. The logic-mixed memory integrated circuit further includes i + 1 chip input / output terminals PA0-P
Ai, and these chip input / output terminals are directly coupled to the logic part LC.

The input selector SL is set, for example, to a normal operation mode of the logic-mixed memory integrated circuit, and the selection control signal P
When SL is at a low level, the chip input / output terminal PB
A connection state is established between 0-PBj and the logic unit LC. When the logic-mixed memory integrated circuit is set to a predetermined test mode and the selection control signal PSL is set to a high level,
The chip input / output terminals PB0 to PBj are directly connected to the DRAM macrocells DRAM0 to DRAM7 to enable a test operation by the DFT circuit.

In this embodiment, the chip input / output terminal P
A signal input or output to the logic-mixed memory integrated circuit via A0 to PAi is a high-speed signal that regulates the operation speed of the logic-mixed memory integrated circuit, such as a clock signal or a start control signal. . However, a signal input or output via the chip input / output terminals PB0 to PBj (first signal
) Is a relatively low-speed signal that does not determine the operation speed of the logic-mixed memory integrated circuit.
Even if the substantial functions of B0 to PBj are switched by the input selector SL, there is no serious effect on the operation speed of the logic-mixed memory integrated circuit.
Since B0 to PBj are also used to input or output a large number of signals required for the operation test by the DFT circuit, the number of required terminals of the logic-mixed memory integrated circuit is reduced, and the cost is reduced.

On the other hand, DRAM macro cells DRAM0 to DRA mounted on the logic-integrated memory integrated circuit of this embodiment
As described above, M7 is assigned an identification number of 0 to 7 corresponding to the serial number, and the macro cell input terminals TDID0 to TDID2 of each DRAM macro cell are connected to the power supply voltage in a combination corresponding to the identification number. Point V
DD or ground potential supply point GND.

That is, as shown in FIG. 6, for example, a DRAM provided with an identification number of 0 corresponding to the serial number
In the macro cell DRAM0, the macro cell input terminal TDI
D0 to TDID2 are all coupled to ground potential supply point GND. Therefore, macro cell identification signals TDID0 to TDID0
Each bit of TDID2 is set to a low level, that is, logic "0", and the logic value is "0" corresponding to a binary value of 0.
00 ". For example, in the DRAM macro cell DRAM 1 to which the identification number corresponding to the serial number is given, the macro cell input terminal TDID0 is connected to the power supply voltage supply point V.
DD and another macro cell input terminal TDID
1 and TDID2 are coupled to ground potential supply point GND. Therefore, the macro cell identification signal TDID0 is set to logic "1" and the macro cell identification signals TDID1 and TDID
ID2 remains at logic "0", and its logic value becomes "001" corresponding to the binary value of 1.

On the other hand, for example, in a DRAM macro cell DRAM 7 given an identification number of 7 corresponding to the serial number,
Macro cell input terminals TDID0 to TDID2 are all coupled to power supply voltage supply point VDD. Therefore, each bit of the macro cell identification signals TDID0 to TDID2 is all set to the high level, that is, logic "1", and the logic value is 7
Becomes "111" corresponding to the binary value of.

Macro cell input terminals TDID0 to TDID
2, macro cell identification signals TDID0 to TDID0
TDID2 is the DFT signal buffer DB as described above.
To the DFT circuit of each DRAM macro cell. Further, the DFT circuit recognizes the identification number given to the corresponding DRAM macro cell based on these macro cell identification signals TDID0 to TDID2, and when the logic embedded memory integrated circuit is set to a predetermined test mode, Identification number and macro cell input terminals TDMS0-T
DFT entry signal TD input via DMS5
MS0 to TDMS5 are compared and compared, and these DFTs are compared.
When a corresponding DRAM macro cell is designated as a test target by an entry signal, an internal macro cell active signal tmain, which is an output signal thereof, is selectively set to a high level.

The DFT circuit of the DRAM macro cell according to this embodiment has a so-called concurrent function. For example, the designation of the DRAM macro cells by the DFT entry signals TDMS0 to TDMS5 is applied to a plurality of DRAM macro cells by adding them sequentially. It is possible to do. Thereby, a plurality of DRAM macro cells can be designated as a target of the function test, and the test operation can be performed in parallel.

Here, the macro cell input terminals TDMS0 to TDMS0
DFT entry signal T input via TDMS5
As illustrated in FIG. 7, DMS0 to TDMS5 are used, for example, to start or stop a function test by the DFT circuit, to selectively specify a test type, a DRAM macro cell to be tested, and the like.

That is, the DFT of each DRAM macro cell
In the circuit, as shown in the first term of FIG. 7, all of the DFT entry signals TDMS0 to TDMS5 are set to a low level, that is, logic “0”, and the logic value is “000000”.
, The DFT mode entry is determined to prepare for the start of a test operation specified thereafter. Also, as shown in the second term of FIG. 7, the DFT entry signal TDMS
When all 0 to TDMS5 are at high level, that is, logic "1", and the logic value is "111111",
The DFT mode exit is determined, and the test operation being performed is stopped. Further, as shown in the third term of FIG.
When the FT entry signal TDMS0 is set to logic "1" and the other DFT entry signals TDMS1 to TDMS5 are set to logic "0" and their logic values are set to "000001", the concurrent mode clear is determined.
Release only the above concurrent specification.

On the other hand, as shown in the fourth to eighth items of FIG. 7, the DFT entry signals TDMS0 to TDMS
The logical value of 5 is “000010” “000011” “00”
0100 "" 000101 "or" 000110 "
Then, a special test mode for shortening the test required time, for example, "2K (kilo) refresh disturb test", "1K refresh disturb test", "all mat active test", "row (row) copy" 1 "" Alternatively, it is determined that “row copy“ 0 ”” is specified, and the corresponding test operation is started.

Further, as shown in items 9 to 16 in FIG. 8, DFT entry signals TDMS0 to TDMS0 to TDMS
The logical value of MS5 is “000111” “001000”
“001001” “001010” “001011”
“001100” “001101” or “0011”
10 ", the macro cell input terminals TDID0 to TDID0
Macro cell identification signal TDID0 supplied to TDID2
TDID2, the corresponding DRAM macro cell D
It is determined that each of the RAM 0 to the DRAM 7 is alternatively specified as a test target, and the internal macro cell active signal tmain is selectively set to a high level or a low level, respectively.

As described above, the logic-mixed memory integrated circuit of this embodiment has eight DRAs each including a DFT circuit.
M macro cells DRAM0 to DRAM7 are provided, and these DRAM macrocells are assigned identification numbers 0 to 7 corresponding to the serial numbers. Each DRAM macro cell has a macro cell input terminal T
DID0 to TDID2 are provided, and these macro cell input terminals are selectively coupled to power supply voltage supply point VDD or ground potential supply point GND according to the logical value of the identification number given to the corresponding DRAM macro cell. . Further, the test mode executed by the DFT circuit of each DRAM macro cell includes the DRAM macro cells DRAM0 to DRAM0.
"DRAM0 active" to "DRAM7 active" modes for alternately designating the DRAM 7 as a test object are added.

DRAM macro cells DRAM0 to DRAM
7 has a macro cell input terminal TD
Based on the macro cell identification signals TDID0 to TDID2 input via ID0 to TDID2, the corresponding DRA
It has a function of recognizing the identification number given to the M macro cell, and further has a function of “DRAM0 active” to “DR
It has a function of receiving the “AM7 active” mode and determining that the corresponding DRAM macro cell is designated as a test target.

As a result, without adding a new chip terminal to the logic-mixed memory integrated circuit and without adding a selector or a multiplexer for a test operation to a signal path that regulates the operation time of the DRAM macro cell DRAM0, The function test of each DRAM macro cell can be individually and efficiently performed by the DFT circuit built in the DRAM 7. As a result, the cost increases and the plurality of DRs can be
It is possible to reduce the number of test steps of a logic-mixed memory integrated circuit on which an AM macro cell is mounted, and to improve the test accuracy.

The functions and effects obtained from the above embodiments are as follows. That is, (1) In a logic-mixed memory integrated circuit or the like in which a plurality of DRAM macro cells each having a DFT circuit are mounted,
A function of assigning an individual identification number to each DRAM macrocell, and recognizing the identification number given to the corresponding macrocell to the DFT circuit of each DRAM macrocell, for example, based on a macrocell identification signal input at a fixed level. When a corresponding macro cell is designated by a DFT entry signal input as a DFT signal, the corresponding macro cell active signal is set to an effective level, and a row address strobe signal and a column address strobe signal serving as an activation control signal are taken into the macro cell. , D
When the corresponding macro cell is not designated by the FT entry signal, the macro cell active signal is set to the invalid level, and the function of fixing the row address strobe signal and the column address strobe signal to the substantially invalid level is provided. The function test of the DRAM macro cell and the like can be performed without adding a new chip terminal to the DME and the like, and without adding a circuit such as a multiplexer to a signal path that regulates the operation time of each DRAM chip.
With the DFT circuit built in the RAM macro cell or the like, an effect that individual and efficient implementation can be obtained.

(2) According to the above item (1), the cost is increased and the plurality of D
An effect is obtained that the number of test steps for a logic-mixed memory integrated circuit or the like on which a RAM macrocell is mounted can be reduced. (3) According to the above item (1), an effect is obtained that the test accuracy of a logic embedded memory integrated circuit or the like can be improved.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the above embodiment, and various modifications can be made without departing from the gist of the invention. Needless to say, there is. For example, in FIG. 1, an arbitrary number of DRAM macro cells and SRAM macro cells can be mounted on the logic-mixed memory integrated circuit, and the DFT circuit can also be provided on the SRAM macro cell. Also, a logic-embedded memory integrated circuit and its DRAM macro cells DRAM0 to DR
The shape of the semiconductor substrate CHIP on which the AM 7 is formed is arbitrary, and the arrangement position and layout size of each block are also arbitrary.

In FIG. 2, DRAM macro cell DRA
The memory array MARY of the M0 to DRAM 7 can have an arbitrary number of word lines and complementary bit lines, and its storage capacity can be set arbitrarily. The number of bits of the macro cell identification signal input via the macro cell input terminals TDID0 to TDID2 of each DRAM macro cell varies according to the number of DRAM macro cells mounted on the logic-mixed memory integrated circuit. These macro cell identification signals may be given to each DRAM macro cell by, for example, previously writing in a predetermined register.
The DRAM macro cell can have an arbitrary block configuration, and a combination of an address signal and a start control signal and an effective level thereof can have any embodiment.

In FIG. 3, the flip-flops FF1 to FF7 constituting the control signal buffer SB are not required to be of the edge trigger type in particular, and the combinations and names of their terminals are not limited to various embodiments. Can be taken. In addition, the OR gates OG1 and OG2 provided in front of the flip-flops FF1 and FF2 can be replaced with other logic gates as necessary, or may be incorporated in the corresponding flip-flop. In FIG. 4, the connection switching between the macro cell input terminals TDID0 to TDID2 and the power supply voltage supply point VDD and the ground potential supply point GND can be performed in a master slice mode. The specific configuration of the control signal buffer SB, the DFT signal buffer DB, and the macro cell active signal buffer TB can take various embodiments as long as the basic logical conditions do not change.

In FIG. 5, DRAM macro cell DRA
The starting modes of the M0 to the DRAM 7 are, for example, those DRA
It can be set arbitrarily, for example, by combining four M-macro cells to be in an operating state. In addition, the logic embedded memory integrated circuit is a BIST (Build In Self).
In the case where a self-diagnosis circuit such as Test) is provided, as shown in FIG. 8, DFT entry signals TDMS0 to TDMS5, which are DFT signals, are converted to the self-diagnosis circuit BIST
May be generated. In FIG. 6, the logical conditions of the macro cell identification signals TDID0 to TDID2 can be set arbitrarily. In FIG. 7, the type of the test mode by the DFT circuit and the DFT entry signals TDMS0 to TDMS
Various embodiments can be considered for the combination of the MS5 and the like.

In the above description, the case where the invention made by the present inventor is mainly applied to a logic embedded memory integrated circuit having a plurality of DRAM macrocells, which is a field of use, has been described. However, the present invention is not limited to this. For example, the present invention can be applied to a memory integrated circuit device having only a memory macro cell such as a DRAM macro cell or a single-chip microcomputer having various digital units such as an arithmetic logic unit as a macro cell. INDUSTRIAL APPLICABILITY The present invention can be widely applied to a semiconductor integrated circuit device equipped with at least a macro cell having a DFT circuit, and a device or a system including such a semiconductor integrated circuit device.

[0076]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in a logic-mixed memory integrated circuit or the like in which a plurality of DRAM macro cells each having a DFT circuit are mounted, an individual identification number is assigned to each DRAM macro cell, and a macro cell identification signal input to the DFT circuit at, for example, a fixed level. Based on
A function for recognizing the identification number given to the corresponding macro cell, and when a corresponding macro cell is designated by a DFT entry signal input as a DFT signal, the corresponding macro cell active signal is set to an effective level, and a row that becomes a start control signal is set. An address strobe signal and a column address strobe signal are taken into a macro cell,
When the corresponding macro cell is not designated by the DFT entry signal, a function of fixing the row address strobe signal and the column address strobe signal to the substantially invalid level by setting the macro cell active signal to the invalid level is provided.

Thus, without adding a new chip terminal to a logic-mixed memory integrated circuit or the like, and without adding a circuit such as a multiplexer to a signal path that regulates the operation time, the logic-mixed memory integrated circuit is not added. The function test of the DRAM macro cell etc. mounted on the
The DFT circuit built in the macro cell or the like can be implemented individually and efficiently. As a result, it is possible to reduce the number of test steps for a logic-mixed memory integrated circuit or the like in which a plurality of DRAM macrocells are mounted, and to increase the test accuracy without increasing the cost and hindering the high-speed operation.

[Brief description of the drawings]

FIG. 1 is a board layout diagram showing an embodiment of a logic-mixed memory integrated circuit to which the present invention is applied.

FIG. 2 is a diagram illustrating a D mounted on the logic-mixed memory integrated circuit of FIG. 1;
FIG. 3 is a block diagram showing one embodiment of a RAM macro cell.

FIG. 3 is a circuit diagram showing one embodiment of a control signal buffer included in the DRAM macro cell of FIG. 2;

FIG. 4 is a partial circuit diagram showing one embodiment of a DFT signal buffer and related parts included in the DRAM macro cell of FIG. 2;

FIG. 5 is a diagram illustrating a D mounted on the logic-mixed memory integrated circuit of FIG. 1;
FIG. 3 is a connection diagram illustrating a first example of a RAM macro cell.

FIG. 6 is a logic condition diagram showing one embodiment of a macro cell identification signal input to the DRAM macro cell of FIG. 2;

FIG. 7 shows a DFT input to the DRAM macro cell of FIG.
FIG. 4 is a partial logic condition diagram showing an embodiment of an entry signal.

8 is a diagram illustrating a D mounted on the logic-mixed memory integrated circuit of FIG. 1;
FIG. 7 is a connection diagram illustrating a second embodiment of the RAM macro cell.

FIG. 9 is a connection diagram showing an example of a DRAM macro cell mounted on a logic embedded memory integrated circuit developed by the present inventors prior to the present invention.

[Explanation of symbols]

CHIP: Semiconductor substrate (chip), DRAM0-DRA
M7: DRAM macro cell, DFT: DFT circuit, SR
AM0 to SRAM7: SRAM macro cell, LC: logic unit, BUMP: bump, IOC: input / output cell. MARY
... Memory array, RD ... Row address decoder, RB ...
Row address buffer, MA: main amplifier, WA: write amplifier, CD: column address decoder, CB: column address buffer, IL: input data latch, OL
... Output data latch, MX ... Mux, OS ... Output selector, CTL ... Memory control circuit, DFT ... DFT
Circuit, SB: control signal buffer, DB: DFT signal buffer, TB: macro cell active signal buffer. CL
KN: Clock signal or its macro cell input terminal, SI
D: scan-in data or its macro cell input terminal
SCK: scan clock signal or its macro cell input terminal; RA0 to RAB: row address or its macro cell input terminal; MS0 to MS3: output selection signal or its macro cell input terminal; DWMC: test output control signal or its macro cell input terminal; DO71 ... output data or its macro cell output terminal, ID0 to ID71 ... input data or its macrocell input terminal, CA0 to CA3 ...
Column address or its macro cell input terminal, RASN
... a row address strobe signal or its macro cell input terminal, CASN ... a column address strobe signal or its macro cell input terminal, RESN ... a reset control signal or its macro cell input terminal, WE0N to WE3N ... a write enable signal or its macro cell input terminal, TDM
S0-TDMS5 ... DFT entry signal or its macro cell input terminal, TDID0-TDID2 ... macro cell identification signal or its macro cell input terminal, TDMCKN ...
DFT clock signal or its macro cell input terminal, TM
AENT: macro cell active signal or its macro cell output terminal; SOD: scan out data or its macro cell output terminal. clkn: internal clock signal, sc
k: internal scan clock signal, resn: internal reset control signal, tmain: internal macro cell active signal, sid: internal scan-in data, sod: internal scan-out data, rasn: internal row address strobe signal, casn: internal column address strobe signal , We0n to we3n ... internal write enable signals. VDD: power supply voltage or its supply point, GND: ground potential or its supply point. IB1 to IB4 ... input buffer, O
B1: output buffer, FF1 to FF7, FF11 to FF
21: Edge trigger flip-flop, V1: Inverter, OG1 to OG2: OR gate. PA0
PAi, PB0 to PBj: chip input / output signal or chip input / output terminal, PSL: selection control signal or its chip input terminal, SL: input selector, BIST: self-diagnosis circuit,
TRAS0N to TRAS7N: test row address strobe signal or its chip input terminal, TCAS0N to TCAS0N
CAS7N: Test column address strobe signal or its chip input terminal, MXR0 to MXR7, MXC0
MXC7: Multiplexer.

Continued on the front page (72) Inventor Yosuke Tanaka 3-16-1, Shinmachi, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. (72) Masahiro Katayama 5-2-1, Josuihoncho, Kodaira-shi, Tokyo F-term (reference) 2G032 AA07 AB01 AK11 AK14 5B024 AA15 BA21 BA29 CA07 CA16 EA01 5L106 AA01 AA15 DD12 GG05 GG07 9A001 BB03 BB05 JJ49 KK31 LL06

Claims (7)

[Claims] 1. A plurality of macrocells each comprising a test circuit for recognizing an identification number given to a corresponding macrocell and selectively performing a function test on the corresponding macrocell by designating the identification number. A semiconductor integrated circuit device characterized by comprising: 2. The test circuit according to claim 1, wherein the test circuit comprises a DFT circuit, and the DFT circuit recognizes the identification number given to a corresponding macro cell by a combination of macro cell identification codes, A semiconductor integrated circuit device for determining, by a combination of DFT entry signals, that the identification number of a corresponding macro cell has been designated. 3. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is a logic integrated memory integrated circuit, and each of the macro cells is a DRAM macro cell having a dynamic RAM as a basic component. A semiconductor integrated circuit device characterized by the above-mentioned. 4. The macro cell identification code according to claim 1, wherein each bit of the macro cell identification code is selected by connecting a corresponding input terminal of the macro cell to a power supply voltage supply point or a ground potential supply point. A semiconductor integrated circuit device which is set to a high level or a low level. 5. The DFT signal according to claim 1, wherein the DFT signal including the DFT entry signal is a first signal that does not determine the operation time of the semiconductor integrated circuit device. Or input or output to the semiconductor integrated circuit device via an output input terminal or output terminal, wherein the semiconductor integrated circuit device is configured to output the first signal or the DFT according to a predetermined selection control signal. A semiconductor integrated circuit device comprising an input selector for selectively transmitting a signal. 6. The semiconductor integrated circuit device according to claim 1, further comprising a self-diagnosis circuit, wherein the DFT signal including the DFT entry signal is: A semiconductor integrated circuit device generated by the self-diagnosis circuit. 7. The macro cell according to claim 1, wherein each of the macro cells is selected by setting a predetermined activation control signal to a valid level. The DFT circuit sets the macro cell active signal to a valid level when the identification number of the corresponding macro cell is specified by the DFT entry signal, and sets the macro cell active signal to an invalid level when not specified. Wherein the activation control signal is taken into a corresponding macro cell when the macro cell active signal is set to a valid level, and is fixed to a substantially invalid level when the macro cell active signal is set to an invalid level. Integrated circuit device.