JP2001094413A - Signal processing cell and signal processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a signal processing cell with a simple configuration that can conduct complicated processing at a high-speed and to provide a signal processor. SOLUTION: A program cell 2 processes an externally input signal A and a feedback input signal O according to a processing procedure decided by given program data and obtains an output D. The program data are so constructed as to be changeable in real time. An output latch section 84 is provided with a plurality of latch circuits LT, LT, etc., to latch a plurality of outputs D outputted from the program cell 2 in different timing. Either one of outputs D among the outputs D latched by the latch circuits LT, LT, etc., becomes the feedback input signal O to the program cell 2 via a feedback line FBL. Thus, the single program cell 2 can conduct complicated consecutive processing at a high-speed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing cell and the like, and more particularly, to a technique for performing complicated processing using a signal processing cell.

[0002]

2. Description of the Related Art A microcomputer is used for controlling industrial machines and home electric appliances. If a microcomputer is used, complicated sequence control can be realized.

[0003]

However, the conventional sequence control using the microcomputer as described above has the following problems. Since the microcomputer is a Neumann computer, it cannot essentially perform simultaneous parallel processing. Therefore, it is not suitable for high-speed processing.

To solve such a problem, a control system using a large number of CPUs can be considered, but such a control system is expensive and the signal processing becomes complicated.

The present invention solves such a problem,
An object of the present invention is to provide a signal processing cell and a signal processing device having a simple configuration capable of performing complicated processing at high speed.

[0006]

Means for Solving the Problems, Functions and Effects of the Invention
The signal processing cell according to claim 1 is configured so that a processing procedure in the combinational circuit unit is dynamically programmable, and an output latch unit that latches a signal output from the combinational circuit unit and an output latch unit. And a feedback unit for feeding back the signal for use as the processed signal of the combinational circuit unit.

Therefore, by continuously changing the processing procedure in the combination circuit section in real time while returning the signal output from the combination circuit section to the combination circuit section, continuous and complicated processing can be realized in one combination circuit section. can do. Also, by providing a large number of processed signals to be input to the combinational circuit, simultaneous parallel processing becomes possible. That is, complicated processing can be performed at high speed with a simple configuration.

According to a second aspect of the present invention, the signal processing cell includes an output latch section having a plurality of latch circuits for latching a plurality of signals output from the combinational circuit section at different timings.

Therefore, a desired signal among a plurality of latched signals can be output as required. Therefore, it is possible to restart the processing from an arbitrary point in time or to jump to an arbitrary processing in a series of processing. Also, by providing a large number of processed signals to be input to the combinational circuit, simultaneous parallel processing becomes possible. That is, complicated processing can be performed at high speed with a simple configuration.

In the signal processing cell according to the third aspect, a feedback unit is provided for feeding back a signal selected from the plurality of signals latched by the plurality of latch circuits so as to use the selected signal as the processed signal of the combinational circuit unit. It is characterized by the following.

Therefore, a desired signal of the plurality of latched signals can be fed back to the combinational circuit unit as needed. Therefore, more complicated processing can be performed at high speed with a simple configuration.

According to a fourth aspect of the present invention, in the signal processing cell, a processing procedure in the combinational circuit section is dynamically programmable.

Therefore, by changing the processing procedure in the combinational circuit section in real time, continuous complicated processing can be realized in one combinational circuit section.
For this reason, even more complicated processing can be performed at high speed with a simple configuration.

According to a fifth aspect of the present invention, in the signal processing cell, the output latch section is configured using a nonvolatile memory element.
It is characterized by.

Therefore, even when the power is cut off,
Processing results can be stored. Therefore, even if the power is shut off due to some accident, the data can be promptly returned to the state before the power was shut down. In addition, when the signal processing cell is not used, the power of the signal processing cell is turned off, and when the signal processing cell is used, the power of the signal processing cell is controlled to be turned on to save power. Can be achieved.

According to a sixth aspect of the present invention, in the signal processing cell, the combinational circuit unit is configured using a nonvolatile memory element.
It is characterized by.

Therefore, even when the power is turned off,
The processing procedure can be stored. Therefore, even if the power is shut off due to some kind of accident, it is possible to quickly return to the processing procedure before the power was shut down. When the signal processing cell is not used, the power of the signal processing cell is turned off, and when the signal processing cell is used, the power of the signal processing cell is turned on.
By controlling so that power consumption can be reduced, power saving can be achieved.

According to a seventh aspect of the present invention, in the signal processing cell, the nonvolatile memory element is formed by using a ferroelectric material. Therefore, a signal processing cell in which the processing procedure information can be rewritten in a nonvolatile manner in real time can be realized with a simple circuit configuration.

An eighth aspect of the present invention is a signal processing apparatus using a plurality of the signal processing cells according to any one of the first to seventh aspects. Therefore, for example, a dynamically programmable gate array (DPGA) that can perform complicated processing at high speed with a simple configuration can be realized.

[0020]

FIG. 1 is a block diagram showing a signal processing cell 82 constituting a dynamically programmable gate array (DPGA) which is a signal processing device according to an embodiment of the present invention. The signal processing cell 82 includes a program cell 2, an output latch unit 84, a program data setting unit 86, and a latch circuit selection unit 88.

FIG. 2 is a circuit diagram of the program cell 2. The program cell 2 includes a program latch unit 4 which is a processing procedure information storage unit, and a combination circuit unit 6. The combinational circuit unit 6 converts the input external input signal A, which is the first processed signal, and the feedback input signal O, which is the second processed signal (both binary signals), into the program latch unit 4.
The processing is performed according to the logical operation configuration (processing procedure) determined by the program data stored in. The output D is the output of the program cell 2.

The processing procedure in the combination circuit section 6 is dynamically programmable. That is, the program data stored in the program latch unit 4 is configured to be changed in real time.

The program data line PDL shown in FIG.
Is taken into the program latch unit 4 (see FIG. 2) constituting the program cell 2 via the program data setting unit 86. The output latch section 84 shown in FIG. 1 includes a plurality of latch circuits LT, LT,... For latching a plurality of outputs D output from the program cell 2 at different timings. The output D output from the program cell 2 is latched by one of the latch circuits LT selected by the latch circuit selection unit 88.

On the other hand, one of the plurality of outputs D latched by the latch circuits LT, LT,... Becomes a feedback input signal O of the program cell 2 via a feedback line FBL which is a feedback section. . Which latch content of the latch circuit LT is used as the feedback input signal O is determined by the above-described latch circuit selection unit 88.

The latch circuit selecting section 88 selects one of the plurality of latch circuits LT, LT,... Constituting the output latch section 84 in accordance with the latch address data given to the latch address line LAL. .

As will be described later, each latch circuit LT, L
T,..., And the above-described program latch unit 4 (see FIG. 2) use a nonvolatile storage element using a ferroelectric substance.

Although only one signal processing cell 82 is shown in FIG. 1, in this embodiment, the DPGA has a plurality of signal processing cells 82 (not shown). According to the bank control data given to the bank control line BCL, the program data line PDL
Of the signal processing cell 82
Is given. Similarly, the above-mentioned latch address line LAL is controlled by the bank control data.
Is specified to which signal processing cell 82 the latch address data applied to is applied.

Referring to FIG. 2, the structure of the program cell 2 will be described in some detail. The program latch unit 4 can rewritably store 4-bit program data that is processing procedure information. That is, the program latch unit 4 includes four latch circuits F0, F1, F2, and F3 corresponding to the number of bits of the program data. Each of the latch circuits F0, F1, F2, and F3 is configured by a nonvolatile storage element having a ferroelectric, that is, a ferroelectric storage element.

The combination circuit section 6 includes three pairs of switching elements, ie, a pair of transistors TP1, TP2 and TP3.

The transistor pair TP1 includes two switching elements, transistors T1 and T2.

The transistor T1 is a metal oxide semiconductor field effect transistor (MOSFET), and has a source electrode S1 as an input terminal and a drain electrode as an output terminal based on data input to a gate electrode G1 as a control terminal. It functions as a switching element for switching between making the electrode D1 substantially conductive and non-conductive.

The transistor T2 has the same configuration as the transistor T1. That is, the transistor T2 causes the source electrode S2 as the input terminal and the drain electrode D2 as the output terminal to be substantially conductive or non-conductive based on the data input to the gate electrode G2 as the control terminal. It functions as a switching element for switching between the states.

The drain electrode D1 of the transistor T1 and the drain electrode D2 of the transistor T2 are connected to form a common output terminal, ie, a common drain electrode CD.

The other transistor pairs TP2 and TP3 have the same configuration as the transistor pair TP1.

As shown in FIG. 2, three transistor pairs TP1, TP2, TP3 constituting the combinational circuit section 6 are
Due to the circuit configuration, they are arranged in two layers. First from the top of the drawing
In the layer, one transistor pair TP1 is arranged. In the second layer, two transistor pairs TP2 and TP
3 are arranged.

The transistor pair TP2, T belonging to the second layer
P3 total of four source electrodes S2, S1, S2, S1
Is, as described above, the 4 that constitutes the program latch unit 4.
To the three latch circuits F0, F1, F2, F3, respectively.
They are connected one-to-one.

The transistor pair TP2, T belonging to the second layer
A total of two common drain electrodes CD, CD of P3 are connected one-to-one to the source electrodes S2, S1 of the transistor pair TP1 belonging to the first layer.

The input signal line L1 for inputting the external input signal A is connected to the gate electrode G1 of the transistor T1 forming the transistor pair TP1 belonging to the first layer. On the other hand, an input signal line L1 for inputting an inverted signal of the external input signal A to the gate electrode G2 of the transistor T2.
B is connected.

An input signal line L2 for inputting a feedback input signal O is connected to the respective gate electrodes G1, G1 of the two transistors T1, T1 constituting the transistor pair TP2, TP3 belonging to the second layer. On the other hand, an input signal line L for inputting an inverted signal of the feedback input signal O to each gate electrode G2, G2 of the two transistors T2, T2.
2B is connected.

Therefore, the input external input signal A,
The feedback input signal O is processed according to the logical operation configuration determined based on the 4-bit program data given to the program latch unit 4, and is output to the common drain electrode CD of the first-layer transistor pair TP1.

FIG. 3 is a table describing the relationship between the input mode and the output pattern in the program cell 2 shown in FIG. 4A to 4D are diagrams illustrating an example of an equivalent circuit of the combinational circuit unit 6 that changes according to the contents of the program data given to the program latch unit 4. The operation of the program cell 2 will be described with reference to FIGS. 2, 3, and 4A to 4D.

As shown in FIG. 2, the input to be processed
Are the external input signal A and the feedback input signal O. Outside
Both the input signal A and the feedback input signal O are binary signals.
Input mode (external input signal A and feedback input signal
The combination of the contents of issue O) is 2 ²As shown in FIG.
As shown in the figure, there are four types of input modes M0 to M3.
You.

On the other hand, since the output D is also a binary signal, the output pattern (the combination of the contents of the output D for each input mode M0 to M3) ^{2 4} types, i.e., as shown in FIG. 3, the output pattern D0~ There are 16 types of D15.
That is, there are 16 logical operation configurations for processing the external input signal A and the feedback input signal O to obtain the output D.

In this embodiment, by providing 4-bit program data corresponding to the output patterns D0 to D15 shown in FIG. 3 to the program latch unit 4 shown in FIG. It was made possible to change in 16 ways.

FIG. 4A shows an equivalent circuit of the combinational circuit unit 6 when 4-bit program data "0000" corresponding to the output pattern D0 shown in FIG. 3 is given to the program latch unit 4 shown in FIG. It is. From the equivalent circuit, the combinational circuit unit 6 calculates the logical operation configuration (logical expression) “D =
0 "is satisfied.

FIG. 4B shows 4-bit program data "000" corresponding to the output pattern D1 shown in FIG.
3 is a diagram showing an equivalent circuit of the combinational circuit unit 6 when “1” is given to the program latch unit 4 shown in FIG. 2. From the equivalent circuit, the combinational circuit unit 6 has a logical operation configuration “D = A”.
It turns out that B "is satisfied.

Similarly, FIGS. 4C to 4D show 4-bit program data "0010" to "0011" corresponding to the output patterns D2 to D3 shown in FIG.
5 is a diagram showing an equivalent circuit of the combinational circuit unit 6 when the circuit is given to the program latch unit 4 shown in FIG. It can be seen from the respective equivalent circuits that the combinational circuit unit 6 given the 4-bit program data satisfies the corresponding logical operation configuration described in the “logical expression” column of FIG. In addition, 4 corresponding to the output patterns D4 to D15
Bit program data “0100” to “111”
The description of the equivalent circuit of the combinational circuit unit 6 when “1” is given to the program latch unit 4 shown in FIG. 2 is omitted.

As described above, the program cell 2 shown in FIG.
Is used, it is possible to arbitrarily set the arithmetic operation configuration of the combinational circuit unit 6 only by supplying 4-bit program data to the program latch unit 4.

The operation of the program cell 2 in which 4-bit program data is set will be described. The source electrodes S1, S2 of the transistors T1, T2,... According to the external input signal A, the feedback input signal O input to the gate electrodes G1, G2 shown in FIG.
.. And the drain electrodes D1, D2,... Become substantially conductive or non-conductive.

The transistor pair TP2, T belonging to the second layer
The 4-bit program data given to each of the source electrodes S2, S1, S2, and S1 of P3 reaches the common drain electrode of the first layer via the transistor which is substantially in a conductive state, and the program cell 2 Is output D.

As described above, at the time of processing in the program cell 2, since the external input signal A, the feedback input signal O, and their inverted signal only pass through the gate electrode G1 or G2 by one stage, the signal processing is performed. Speed will be faster.

All of the three terminals of the transistors T1, T2,..., That is, the gate electrode, the source electrode, and the drain electrode are used for signal input or output. That is, the gate electrode is used as a terminal for inputting an external input signal A, a feedback input signal O, and an inverted signal thereof, the source electrode is used as a terminal for inputting program data, and the drain electrode is used for outputting program data. It is used as a terminal on the side where

Therefore, complicated logic processing can be performed with a small number of transistors (six in this embodiment). Therefore, the degree of integration of the program cells can be increased. In addition, power consumption during signal processing can be reduced.

Further, since a metal oxide semiconductor field effect transistor (MOSFET) is used as the switching element, the degree of integration of the program cells can be further increased. Further, power consumption during signal processing can be further reduced.

The case where two signals (external input signal A and feedback input signal O) are input as the processed signal has been described as an example, but the processed signal is not limited to this.
The present invention can be applied to a case where three or more signals are input as a signal to be processed or a case where only one signal is input.

FIG. 5 is a circuit diagram of a program cell 12 configured to receive three signals (external input signal A, external input signal B, and feedback input signal O). The program cell 12 has substantially the same configuration as the above-described program cell 2 (see FIG. 2). However, it is partially different from the program cell 2 in order to support three inputs.

That is, as shown in FIG. 5, the combinational circuit section 16 of the program cell 12 includes seven transistor pairs TP1 to TP7 arranged in three layers in terms of circuit configuration. In the first layer from the top of the drawing, one transistor pair TP1 is arranged. In the second layer, two transistor pairs TP2 and TP3 are arranged. On the third layer, four transistor pairs TP4, TP5, TP6, T
P7 is arranged.

The program latch section 14 of the program cell 12 can rewritably store 8-bit program data as processing procedure information. That is, the program latch unit 14 includes eight latch circuits F0 to F7 corresponding to the number of bits of the program data.

FIG. 6 is a table describing the relationship between the input mode and the output pattern in the program cell 12. As shown in FIG. 5, the input to be processed, the external input signal A, an external input signal B, since it is three feedback input signal O, input mode 2 ^triplicate, i.e., as shown in FIG. 6 , Input modes M0 to M7.

[0060] Therefore, the output pattern ^{2 eight,} i.e., as shown in FIG. 6, the output pattern D0~D25
5, 256 ways. That is, there are 256 logical operation configurations for processing the external input signal A, the external input signal B, and the feedback input signal O to obtain the output D.

That is, in the program cell 12,
By providing 8-bit program data corresponding to the output patterns D0 to D255 shown in FIG. 6 to the program latch unit 14 shown in FIG. 5, the logical operation configuration of the combinational circuit unit 16 can be changed in 256 ways. .

Program cell 2 or program cell 1
Focusing on 2, the signal processing cell 82 is generally described as follows.

That is, the signal processing cell 82 is a signal processing cell having a combinational circuit unit for processing and outputting the input processed signal in accordance with a predetermined processing procedure.
The combinational circuit unit determines whether the input terminal and the output terminal are substantially in a conductive state or a non-conductive state based on the following (A) switching element pair and (A) data input to the control terminal. Equipped with two switching elements for switching,
The control terminals of the two switching elements are respectively connected to the first
And a second control terminal, wherein the input terminals of the two switching elements are first and second input terminals, respectively, and the output terminals of the two switching elements are combined to form a common output terminal. (2 ⁿ −
1) (n is a positive integer) such that the number of switching element pairs belonging to the i-th layer (i = 1, 2,..., N) is 2 ^(i−1). 2 ⁿ corresponding to a total of 2 ⁿ first and second input terminals of a switching element pair belonging to the n-th layer and arranged on the n-th layer in terms of circuit configuration.
Bits of programmable procedure information, where n is 2
In the above case, the output of the common output terminal of each switching element pair belonging to the i-th layer (i = 2,.
1) applied to the corresponding first or second input terminal of the switching element pair belonging to the layer, and to the ith layer (i = 1, 2,..., N)
, The ith processing signal is input to the first control terminal of each switching element pair, and a signal obtained by inverting the ith processing signal is input to the second control terminal. A programmable signal configured to process the signal in accordance with a processing procedure determined based on the provided processing procedure information and to output the signal to a common output terminal of the first-layer switching element pair. Processing cell.

In each of the above embodiments, the case where a metal oxide semiconductor field effect transistor (MOSFET) is used as the switching element has been described as an example. However, the switching element is not limited to this. Absent. As the switching element, for example, another field-effect transistor or a bipolar transistor can be used. Also, a switching element such as a relay can be used.

In the above embodiment, the ferroelectric memory element used for the latch circuit F0 and the like constituting the program latch section 4 and the like is not particularly limited.
For example, a storage element using a ferroelectric capacitor, such as a one-transistor one-capacitor type ferroelectric storage element or a two-transistor two-capacitor type ferroelectric storage element, can be used.

FIG. 7 shows a part of the circuit configuration of the ferroelectric memory element 22 using such a ferroelectric capacitor.
The ferroelectric memory element 22 includes a ferroelectric (for example, PZT
(PbZr _x Ti _1-x O ₃ )) Ferroelectric Capacitor 2
4 and a load capacitor 26. FIG. 8 shows a voltage related to the ferroelectric capacitor 24 (the bit line BL when the plate line PL shown in FIG.
2 shows a hysteresis curve (voltage-charge characteristic) showing the relationship between the polarization state and the polarization state (in the figure, represented by “charge” equivalent to the “polarization state”).

In FIG. 8, a state in which remanent polarization Z1 occurs is referred to as a first polarization state P1 (corresponding to stored data "1").
The state in which the remanent polarization Z2 occurs is referred to as a second polarization state P2 (corresponding to the stored data “0”). By examining which polarization state the ferroelectric capacitor 24 is in, the data stored in the ferroelectric capacitor 24 can be read.

In order to check the polarization state of the ferroelectric capacitor 24, the bit line BL is set to the floating state after discharging the load capacitor 26 shown in FIG. The application voltage Vp is applied, and the voltage Vf generated across the ferroelectric capacitor 24 at this time is measured.

According to the diagrammatic solution shown in FIG. 8, when the capacitance of the load capacitor 26 is represented by the slope of the straight line L1, if the ferroelectric capacitor 24 is in the first polarization state P1, the ferroelectric capacitor Voltage Vf generated across capacitor 24
Becomes V1, and if it is in the second polarization state P2, the voltage Vf
Becomes V2. Therefore, if the reference voltage Vref is set as shown in FIG. 8, by comparing the voltage Vf generated at both ends of the dielectric capacitor 24 at the time of reading with the reference voltage Vref, the polarization of the ferroelectric capacitor 24 can be determined. You can check if it is in the state.

By examining the polarization state of the ferroelectric capacitor 24 in this manner, the stored data corresponding to the polarization state can be read.

As a ferroelectric memory element used in the latch circuit F0 and the like, in addition to the above-described memory element using a ferroelectric capacitor, for example, an FET using a ferroelectric film is used.
(Field-effect transistors).

FIG. 9A shows an example of an FET using a ferroelectric film. The FET 32 shown in FIG. 9A has the MFMIS (Me
tal Ferroelectric Metal Insulator Silicon) FET, which is a channel forming region C of the semiconductor substrate 34
H, the gate oxide film 36 and the floating gate 3
8, a ferroelectric film 40 and a control gate 42 are formed in this order.

FIG. 9B is a diagram in which the FET 32 shown in FIG. 9A is represented by a symbol. The source electrode S is connected to the source region formed on the semiconductor substrate 34, and the drain electrode D is connected to the drain region. The control gate 42 is connected to the control gate electrode CG. Nothing is connected to the floating gate 38, and the substrate 34 of the floating FET 32 (N-channel) is grounded, and the control gate 4
When a positive voltage + V is applied to 2, the ferroelectric film 40 causes polarization reversal. Even when the voltage of the control gate 42 is removed, the channel formation region C
H generates a negative charge. This is referred to as "1".

Conversely, when a negative voltage -V is applied to the control gate 42, the polarization of the ferroelectric film 40 is reversed in the reverse direction. Even if the voltage of the control gate 42 is removed,
Due to the remanent polarization of the ferroelectric film 40, the channel formation region CH
Generates a positive charge. This is set to a state of “0”.
Thus, information (“1” or “0”) is written into the FET 32.

To read the written information, a read voltage Vr is applied to the control gate 42. The read voltage Vr is set to a value between the threshold voltage Vth1 of the FET 32 in the state of “1” and the threshold voltage Vth0 of the FET 32 in the state of “0”. Therefore, when the read voltage Vr is applied to the control gate 42, whether the written information is “1” or “0” is detected by detecting whether or not a predetermined drain current has flowed.
You can see if it was. When reading is performed, the written information does not disappear.

As described above, the FET 3 using the ferroelectric film
If 2 is used, so-called non-destructive reading becomes possible.
For this reason, like a ferroelectric memory element for destructive reading,
When reading is performed, the stored contents are not destroyed once. Therefore, the operation speed during the read operation is high. Further, power consumption is small. Further, since the ferroelectric film is less deteriorated and the reliability of retaining the stored contents is relatively high, it is more convenient.

By configuring the latch circuits F0 and the like constituting the program latch section 4 and the like using ferroelectric memory elements, the processing procedure can be stored even when the power is cut off. . Therefore, even if the power is shut off due to some kind of accident, it is possible to quickly return to the processing procedure before the power was shut down. When the signal processing cell 82 is not used, the power of the signal processing cell 82 is turned off, and the power of the signal processing cell 82 is controlled to be turned on when the signal processing cell 82 is used. Thus, power saving can be achieved.

Further, by using a ferroelectric storage element, a program cell in which processing procedure information can be rewritten in a nonvolatile manner in real time can be realized with a simple circuit configuration.

In each of the above-described embodiments, the case where a ferroelectric memory element is used as a nonvolatile memory element used in the latch circuit F0 or the like constituting the program latch section 4 or the like has been described as an example. However, the nonvolatile storage element used for the latch circuit F0 and the like is not limited to the ferroelectric storage element.

In the above-described embodiment, the latch circuits F0 and the like constituting the program latch section 4 and the like are constituted by using the nonvolatile storage elements. However, the latch circuits F0 and the like are constituted by using the volatile storage elements. You may comprise. As a volatile storage element used for the latch circuit F0 or the like, for example,
The storage element 62 (SRAM (st
atic random access memory)). Since the storage element 62 can rewrite program data in real time, the storage element 62 can be used as a program cell configuring a dynamically programmable gate array (DPGA). However, when the power is turned off, the program data is lost.

Next, the latch circuit L described above (see FIG. 1)
The configuration of T will be described with reference to FIG.

The latch circuit LT has a line 104 constituting a signal path for transmitting the output D. Line 104
Is constituted by a line 106 constituting a main signal path and a line 108 constituting a feedback signal path.
The line 106 and the line 108 form an annular signal path.

On the input side of the ring signal path, line 1
A transmission gate GT1, which is an input-side gate that performs a switching operation based on a clock pulse Cp, which is a gate control signal, is inserted in 04. The transmission gate GT1 is configured to be turned off when the clock pulse Cp is “H” and to be turned on when the clock pulse Cp is “L”.

A transmission gate GT2, which is a feedback gate, is inserted into the line 108. The transmission gate GT2 is turned on when the clock pulse Cp is “H”, and is turned off when the clock pulse Cp is “L”, contrary to the transmission gate GT1.
F.

As described above, the transmission gate G
By inserting T2 to cut off the line 108, power consumption during non-latching can be reduced.

The line 106 includes an inverter circuit INV
1 is inserted. The inverter circuit INV1 has a CM
An OS inverter circuit having a configuration in which a P-channel MOSFET and an N-channel MOSFET are connected in series.

As described above, the line 1 constituting the main signal path
By not providing a ferroelectric transistor in 06, the signal transmission speed during non-latching can be increased.

An inverter circuit INV2, which is a ferroelectric memory, is inserted into the line 108. The inverter circuit INV2 has the same configuration as the inverter circuit INV1.
Although this is a MOS inverter circuit, it differs from the inverter circuit INV1 in that the transistor PT, which is a P-channel MOSFET, and the transistor NT, which is an N-channel MOSFET, are both ferroelectric transistors.

Transistor NT and Transistor PT
Is a ferroelectric transistor having a so-called MFMIS structure, and has a configuration similar to that of the above-described FET 32 (see FIGS. 9A and 9B).

The control gate electrode CG (the input side of the inverter circuit INV2) is connected to the output side of the inverter circuit INV1 shown in FIG. 11, and the drain electrode D (the output side of the inverter circuit INV2) is connected to the transmission gate GT2. , Source electrode S is grounded.

The transistor NT and the transistor PT are one except that one is an “N-channel type” MOSFET and the other is a “P-channel type” MOSFET.
It has a similar configuration. That is, the transistor PT also has M
This is a ferroelectric transistor having an FMIS structure.

Output D from program cell 2 shown in FIG.
Is supplied to the selected latch circuit LT via the latch circuit selecting transistor ST turned ON by the latch circuit selecting unit 88. The output D given to the latch circuit LT is the transmission gate G shown in FIG.
After being input via T1 and inverted by the inverter circuit INV1, it is again inverted (ie, restored) by the inverter circuit INV2, and is again returned to the inverter circuit INV.
1 is input. That is, the data holding is stabilized using the feedback circuit having the inverter circuit INV2.

The output of the inverter circuit INV1, that is, the output of the latch circuit LT is input to the program cell 2 as the feedback input signal O via the transistor ST and the feedback line FBL shown in FIG. That is, the selected latch circuit L via the latch circuit selecting transistor ST turned on by the latch circuit selection unit 88.
The output of T is used as the feedback input signal O as the program cell 2
Is input to

As described above, the latch circuit LT shown in FIG.
Has ferroelectric transistors NT and PT. Therefore, the processing result can be stored even when the power is turned off. Therefore, even if the power is shut off due to some accident, the data can be promptly returned to the state before the power was shut down.
When the signal processing cell 82 is not used, the power of the signal processing cell 82 is turned off, and the power of the signal processing cell 82 is controlled to be turned on when the signal processing cell 82 is used. Thus, power saving can be achieved.

Further, by using a ferroelectric transistor, a latch circuit capable of latching data in a nonvolatile manner in real time can be realized with a simple circuit configuration.

The structure of latch circuit LT is not limited to the structure shown in FIG. For example, FIG.
Conversely, two transistors forming the inverter circuit INV1 can be ferroelectric transistors. Further, all of the four transistors forming the inverter circuits INV1 and INV2 may be ferroelectric transistors. Further, only one of the four transistors may be a ferroelectric transistor. Furthermore, the latch circuit LT can be configured using a ferroelectric capacitor (see FIG. 7).

Although the case where a ferroelectric memory element is used as the nonvolatile memory element used in the latch circuit LT has been described as an example, the nonvolatile memory element used in the latch circuit LT is a ferroelectric memory element. However, the present invention is not limited to this.

Although the latch circuit LT is configured using a non-volatile memory element, the latch circuit LT is, for example, shown in FIG.
2 may be used for the SRAM (static random access memory) type volatile storage element. However, in this case, when the power is turned off, the latch data is lost.

Next, the operation of the signal processing cell 82 will be described with reference to FIG. 6 and FIGS. FIG.
FIG. 2 is a simplified block diagram showing a part of the signal processing cell 82 shown in FIG. 1 to explain the operation of the signal processing cell 82. However, the program cell 12 shown in FIG. 5 is used instead of the program cell 2. Further, for convenience of explanation, it is assumed that the output latch section 84 includes only one latch circuit LT.

FIG. 14 shows a signal processing cell 8 when 8-bit program data corresponding to the output pattern D0 of FIG. 6 is given to the program latch section 14 shown in FIG.
2 is a state transition diagram of FIG.

As shown in FIG. 6, for example, when external input signals A and B and feedback input signal O are all "0" (in the case of input mode M0), output D resulting from processing these inputs is output. Becomes “0”. Therefore, the feedback input signal O becomes "0" again. That is, the input mode remains M0 (see FIG. 14).

On the other hand, when the external input signals A and B are "0" and the feedback input signal O is "1" (in the case of the input mode M1), the output D obtained by processing these inputs is "0". "
Becomes Therefore, the feedback input signal O becomes “0”.
That is, the input mode shifts from M1 to M0 (see FIG. 14).

Similarly, the initial state is the input mode M2, M
4, M6, these states are maintained even after the input processing (see FIG. 14). If the first state is the input mode M3, M5, M7, after the input processing, these states are changed to the input modes M2, M5 respectively.
4 and M6 (see FIG. 14).

FIG. 15 shows a signal processing cell 8 when 8-bit program data corresponding to the output pattern D1 of FIG. 6 is supplied to the program latch section 14 shown in FIG.
2 is a state transition diagram of FIG.

A comparison between FIG. 14 and FIG. 15 shows that when the initial state is the input mode M7, how the state changes next differs between the two.

Although not shown, the output patterns D2 to D2 in FIG.
FIG. 5 shows 8-bit program data corresponding to D255.
In the case where it is given to the program latch unit 14 shown in FIG.
There are state transition diagrams of the signal processing cells 82, respectively.

As described above, the output D of the program cell 12 is
Is latched in the latch circuit LT, and is fed back to the program cell 12 at a predetermined timing as the feedback input signal O, whereby a plurality of continuous processes can be realized by one program cell 12. in this case,
By providing arbitrary 8-bit program data to the program latch unit 14 shown in FIG. 5, a plurality of desired continuous processes can be realized.

Further, in this embodiment, the program data given to the program latch section 14 can be changed in real time. Therefore, continuous and more complicated processing can be realized by one program cell 12. Further, by providing a large number of processing signals to be input to the program cell 12, simultaneous parallel processing becomes possible. That is, complicated processing can be performed at high speed with a simple configuration.

Further, as described above, in this embodiment, as shown in FIG.
Are latched in a plurality of latch circuits LT, LT,..., And if necessary, an output at a desired timing is taken out from an arbitrary latch circuit LT, and a feedback input is performed. The signal O can be fed back to the program cell 12.

Therefore, it is possible to restart the processing from an arbitrary point in time or to jump to an arbitrary processing in a series of processing. Further, the program data to be supplied to the program latch unit 14 and the latch circuit LT for extracting the feedback input signal O can be changed in real time, so that a more complicated and continuous process can be performed with a simple configuration.

Further, the DPGA in this embodiment
As described above (see FIG. 1), the plurality of signal processing cells 8
., And which signal processing cell 82 is to be given the program data given to the program data line PDL by the bank control data given to the bank control line BCL. Similarly, by bank control data,
To which signal processing cell 82 the latch address data given to the latch address line LAL is given,
Be instructed.

Therefore, a plurality of signal processing cells 82, 8
By performing the processing in a plurality of signal processing cells 82, 82,... In real time by switching between 2,..., It is possible to execute extremely complicated continuous processing despite the simple configuration.

In the above-described embodiment, the signal processing cell 82 having the two-input one-output program cell 2 or the three-input one-output program cell 12 as the signal processing cell.
However, the signal processing cell according to the present invention is not limited to these. For example, the present invention can be applied to a signal processing cell including a 3-input / 2-output program cell.

FIG. 16 is a simplified block diagram showing a part of such a signal processing cell. The signal processing cell shown in FIG. 16 has three input and two output program cells 92 and 2
And a latch circuit 94 that can latch two data.

The program cell 92 processes the external input signal A and the feedback input signals O1 and O2 according to the applied 16-bit program data, and outputs the outputs D1 and D2.
Get. The outputs D1 and D2 are latched by the latch circuit 94 and input to the program cell 92 at predetermined timings as the feedback input signals O1 and O2 via the processing lines FBL1 and FBL2.

Program cell 92 and latch circuit 94 in FIG. 16 correspond to, for example, program cell 1 shown in FIG.
17 and two latch circuits LT, respectively.
It can be realized by connecting as follows.

FIG. 18 is a table showing the relationship between the input mode and the output pattern in the program cell 92.
As shown in FIG. 16, the input to be processed, the external input signal A, the feedback input signal O1, 3 one because it of the feedback input signal O2, input mode 2 ^triplicate, i.e., as shown in FIG. 18 , Input modes M0 to M7.

[0118] Thus, each of the ^{two eight} output pattern of the output D1, D2, i.e., as shown in FIG. 18, the output pattern of the output D1 is output pattern D1,0~
There are 256 patterns of D1,255, and the output pattern of the output D2 is 256 patterns of output patterns D2,0 to D2,255.
In other words, the external input signal A, the feedback input signal O1, logical operation configuration for processing the feedback input signal O2 obtain an output D1, D2 is, 256 × 256 ways, i.e. there are ^{two 16.}

That is, in the program cell 92,
Providing 16-bit program data corresponding to a combination of the output patterns D1,0 to D1,255 and the output patterns D2,0 to D2,255 shown in FIG. 18 to the program latch unit (see the program latch unit 14 in FIG. 5). Thus, the logical operation configuration of the combinational circuit section (see FIG. 5, combinational circuit section 16) can be changed in ²¹⁶ ways.

Next, based on FIGS. 16 to 19, FIG.
The operation of the signal processing cell shown in FIG. FIG. 19 shows an example of a state transition diagram of the signal processing cell shown in FIG. 16 (16-bit program data corresponding to the output patterns D1,163 and D2,64 in FIG. 18 is given to the program latch unit of the program cell). FIG. 7 is a state transition diagram of the signal processing cell in the case).

In the above example, as shown in FIG. 18, when the external input signal A and the feedback input signals O1 and O2 are all "0" (in the case of the input mode M0), these inputs are processed. Outputs D1 and D2 of the result are “1” and “0”, respectively. Therefore, the feedback input signal O
1 and O2 are “1” and “0”, respectively. That is, the input mode shifts to M2 (see FIG. 19).

On the other hand, the external input signal A and the feedback input signal O1
Are both "0" and the feedback input signal O2 is "1" (in the case of the input mode M1), the outputs D1 and D2 obtained by processing these inputs are "0" and "1", respectively. Become. Therefore, the feedback input signals O1 and O2 are "0" and "1", respectively. That is, the input mode is M1
(See FIG. 19).

FIG. 19 also shows how the states change when the first state is the input mode M2 to M7. Although not shown, there are state transition diagrams of the signal processing cells when 16-bit program data corresponding to another combination of the output patterns shown in FIG.

As described above, by applying the present invention to a signal processing cell having a 3-input / 2-output program cell, a plurality of more complicated and continuous processes can be realized. Further, the present invention can be applied to a multi-output program cell other than three-input two-output, for example, a five-input three-output program cell.

In each of the above embodiments, the output latch section having a plurality of latch circuits is provided. However, the output latch section having one latch circuit may be provided.

In each of the above embodiments, the signal latched by the latch circuit is fed back to be used as the processed signal of the combinational circuit unit. However, the latched signal is not fed back. Can also.

Further, in each of the above embodiments, the processing procedure in the combinational circuit section is configured to be dynamically programmable, but the processing procedure in the combinational circuit section may be configured to be not dynamically programmable.

The present invention can be applied not only to a dynamically programmable gate array (DPGA) but also to a general signal processing device such as a computer. Further, the present invention can be applied to general semiconductor devices including at least one signal processing cell.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a signal processing device according to an embodiment of the present invention;
FIG. 3 is a block diagram showing a signal processing cell 82 constituting PGA).

FIG. 2 is a circuit diagram showing an example of a program cell used for a signal processing cell 82.

FIG. 3 is a table describing a relationship between an input mode and an output pattern in the program cell 2 shown in FIG. 2;

FIGS. 4A to 4D are diagrams showing equivalent circuits of the combinational circuit unit 6 which change according to the contents of program data given to the program latch unit 4. FIGS.

FIG. 5 is a circuit diagram showing another example of a program cell used for the signal processing cell 82.

FIG. 6 is a table describing a relationship between an input mode and an output pattern in the program cell 12 shown in FIG.

FIG. 7 is a diagram showing a part of a circuit configuration of a ferroelectric memory element 22 using a ferroelectric capacitor.

FIG. 8 is a drawing showing a hysteresis curve (voltage / charge characteristic) representing a relationship between a voltage and a polarization state regarding the ferroelectric capacitor 24.

FIG. 9A is a drawing showing an example of an FET using a ferroelectric film. FIG. 9B is a diagram in which the FET 32 shown in FIG. 9A is represented by a symbol.

FIG. 10 is a diagram showing an example of a volatile storage element used in the latch circuit F0 and the like by symbols.

FIG. 11 is a circuit diagram showing an example of a configuration of a latch circuit LT shown in FIG. 1;

FIG. 12 is a circuit diagram showing another example of the configuration of the latch circuit LT shown in FIG. 1;

FIG. 13 illustrates the operation of the signal processing cell 82;
FIG. 2 is a simplified block diagram showing a part of a signal processing cell 82 shown in FIG.

FIG. 14 is a state transition diagram of the signal processing cell 82 when 8-bit program data corresponding to the output pattern D0 of FIG. 6 is given to the program latch unit 14.

FIG. 15 is a state transition diagram of the signal processing cell 82 when 8-bit program data corresponding to the output pattern D1 of FIG. 6 is given to the program latch unit 14.

FIG. 16 is a simplified block diagram showing a part of another example of a signal processing cell included in a dynamically programmable gate array (DPGA) which is a signal processing device according to an embodiment of the present invention.

17 is a diagram showing a specific configuration example of a program cell 92 and a latch circuit 94 in FIG.

18 is a table describing a relationship between an input mode and an output pattern in a program cell 92. FIG.

19 is a drawing illustrating an example of a state transition diagram of the signal processing cell illustrated in FIG. 16;

[Explanation of symbols]

 2 Program cell 84 Output latch unit A External input signal D Output FBL Feedback line LT ·········· Latch circuit O ········· Feedback input signal

Claims (8)

[Claims] 1. A signal processing cell having a combinational circuit unit for processing and outputting an input processed signal in accordance with a predetermined processing procedure, wherein the processing procedure in the combinational circuit unit is dynamically programmable. And an output latch unit for latching a signal output from the combinational circuit unit, and a feedback unit for feeding back the signal latched by the output latch unit for use as a processed signal of the combinational circuit unit. A signal processing cell, characterized in that: 2. A signal processing cell having a combinational circuit unit for processing and outputting an input processed signal in accordance with a predetermined processing procedure, wherein a plurality of signals output at different timings from the combinational circuit unit are latched. A signal processing cell, comprising: an output latch unit having a plurality of latch circuits. 3. The signal processing cell according to claim 2, further comprising: a feedback unit that feeds back a signal selected from the plurality of signals latched by the plurality of latch circuits so as to use the selected signal as a processed signal of the combinational circuit unit. That has been provided. 4. The signal processing cell according to claim 2, wherein a processing procedure in said combinational circuit unit is dynamically programmable. 5. The signal processing cell according to claim 1, wherein the output latch unit is configured using a nonvolatile memory element. 6. The signal processing cell according to claim 1, wherein the combinational circuit unit is configured using a nonvolatile memory element. 7. The signal processing cell according to claim 5, wherein the nonvolatile memory element is formed using a ferroelectric material. 8. A signal processing device comprising a plurality of the signal processing cells according to claim 1.