JP2001093293A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve relieving efficiency of a shift type redundant circuit and to reduce exclusive area of a redundant cell. SOLUTION: In first to third memory sub-arrays 11A-11c excluding a forth memory sub-array 11D, cell columns of 64 columns accessed by column lines respectively are arranged, cell columns of 65 columns including a redundant cell column 11a is arranged only in the forth memory sub-array 11D. An internal data bus DBA and an internal column line start signal line YA connected to the forth memory sub-array 11D are formed respectively as a signal line having 65 bits width. A connection switching circuit 121 is arranged so that the column line start signal line Y and the internal column line start signal line YA can be connected by shifting, and a data bus DB and an internal data bus DBA also are arranged so that they can be connected by shifting.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a plurality of data input / output circuits and a number of memory cell arrays corresponding to a plurality of data input / output circuits. The present invention relates to a semiconductor memory device having a redundant cell function of replacing a redundant memory cell group having the same configuration as a memory cell group (column) and performing repair.

[0002]

2. Description of the Related Art Conventionally, in a semiconductor memory device such as a DRAM (Dynamic Random Access Memory), a redundant circuit is provided as a means for improving the yield in manufacturing.

[0003] As such a redundant circuit, a shift type redundant circuit capable of rapidly raising a column line is known. Japanese Patent Application Laid-Open No. Hei 9-231790 discloses a configuration in which two sets of series-connected fuses and two column line switching circuits are provided so that a defective cell column of two column lines can be relieved per memory cell block. It has been disclosed.

[0004]

Recently, large-scale semiconductor memory devices adopt a sub-array configuration in which a memory cell array is divided into a predetermined number of blocks, and an external data input / output circuit is arranged for each sub-array. General. Here, the external data input / output circuits are often provided by the number corresponding to the bit width of the external data bus. Therefore, when expanding the bit width of the external data bus, for example,
When the width is increased from 16 bits to 32 bits, it is necessary to increase the number of external data input / output circuits by the number of bits to be expanded.

However, in the conventional semiconductor memory device having a shift-type redundant circuit, since a redundant cell column is provided for each sub-array corresponding to an external data input / output circuit, the area occupied by the redundant cell column is increased, and In addition, there is a problem that the use efficiency of the redundant cell column is poor.

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above-described conventional problems, and has as its object to improve the relief efficiency of a shift-type redundant circuit and reduce the area occupied by redundant cells.

[0007]

In order to achieve the above-mentioned object, the present invention provides a semiconductor memory device in which a plurality of data rows are stored in each cell row included in the sub-array without providing a redundant cell row for each sub-array. A connection switching means is provided which is connected to any one of the output circuits and which can sequentially shift and change the connection state between the data input / output circuit and the cell column.

More specifically, a first semiconductor memory device according to the present invention comprises a plurality of data holding units having a plurality of data holding units arranged in a matrix, and a plurality of data holding units corresponding to the plurality of data holding units. Input / output means, and a plurality of data holding means and a connection switching means for switching an electrical connection between the plurality of data input / output means, wherein the connection switching means comprises one column or one row included in the plurality of data holding means. Each data holding unit to one of a plurality of data input / output units.
The connection state is provided so that the connection state can be sequentially shifted and changed when the connection is switched.

According to the first semiconductor memory device, the connection switching unit selects one of the data holding units for one column or one row included in the plurality of data holding units with any one of the plurality of data input / output units. The data transferred from the data input / output means is not limited to one of the plurality of data holding means. Further, the connection switching means is provided so that the connection state can be sequentially shifted and changed at the time of connection switching, so that one column or one row of redundant data is stored in the data holding means arranged on the shifted side. If at least one holding unit is provided, there is no need to provide a redundant data holding unit for each of the plurality of data holding units. As a result, since the redundant data holding unit is not provided for each of the plurality of data holding units, the area occupied by the redundant data holding unit is greatly reduced, and the redundant data holding unit is eliminated, thereby improving the relief efficiency of the redundant data holding unit. I do.

In the first semiconductor memory device, the connection switching means is connected to each data input / output means by a predetermined number of first data lines, and each data holding means is connected to each data input / output means by the number of first data lines. Are connected by more second data lines, and are provided such that the total number of columns or total rows of the data holding units in the plurality of data holding units is equal to or greater than the second data lines. Is preferred. In this case, the difference between the number of second data lines and the number of first data lines becomes the number of redundant data holding units for one column or one row. Accordingly, when a defective portion occurs in one of the data holding units for one column or one row of the plurality of data input / output units, the data holding unit column (row) including the defective portion is stored in the data storage unit. By disconnecting the connection with the input / output means and sequentially shifting from the column (row) of the disconnected data holding section to the side where the redundant data holding section is provided, it is possible to reliably remedy a defective portion. it can.

A second semiconductor memory device according to the present invention comprises: a plurality of memory cell arrays having a plurality of memory cells arranged in a matrix; a plurality of data input / output circuits corresponding to the plurality of memory cell arrays; A connection switching circuit that switches an electrical connection state between the data input / output circuit and the plurality of memory cell arrays, a plurality of first data buses that connect the data input / output circuit and the connection switching circuit, and a connection switching circuit. A plurality of second data buses for connecting the plurality of memory cell arrays, and a plurality of first data buses, which are connected in parallel between the connection switching circuit and the data input / output circuit, and each cell column of the memory cell array; And a connection switching circuit corresponding to a plurality of first column line activation signal lines to which a column line activation signal for inputting a data transfer trigger is input and a plurality of second data buses. A first column line activation signal line selectively connected to the first column line activation signal line and a second column line activation signal line selectively connected to the first column line. And the second
The number of the column line activation signal lines is greater than that of the first column line activation signal lines, and the connection switching circuit connects each first data bus to one of the plurality of second data buses. Selectively connecting and selectively connecting each of the first column line activation signal lines to any one of the plurality of second column line activation signal lines, and corresponding to a defective column detected in the memory cell array. The connection between the first data bus and the second data bus and the connection between the first column line activation signal line and the second column line activation signal line are disconnected, and the first and second columns corresponding to the columns following the disconnected defective column are disconnected. A connection state between the first data bus and the second data bus and a connection state between the first column line activation signal line and the second column line activation signal line are provided so as to be sequentially shifted and changed in correspondence with each other. ing

According to the second semiconductor memory device, the second data bus is provided more than the first data bus connected to the data input / output circuit, and the second column line activation signal line is provided. More column lines are provided than the first column line activation signal line that receives a column line activation signal input from the outside. Further, since the connection switching circuit selectively connects each cell column included in the plurality of memory cell arrays to any one of the plurality of data input / output circuits, data transferred from the data input / output circuit includes: It is no longer limited to one of the plurality of memory cell arrays. In addition, the connection switching means is configured to connect the first data bus and the second data bus corresponding to the detected defective column and to connect the first column line activation signal line and the second column line activation signal line. The connection is cut off, the connection state of the first data bus and the second data bus corresponding to each column after the cut-off defective column, and the connection between the first column line start signal line and the second column line start signal line. Since the connection state can be sequentially shifted and changed while corresponding to each other, if at least one redundant cell column is provided in the memory cell array arranged on the shifted side, a redundant cell column is provided for each of the plurality of memory cell arrays. No need. As a result, it is not necessary to have a redundant cell column for each of the plurality of memory cell arrays, so that the area occupied by the redundant cell column is greatly reduced. improves.

In the second semiconductor memory device, the plurality of memory cell arrays are provided such that the total number of cell columns is equal to the total number of second data buses or second column line activation signal lines. The switching circuit belongs to each memory cell array and selectively connects one cell column and the other cell column among cell columns adjacent to each other, and is located on a side portion adjacent to each other in the plurality of memory cell arrays. It is preferable to have a switch changing means for selectively connecting a cell column belonging to one memory cell array and a cell column belonging to the other memory cell array among the cell columns. With this configuration, the switching changing means of the connection switching circuit selectively connects one of the cell columns adjacent to each other in the memory cell array, and selects the adjacent cell column in the memory cell arrays adjacent to each other. If one of the cell columns included in the plurality of memory cell arrays has a defective portion in order to selectively connect one of the cell columns located in the section, the cell column including the defective portion is While disconnecting the data input / output circuit,
By sequentially shifting from the disconnected cell row to the side where the redundant cell row is provided, a defective portion can be reliably relieved.

In the second semiconductor memory device, the first column line activation signal line is provided for every m number of first data buses (where m is an integer of 2 or more). Is preferred. In this case, the number of the first column line activation signal lines is 1 / m of the number of the first data buses, so that the layout area can be further reduced.

[0015]

(First Embodiment) A first embodiment of the present invention.
An embodiment will be described with reference to the drawings.

FIG. 1 shows a schematic block configuration of a semiconductor memory device according to the first embodiment of the present invention. FIG.
As shown in FIG. 1, a memory cell array 1 as a data holding means for holding a large number of data includes a memory segment 1
0 and an I / F unit 20 serving as an interface for external signals. The memory segment unit 10 includes n memory cells (not shown) each serving as a data holding unit arranged in a matrix (where n is an integer of 2 or more).
Sub-arrays 11A to 11D which are sub-blocks of
And a connection switching unit 12 as connection switching means for switching a signal path with the I / F unit 20.

A peripheral circuit of the memory cell array 1,
External input / output circuits 31A to 31D as data input / output means for controlling input / output of data with the outside are provided so as to correspond to n memory sub arrays 11A to 11D, respectively.

An address input circuit 32 receives an external address signal for specifying data in the memory cell array 1, generates a column address signal for specifying a cell column, and outputs a row address signal for specifying a cell row. Have been. A row decoder circuit 33 is provided between the address input circuit 32 and the memory cell array 10 for generating a row address decode signal from the received row address signal and outputting the signal to the memory cell array 1.

FIG. 2 shows a detailed block configuration of the memory cell array 1 according to the present embodiment. In FIG.
Components that are the same as the components shown in FIG. 1 are given the same reference numerals, and descriptions thereof will be omitted. As shown in FIG.
The / F unit 20 receives a column address signal from the address input circuit 32 shown in FIG. 1, generates a column decode signal from the received column address signal, and supplies the column decode signal to each of the memory sub-arrays 11A to 11D in the memory segment unit 10. Output column decoders 21A to 21D are provided. Here, four memory sub arrays 11A to 11A
D, and each of the memory sub-arrays 11A to 11A to
Data read from 11D passes through a data bus DB as a first data line having a bit width of 64 bits,
The data is converted into 1-bit data by the multiplexers 22A to 22D. Each converted 1-bit data is
The signals are output to the external input / output circuits 31A to 31D shown in FIG. As described above, external data output to the outside from the four external input / output circuits 31A to 31D provided in parallel is:
It is processed as 4-bit data.

FIG. 3 shows a detailed block configuration of the memory segment unit 10 according to the present embodiment. As shown in FIG. 3, the connection switching unit 12 includes the connection switching circuit 121 and the first
To 4th column line activation signal generation circuits 13A to 13D. The connection switching circuit 121 is connected to each memory sub-array 1
64 data buses D provided for each of 1A to 11D
B, and each of the memory sub arrays 11A to 11D is connected to 64 internal data buses D as second data lines.
Connected to BA. First to fourth column line activation signal generating circuits 13A each receiving a column decode signal
13D are connected to the connection switching circuit 121 and the column line activation signal lines Y each having a 64-bit width. On the other hand, the connection switching circuit 121 receiving the column line activation signal Y
To the fourth memory sub-arrays 11A to 11D and the internal column line activation signal lines YA, respectively.

As a feature of the present embodiment, the first to third memory sub-arrays 1 except for the fourth memory sub-array 11D are provided.
In 1A to 11C, 64 columns of cells accessed by column lines (= Y lines or bit lines) are arranged, and 65 columns of cells are arranged only in the fourth memory sub-array 11D. Thus, the 65th cell column of the fourth memory sub-array 11D is provided as a redundant cell column.

Therefore, as shown in FIG. 3, both the internal data bus DBA and the internal column line activation signal line YA connected to the fourth memory sub-array 11D are formed as 65-bit wide signal lines.

FIGS. 4A and 4B show a memory sub-array according to the present embodiment. FIG. 4A shows a schematic configuration of a memory sub-array having a 64-column configuration, and FIG. 3 shows a schematic configuration of a memory sub-array. FIG.
As shown in (a), in the case of the first memory sub-array 11A, each of the memory cells 111 arranged in a matrix has 64 bit lines BL (1) to BL (64).
, And one of the 128 word lines WL (1) to WL (128) that make the memory cell 111 accessible.

On the other hand, as shown in FIG. 4B, in the case of the fourth memory sub-array 11D, each memory cell 111 arranged in a matrix has 65 bit lines B
It is connected to one of L (193) to BL (257) and one of 128 word lines WL (1) to WL (128) enabling access to memory cell 111. As described above, the 65th column is the only redundant cell column 1 for repairing the defective cell column in the memory cell array 1.
1a.

Hereinafter, the operation of the semiconductor memory device configured as described above will be described.

First, the case where the redundant cell column 11a is not used will be described.

It is assumed that an address signal having a row address of 0 and a column address of 0 is output from the address input circuit 32 shown in FIG. In this case, the row decoder circuit 33 controls the word lines W shown in FIGS.
L1 is selected. On the other hand, the column decoder 2 shown in FIG.
1A to 21D, the column line activation signal lines Y in each of the column line activation signal generation circuits 13A to 13D shown in FIG.
(1), Y (65), Y (129) and Y (193) are activated. Thereby, FIG. 4 (a) and FIG. 4 (b)
Bit lines BL (1), BL (65), BL (129) of the first to fourth memory sub-arrays 11A to 11D shown in FIG.
And BL (193) are selected.

Next, the bit line BL (1) of the first memory sub-array 11A and the internal data bus DBA (1) are connected, and the bit line BL (2) of the second memory sub-array 11B is connected.
(65) and the internal data bus DBA (65) are connected, and the bit line BL (129) of the third memory sub-array is connected.
And the internal data bus DBA (129) are connected to
The bit line BL (193) of the memory sub-array 11D is connected to the internal data bus DBA (193). Thereby, the word line WL1 and each of the memory sub arrays 11A to
Bit lines BL (1), BL (65), BL in 11D
(129) and data can be input / output to / from the four memory cells 111 connected to the BL (193).

Even when another address is selected, the column switching signal Y (1-64) from the first column switching signal generating circuit 13A is switched by the connection switching circuit 121 to the internal column switching signal YA. (1 to 64) and the data bus DB (1 to 64) is also connected to the connection switching circuit 1
21, the internal data buses DBA (1-64) and 1
They are connected in a one-to-one correspondence. Similarly, the remaining column line activation signal lines Y (65-256) are internal column line activation signal lines YA.
(65-256) and the remaining data buses DB (65-256) are connected to the internal data bus DBA (65).
To 256) in a one-to-one connection.

As described above, each of the memory sub-arrays 11A-
If no failure occurs in any of the predetermined 64 cell columns and 64 bit lines in 11D, the internal column line activation signal line YA (257) and the internal data bus DBA
(257) is a column line activation signal line Y (256)
And the data bus DB (256).

Next, the data bus DB (1-256) is
The external input / output circuits 31A to 31D shown in FIG. 1 are connected via the Q multiplexers 22A to 22D. Accordingly, data access (reading and writing) can be performed between the four memory cells 111 connected to the word line WL selected by the row address and selected by the column address. In this case, the bit line BL
No access is made to the redundant cell column 11a connected to (257).

Next, when there is a defective portion in the specific memory cell 111 or the bit line BL, for example, the memory cell 111 or the bit line BL (7) connected to the bit line BL (7) of the first memory sub-array 11A. If there is a defect in the cell column (7) of the first memory sub-array 11A, the connection switching circuit 121 is programmed in advance in the product inspection step.
To rescue. Here, only the outline of the rescue programming will be described, and a description using a specific circuit configuration of the connection switching circuit 121 will be described later.

The outline of the rescue programming is as follows. For the connection switching circuit 121, the column line activation signal lines Y (1-6) are connected to the internal column line activation signal lines YA (1-6), respectively.
The column line activation signal lines Y (7-256) are connected to be shifted from the internal column line activation signal lines YA (8-257), respectively. Similarly, the data buses DB (1-6) are respectively connected to the internal data buses. DBAs (1 to 6) and the data buses DB (7 to 256)
BA (8 to 257) are connected so as to be shifted. As a result, the first external input / output circuit 31A
Of the internal data buses DBA (1 to 6, 8 to 64) connected to the memory sub-array 11A and the internal data bus DBA (65) connected to the second memory sub-array 11B. Perform The fourth external input / output circuit 31D is connected to the internal data bus DBA (19) connected to the fourth memory sub-array 11D.
4 to 257), data is transmitted and received in a total of 64 bits.

As described above, the first memory sub-array 11
The cell column (7) of A is repaired by the redundant cell column 11a including the cell column (65) of the fourth memory sub-array 11D.

As described above, according to the present embodiment, the memory sub-array 11A as a plurality of sub-blocks
11D, only one redundant cell column 11a is provided, and the connection switching circuit 121 is supplied to the internal column line activation signal line YA and the internal data bus D during product inspection.
By sequentially shifting the BA toward the redundant cell column 11a by one cell column, one cell column having a defective portion can be avoided, so that a defective semiconductor memory device can be relieved.

As described above, in the conventional redundant shift method, a redundant cell column must be provided for each sub-array corresponding to each external input / output circuit, and the bit width is increased, for example, from 4 bit width to 8 bit width. When the bit width is increased from the 8-bit width to the 16-bit width, the number of redundant cell columns must be increased by the number of external input / output circuits. As a result, the memory cells on the chip are increased. Of the cell array, and also the cell column rescue efficiency.

According to the present embodiment, only one redundant cell column 11a is provided for the four memory sub-arrays 11A to 11D.
11D and corresponding external input / output circuits 31A-3
The correspondence of data exchange with 1D is not fixed. Thereby, a part of the data in each of the memory sub arrays 11A to 11D can share the external input / output circuits adjacent to each other. Thus, each of the memory sub-arrays 11A to 11A to
11C is connected to the external input / output circuit 31A in a range adjacent to each other.
31D can be connected to the four external input / output circuits 31A to 31D, so that only one redundant cell 11a is provided for the four external input / output circuits 31A to 31D.

In the present embodiment, four external input / output circuits 31A to 31D are provided, but the number of external input / output circuits is not limited to this.

The first to fourth external input / output circuits 31A
Although the bit width of the column line activation signal line Y and the data bus DB corresponding to .about.31D is 64 bits, the invention is not limited to this.

Although the redundant cell column 11a is one column, a plurality of redundant cell columns may be provided. Two or more redundant cell columns 11a
Is provided, the bit width of the internal column line activation signal line YA and the bit width of the internal data bus
What is necessary is just to add more so as to correspond to the number of columns of 1a.

Hereinafter, the connection switching circuit according to the present embodiment will be described with reference to the drawings.

FIG. 5 shows a partial circuit configuration of the connection switching circuit in the semiconductor memory device according to the present embodiment.
The connection switching circuit 121 has first to fourth column line activation signal generation circuits 13A to 13 shown in FIG.
D is connected to a total of 256 column line activation signal lines Y (1 to 256) of 64 lines each, and is connected to the first to fourth DQ multiplexers 22A to 22D shown in FIG.
The data buses are connected to a total of 256 data buses DB (1 to 256). Also, as shown in FIG. 3, the first to third memory sub-arrays 11A to 11A
C is a total of 192 internal column line activation signal lines YA (1 to 192) each of 64 and a total of 192 internal data buses DBA (1 to 192) of 64 each.
And the fourth memory sub-array 11D is connected to 65 internal column line activation signal lines YA (193-2
57) and 65 internal data buses DBA (193-2)
57).

FIG. 5 shows four column line activation signal lines Y (1 to 4) and five internal column line activation signal lines YA.
(1-5) Only four data buses DB (1-4) and five internal data buses DBA (1-5) are shown. Here, as shown in FIG. 5, for convenience, the first two sets will be described as a first switching block 401 and a second switching block 402, respectively. Therefore, the connection switching circuit 1
Reference numeral 21 includes 256 switching blocks.

The first switching block 401 has a drain connected to the column line activation signal line Y (1), a source connected to the internal column line activation signal line YA (1), and a gate indicating the result of the rescue programming. A first NMOS transistor 41 that receives a first switching control signal, a drain is connected to the column line activation signal line Y (1), a source is connected to the internal column line activation signal line YA (2), and a gate is relieved. A second NMOS transistor 42 receiving a second switching control signal indicating a result of programming; a drain connected to the data bus DB (1); a source connected to the internal data bus DBA (1); , A drain connected to the data bus DB (1), and a source connected to the internal data bus DBA (2). It is connected to a gate and a fourth NMOS transistor 44 which receives the second switching control signal. The first switching control signal is output from the first inverter 4
5 is generated through a fuse element 46 serving as a switching change unit that is in a conductive state, and a second switching control signal is generated by the second inverter 47 by the first switching control signal. Generated inverted. The first and second switching control signals are supplied to the third inverter 48 whose input terminal is connected to the output terminal of the second inverter 47 and whose output terminal is connected to the input terminal of the second inverter 47. The potentials of the first and second switching control signals are latched.

The fifth NMOS transistor 4 has a source grounded, a gate receiving an initialization signal from the reset circuit 50, and a drain outputting a first switching control signal.
9. Thus, by activating the fifth NMOS transistor 49 only during a predetermined time when the device is initialized, the potentials of the first and second switching control signals are determined to be high or low.

As shown in FIG. 5, the second switching block 4
02 has the same configuration, the output of the first NMOS transistor 41 in the second switching block 402 is connected to the internal column line activation signal line YA (2), and the third NMOS in the second switching block 402 Transistor 43
Are connected to the internal data bus DBA (2). As a result, the internal column line activation signal line YA (2) and the internal data bus DBA (2) become a common part shared with the first switching block 401. Similarly, the internal column line activation signal line YA (3) and the internal data bus DBA
(3) is a common part with the third switching block, though not shown. Therefore, the internal column line activation signal line YA
(256) and an internal data bus DBA (256).

The operation of the connection switching circuit 121 configured as described above will be described below.

First, a case where there is no defective portion in each of the cell columns and the bit lines of the first to fourth memory sub-arrays 11A to 11D shown in FIG. 3 will be described.

In this case, since the fuse element 46 in the first switching block 401 shown in FIG. 5 is not trimmed (blown), the first switching control signal is latched at a high level potential, and the second switching control signal is latched at the second level. The switching control signal is latched at a low level potential. Thereby, the first NMOS
The transistor 41 becomes conductive and the second NMOS
Since transistor 42 is turned off, column line activation signal line Y (1) and internal column line activation signal line YA (1) are connected. Similarly, the third NMOS transistor 4
3 becomes conductive and the fourth NMOS transistor 4
4 is turned off, so that data bus DB (1) and internal data bus DBA (1) are connected.

Similarly, in the second switching block 402, since the fuse element 46 is not trimmed, the column line activation signal line Y (2) and the internal column line activation signal line YA (2) are connected. With the data bus DB
(2) and the internal data bus DBA (2) are connected.
As a result, the last internal column line activation signal line YA (257)
And the internal data bus DBA (257) remains unused.

Next, as an example, a case where a defective portion exists only in the cell column (1) or the bit line of the first memory sub-array 11A will be described.

In this case, in the product inspection process, the fuse element 46 in the first switching block 401
It is trimmed beforehand by laser irradiation or the like. Therefore, the first switching control signal is latched at a low level which is the potential at the time of initialization, and conversely, the second switching control signal is latched at a high level potential. As a result, the first NMOS transistor 41 is turned off and the second NMOS transistor 41 is turned off.
NMOS transistor 42 is turned on, so that column line activation signal line Y (1) and internal column line activation signal line YA
(2) is connected. Similarly, since the third NMOS transistor 43 is turned off and the fourth NMOS transistor 44 is turned on, the data bus DB
(1) and the internal data bus DBA (2) are connected.

Similarly, in the second switching block 402, the first switching control signal is set to the low level potential,
Are respectively latched at the high level potential, the column line activation signal line Y (2) and the internal column line activation signal line YA (3) are connected, and the data bus D
B (2) and the internal data bus DBA (3) are connected.

Thus, the last column line activation signal line Y
(256) is connected to the internal column line activation signal line YA (257), and the data bus DB (256) is connected to the internal data bus DBA (257). As a result, FIG.
Cell column (1) of the first memory sub-array 11A shown in FIG.
Is the cell column (65) of the fourth memory sub-array 11D.
(= Redundant cell column 11a).

As described above, according to the connection switching circuit 121 according to this embodiment, even between different memory sub-arrays, each internal column line activation signal line YA and each internal data bus DBA are sequentially placed on the redundant cell 11a side. Connection switching that switches simultaneously while shifting can be reliably performed.

(Second Embodiment) Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.

FIGS. 6 and 7 show a semiconductor memory device according to a second embodiment of the present invention. FIG. 6 shows a block configuration of a memory segment portion, and FIG. 7 shows a fourth memory sub-array having a 68-column configuration. 1 shows a schematic configuration of the embodiment. 6, the same components as those shown in FIG. 3 are denoted by the same reference numerals, and description thereof will be omitted. As shown in FIG. 6, the column line activation signal lines Y (1 to 16) extending from the first column line activation signal generating circuit 13A according to the present embodiment have a data width of 16 bits. Therefore, the first column line activation signal generating circuit 13A is connected to the 64-bit data bus DB extending from the first DQ multiplexer 22A.
Four bits (1 to 64), that is, four bit lines are controlled by one bit. The same applies to the second to fourth column line activation signal generation circuits 13B to 13D.

With this configuration, for example, the column line activation signal line Y (1) is selectively connected to the internal column line activation signal line YA (1) or the internal column line activation signal line YA (2), Bus DB (1 to 4) and internal data bus D
BA (1 to 4) or the internal data bus DBA (5 to 8) are selectively connected.

As shown in FIGS. 6 and 7, the fourth memory sub-array 11D has four cell columns (65 to 6).
8) as the redundant cell column group 11b.

FIGS. 8 and 9 show the switching connection circuit 122 according to the present embodiment. FIG. 8 shows the circuit configuration of the internal data bus selector, and FIG. 9 shows the circuit configuration of the bit line selector. . As shown in FIG. 8, the internal data bus selection unit 12
2a denotes four column line activation signal lines Y (1 to 4), five internal column line activation signal lines YA (1 to 5), 16 data buses DB (1 to 16) and 20 internal Only the data bus DBA (1 to 20) is shown. Here, as shown in FIG. 8, for convenience, the first two sets will be described as a first switching block 501 and a second switching block 502, respectively. Therefore, the connection switching circuit 122 includes 64 switching blocks.

In the first switching block 501, the drain is connected to the column line activation signal line Y (1), the source is connected to the internal column line activation signal line YA (1), and the gate indicates the result of the rescue programming. A first NMOS transistor 51 receiving the first switching control signal, a drain is connected to the column line activation signal line Y (1), a source is connected to the internal column line activation signal line YA (2), and a gate is relieved. A second NMOS transistor 52 receiving a second switching control signal indicating a result of programming; a drain connected to the data bus DB (1); a source connected to the internal data bus DBA (1); and a gate connected to the first data bus DBA (1) , A drain connected to the data bus DB (1), and a source connected to the internal data bus DBA (5). It is connected to a gate and a fourth NMOS transistor 54 which receives the second switching control signal. Further, third and fourth transistors 53,
54, which is connected to the data bus DB (2), and has an internal data bus (2) and an internal data bus (6).
And the fifth transistor 5 to select and connect
Fifth and 56, seventh and eighth transistors 57 and 58 which are connected to the data bus DB (3) and select and connect the internal data bus (3) and the internal data bus (7); It has ninth and tenth transistors 59 and 60 that are connected to (4) and select and connect the internal data bus (4) and the internal data bus (8).

The first switching control signal is generated via the fuse element 62 in which the high-level potential generated by the first inverter 61 is conductive, and the second switching control signal is generated by the first switching control signal. The control signal is generated by being inverted by the second inverter 63. The first and second switching control signals are supplied to a third inverter 64 whose input terminal is connected to the output terminal of the second inverter 63 and whose output terminal is connected to the input terminal of the second inverter 63. The potentials of the first and second switching control signals are latched.

Further, the source is grounded, the gate receives the initialization signal from the reset circuit 50, outputs the first switching control signal to the drain, and sets the potentials of the first and second switching control signals at initialization. An eleventh NMOS transistor 65 that can be determined is provided.

As shown in FIG. 8, the second switching block 5
02 has the same configuration. Thereby, the internal column line activation signal line YA (2) and the internal data bus DBA
(5) The internal data bus DBA (6), the internal data bus DBA (7) and the internal data bus DBA (8)
Is a common part shared by the switching block 501 of FIG. As described above, the common portion is formed up to the internal column line activation signal line YA (64) and the internal data bus DBA (253 to 256), and it is possible to realize a configuration in which the components are sequentially shifted and connected as described above. I have.

Next, the bit line selection section 122b will be described.

As shown in FIG. 9, here, the first internal column line activation signal line YA (1) of the 65 internal column line activation signal lines YA (1 to 65) and 260 internal column line activation signal lines YA (1 to 65) are connected. Only the first to fourth internal data buses DBA (1 to 4) of the data buses DBA (1 to 260) are shown.

The partial circuit of the bit line selection section 122b which receives the internal column line activation signal line YA (1) has a gate connected to the internal column line activation signal line YA (1) from the internal data bus selection section 122a. Receiving and draining the internal data bus D from the internal data bus selecting unit 122a.
First NMOS transistor 7 connected to BA (1)
1, the gate of which receives the output of the bit line selection circuit 70, the drain of which is connected to the source of the first NMOS transistor 71, and the source of which is connected to the bit line BL (1) of the first memory sub-array 11A. NMOS transistor 72. Also, the internal data bus DBA
The state of connection between (2) and the bit line BL (2) is controlled, and the third NMOS transistor 73 connected in parallel with the first NMOS transistor 71 and the fourth NMOS connected in parallel with the second NMOS transistor 72. NMOS transistor 74, internal data bus DBA (3) and bit line BL
(3), a fifth NMOS transistor 75 connected in parallel with the first NMOS transistor 71, a sixth NMOS transistor 76 connected in parallel with the second NMOS transistor 72, and internal data. A connection state between the bus DBA (4) and the bit line BL (4) is controlled, and a seventh NMOS transistor 77 and a second NMOS connected in parallel with the first NMOS transistor 71 are provided.
An eighth NMOS transistor 78 is connected in parallel with the transistor 72.

Further, ninth to twelfth NMOSs each having a gate receiving the read operation signal 80 and connecting each internal data bus (1 to 4) to each bit line BL (1 to 4).
It has transistors 81 to 84. Here, the read operation signal 80 is common to the bit line selection unit 122b, and the bit line selection circuit 70 is provided corresponding to each of the column decoders 21A to 21D shown in FIG.

According to this configuration, at the time of the read operation,
Since both the output signal from the bit line selection circuit 70 and the read operation signal 80 are at the high level, all of the four bit lines BL (1 to 4) are connected to the internal data bus DBA (1).
To 4). Therefore, the bit line selection unit 122
In b, selection by a column address is not performed,
Instead, it is selected bit by bit in the DQ multiplexer 22A shown in FIG.

At the time of the write operation, the read operation signal 8
Since 0 has transitioned to the low level, only the bit line BL selected by the internal column line activation signal line YA (1) and the output signal from the bit line selection circuit 70 is connected to the internal data bus DBA. In addition, data can be written only to one selected bit line BL.

Hereinafter, the operation of the semiconductor memory device having the switching connection circuit 122 configured as described above will be described.

First, the case where there is no defective portion in each of the cell columns and the bit lines of the first to fourth memory sub-arrays 11A to 11D shown in FIG. 5 will be described.

In this case, as in the first embodiment, since the fuse element 62 in the first switching block 501 shown in FIG. 8 is not trimmed, the first switching control signal is latched at a high-level potential. Then, the second switching control signal is latched at a low-level potential. This allows
Since the first NMOS transistor 51 is turned on and the second NMOS transistor 52 is turned off, the column line activation signal line Y (1) and the internal column line activation signal line YA (1) are connected. . Similarly, the third, fifth, seventh, and ninth NMOS transistors 53, 55, 57,
59 becomes conductive and the fourth, sixth, eighth and tenth
NMOS transistors 54, 56, 58, and 60 are turned off, so that data buses DB (1 to 4) and internal data buses DBA (1 to 4) are connected.

Thus, the last internal column line activation signal line YA (65) and internal data bus DBA (257 to 26)
0) remains unused.

Next, for example, it is assumed that a defective portion exists only in the cell column (1) or the bit line of the first memory sub-array 11A.

Also in this case, in the product inspection process, the fuse element 62 in the first switching block 501
It is already trimmed. Therefore, the first switching control signal is latched at a low level potential, and the second switching control signal is latched at a high level potential. As a result, the first NMOS transistor 51 is turned off and the second NMOS transistor 52 is turned on, so that the column line activation signal line Y (1) and the internal column line activation signal line YA (2) are connected. Connected. Similarly, the third, fifth, seventh, and ninth NMOS transistors 53, 55,
57, 59 become non-conductive and the fourth, sixth, eighth, and tenth NMOS transistors 54, 56, 58, 6
Since 0 is conductive, the data buses DB (1 to 4) and the internal data buses DBA (5 to 8) are connected.

As a result, the last column line activation signal line Y
(64) is connected to the internal column line activation signal line YA (65), and the data bus DB (253 to 256) is connected to the internal data bus DBA (257 to 260). As a result, FIG. The cell columns (1 to 4) of the first memory sub-array 11A shown are relieved by the cell columns (65 to 68) (= redundant cell column 11b) of the fourth memory sub-array 11D.

As described above, according to the present embodiment, the connection switching of the four data buses DB (1 to 256) is performed simultaneously, so that the efficiency of repairing the defective bit line is reduced, but the column line activation signal line Y ( 1-64) is only a quarter of the number. Further, since only one fuse element 62 having a relatively large element area is required for four data buses DB, the layout area can be significantly reduced and a relief circuit with high relief efficiency can be realized.

In this embodiment, four data buses DB and four redundant cell columns are provided for each column line activation signal line Y. However, the present invention is not limited to this.

[0080]

According to the semiconductor memory device of the present invention,
Since the connection switching means is provided so that the connection state can be sequentially shifted and changed for each column after the defective column detected in the memory cell array, the data holding means arranged on the shifted side If at least one redundant data holding unit for one row is provided, it is not necessary to provide a redundant data holding unit for each of a plurality of data holding units. Therefore, it is not necessary to have a redundant data holding unit for each of the plurality of data holding units, so that the area occupied by the redundant data holding unit is greatly reduced, and no redundant redundant data holding unit is used. Efficiency is improved.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram showing a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a memory cell array of the semiconductor memory device according to the first embodiment of the present invention.

FIG. 3 is a block diagram showing a memory segment unit of the semiconductor memory device according to the first embodiment of the present invention.

FIGS. 4A and 4B show a memory sub-array of the semiconductor memory device according to the first embodiment of the present invention, and FIG.
FIG. 2 is a schematic configuration diagram showing a memory sub-array having no redundant cell column, and FIG. 2B is a schematic configuration diagram showing a memory sub-array having a redundant cell column.

FIG. 5 is a partial circuit diagram illustrating a connection switching circuit in the semiconductor memory device according to the first embodiment of the present invention.

FIG. 6 is a block diagram showing a memory segment unit of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 7 is a schematic configuration diagram showing a memory sub-array having a plurality of redundant cell columns in a semiconductor memory device according to a second embodiment of the present invention.

FIG. 8 is a partial circuit diagram showing an internal data bus selection unit of a connection switching circuit in a semiconductor memory device according to a second embodiment of the present invention.

FIG. 9 is a partial circuit diagram illustrating a bit line selection unit of a connection switching circuit in a semiconductor memory device according to a second embodiment of the present invention.

[Explanation of symbols]

Reference Signs List 1 memory cell array (data holding means) 10 memory segment section 11A (first) memory sub-array 11B (second) memory sub-array 11C (third) memory sub-array 11D (fourth) memory sub-array 111 memory cell (data holding) Unit) 11a redundant cell column 11b redundant cell column group 12 connection switching unit (connection switching unit) 121 connection switching circuit 122 connection switching circuit 122a internal data bus selection unit 122b bit line selection unit 13A first column line activation signal generation circuit 13D Fourth column line activation signal generation circuit 20 I / F unit 21A First column decoder 21D Fourth column decoder 22A First DQ multiplexer 22D Fourth DQ multiplexer 31A First external input / output circuit 31D Fourth External input / output circuit 32 address input times 33 row decoder circuit DB data bus (first data line / first data bus) DBA internal data bus (second data line / second data bus) Y column line activation signal line (first column line activation) YA Internal column line activation signal line (first internal column line activation signal line) 401 First switching block 402 Second switching block 41 First NMOS transistor 42 Second NMOS transistor 43 Third NMOS Transistor 44 Fourth NMOS transistor 45 First inverter 46 Fuse element (switch changing means) 47 Second inverter 48 Third inverter 49 Fifth NMOS transistor 50 Reset circuit 501 First switch block 502 Second switch Block 51 First NMOS transistor 52 Second NMOS transistor Transistor 53 third NMOS transistor 54 fourth NMOS transistor 55 fifth NMOS transistor 56 sixth NMOS transistor 57 seventh NMOS transistor 58 eighth NMOS transistor 59 ninth NMOS transistor 60 tenth NMOS transistor 61 First inverter 62 Fuse element (switch changing means) 63 Second inverter 64 Third inverter 65 Eleventh NMOS transistor 70 Bit line selection circuit 71 First NMOS transistor 72 Second NMOS transistor 73 Third NMOS Transistor 74 Fourth NMOS transistor 75 Fifth NMOS transistor 76 Sixth NMOS transistor 77 Seventh NMOS transistor 78 Eighth NMOS transistor 8 Read operation signal 81 the ninth NMOS transistor 82 a 10 NMOS transistor 83 a 11 NMOS transistor 84 twelfth NMOS transistor of

Claims (5)

[Claims] A plurality of data holding units having a plurality of data holding units arranged in a matrix; a plurality of data input / output units corresponding to the plurality of data holding units; a plurality of data holding units; Connection switching means for switching an electrical connection between a plurality of data input / output means, wherein the connection switching means includes a plurality of data holding units for one row or one row included in the plurality of data holding means. A semiconductor memory device which is selectively connected to any one of the data input / output means, and is provided so that the connection state can be sequentially shifted and changed when the connection is switched. 2. The connection switching unit is connected to each of the data input / output units by a predetermined number of first data lines, and is connected to each of the data holding units by a number greater than the number of the first data lines. The plurality of data holding units are connected so that the total number of columns or total number of rows of the data holding units in the plurality of data holding units is equal to or greater than that of the second data lines. 2. The semiconductor memory device according to claim 1, wherein: A plurality of memory cell arrays having a plurality of memory cells arranged in a matrix; a plurality of data input / output circuits corresponding to the plurality of memory cell arrays; a plurality of data input / output circuits; A connection switching circuit for switching an electrical connection state with a memory cell array; a plurality of first data buses connecting the data input / output circuit and the connection switching circuit; a connection switching circuit and the plurality of memories A plurality of second data buses connecting the cell array; and a plurality of second data buses connected in parallel between the connection switching circuit and the data input / output circuit corresponding to the plurality of first data buses, wherein each cell of the memory cell array is A plurality of first column line activation signal lines to which a column line activation signal for triggering data transfer to a column is input; and a plurality of second data buses. A second column line activation signal line, which is connected in parallel between the connection switching circuit and the cell column, and is selectively connected to the first column line activation signal line; The number of the second column line activation signal lines is greater than that of the first column line activation signal line, and the number of the second column line activation signal lines is greater than that of the first column line activation signal line. The connection switching circuit selectively connects each of the first data buses to any one of the plurality of second data buses and connects each of the first column line activation signal lines to the plurality of second columns. And selectively connecting to any one of the line activation signal lines, a connection between the first data bus and the second data bus corresponding to a defective column detected in the memory cell array, and the first column Line start signal line and front 2nd
And the connection state of the first data bus and the second data bus corresponding to each column after the disconnected defective column, and the first column line activation signal. A semiconductor memory device provided so as to be able to sequentially shift and change the connection state between a line and the second column line activation signal line while making them correspond to each other. 4. The plurality of memory cell arrays are provided such that the total number of the cell columns is equal to the total number of the second data buses or the second column line activation signal lines. The circuit selectively connects one of the cell columns belonging to each of the memory cell arrays and the cell column adjacent to each other and the other cell column, and opposes side portions of the plurality of memory cell arrays adjacent to each other. And a switching unit for selectively connecting a cell column belonging to one memory cell array and a cell column belonging to the other memory cell array among the cell columns located in the memory cell array. 13. The semiconductor memory device according to claim 1. 5. The method according to claim 1, wherein the first column line activation signal line is provided for every m lines of the plurality of first data buses (where m is an integer of 2 or more). The semiconductor memory device according to claim 3, wherein: