JP2001086169A - Modem - Google Patents

Abstract

PROBLEM TO BE SOLVED: To surely transmit asynchronous input data by judging start and stop bits, temporarily storing input data and adding the start and stop bits to data in the case of a modulation output by a clock synchronization system. SOLUTION: A program incorporating CPU 32 identifies the start and stop bits concerning asynchronous (start-stop synchronous) system data which are inputted from a base station 4, inputs them by the asynchronous system, temporarily stores them and outputs them to a clock incorporating modem substrate 31 as transmission data of the clock synchronization system by synchronization with a clock from a clock incorporating modem substrate 31. The transmission data line normally transmits High (1) and decreases it to be Lo (0) as a data transmission signal when data are transmitted. It is adopted as the start bit in the asynchronous system, data 1 byte (8 bit) is transmitted in accordance with the clock from a succeeding timing, High (1) is decreased to be Lo (0) in the succeeding clock to transmit the stop bit by the asynchronous system and, then, High (1) is obtained again.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a modem used in a train radio system and the like, and more particularly to a modem capable of reliably transmitting asynchronous input data in a clock synchronous manner.

[0002]

2. Description of the Related Art A conventional clock-synchronous modem or a modem set to the clock-synchronous system assumes that clock-synchronous data generated in accordance with a clock is input, and the input data is used as the clock. Sampling, modulation and transmission are performed according to the same external or internal clock.

For example, as shown in FIG. 9, when input data is sampled at the same rising edge of a clock as the input side and a start bit is detected, 8-bit data is detected, modulated, and transmitted in accordance with the clock timing thereafter. Was. FIG. 9 is an explanatory diagram showing a sampling method of the clock synchronization method.

[0004] Incidentally, as a technology relating to synchronous / asynchronous and asynchronous / synchronous in data transmission, in 1998 (199)
8) Japanese Patent Application Laid-Open No. 10-271538, published on Oct. 9, 2008, "Data transmission method between telephone devices and telephone devices usable for the same" (Applicant: Fujitsu Eye Network Systems Ltd., Inventor: Tomoo Matsubara) There is. In the above invention, when data is transmitted between a plurality of telephone devices via a digital interface, synchronous-asynchronous conversion of synchronous communication data is performed, and the data is transmitted as start-stop synchronous transmission data.
Asynchronous reception data is asynchronous-to-synchronous conversion to be synchronous reception data.

[0005]

However, in a conventional clock synchronous modem, when asynchronous (start-stop synchronous) data is input, sampling is performed by the operation of the conventional clock synchronous method. As shown in FIG. 10, there is a possibility that sampling timing does not match, data detection cannot be performed, and an indeterminate portion occurs, data may be missed, and asynchronous input data cannot be reliably transmitted in clock synchronization. There was a problem. FIG.
0 is an explanatory diagram showing a case in which start-stop synchronization data is sampled by a clock synchronization sampling method.

As a method of connecting asynchronous terminals in a synchronous manner, a method of arranging a synchronous / asynchronous interface converter between a terminal and a modem is known. In addition, there is a problem that the configuration becomes complicated and the cost increases.

The present invention has been made in view of the above circumstances, and has as its object to provide a modem that can reliably transmit asynchronous input data in a clock synchronous manner.

[0008]

According to the present invention, in order to solve the above-mentioned problems of the prior art, in a modem, a demodulation means inputs a modulation signal, demodulates with a clock included in the modulation signal, and outputs demodulated data. And outputs a clock, and the asynchronous / synchronous conversion means determines the start bit and the stop bit for the data from the asynchronous terminal, temporarily stores the input data, and stores the start bit and the stop bit in the stored data. In addition, transmission data synchronized with the clock supplied from the demodulation means is output, and the modulation means modulates the demodulation data from the demodulation means or the transmission data from the asynchronous / synchronous conversion means and sends out a modulation signal. Asynchronous data can be transmitted in a synchronous manner.

[0009]

Embodiments of the present invention will be described with reference to the drawings. Note that the function realizing means described below may be any circuit or device as long as the function can be realized, and some or all of the functions may be realized by software. is there. Further, the function realizing means may be realized by a plurality of circuits, or the plurality of function realizing means may be realized by a single circuit.

A modem according to the present invention determines a start bit and a stop bit for data from an asynchronous terminal, temporarily stores input data, and modulates and outputs data in a clock synchronous manner. A start bit and a stop bit are added to the synchronous communication environment, and an asynchronous terminal can be connected to the synchronous communication environment to perform reliable data transfer.

FIG. 1 is a block diagram showing a connection system of a train radio system using a modem according to an embodiment of the present invention. As shown in FIG. 1, a train radio system using a modem according to the present embodiment has a central control unit (Master Equipment: M) that manages and controls the entire train radio system.
E) 1, a single modem (Single Modem: SM) 2 that connects to the central control device 1 or the base station 4 to perform data transmission with another modem, and connects to the base station 4 and other modems. A multimodem (MM) 3 for performing data transmission between two modems, a portable device as a wireless base station,
Base station that communicates with train radios (Base Station: B
S) 4).

Here, the communication between the central control unit 1 and the single modem 2, between each multi-modem 3 and the base station 4, and between the single modem 2 and the base station 4 is, for example, RS4.
22 or RS232C serial interface, and input / output data in an asynchronous (start-stop synchronization) method. Further, between the single modem 2 and the multi-modem 3 and between the multi-modem 3, for example, a four-wire 600
It is assumed that they are connected in a Ω balanced type and transmitted in a clock synchronous system.

Therefore, each single modem 2 and each multi-modem 3 input / output data to / from the central control unit 1 or the base station 4 in an asynchronous manner, and transmission between the modems must be performed in a clock synchronous manner. There is.

[0014] In the multi-modem according to the embodiment of the present invention, the asynchronous / synchronous conversion means determines the start bit and the stop bit for the data from the asynchronous terminal, and temporarily stores the input data. A start bit and a stop bit are added to data, and transmission data synchronized with the clock supplied from the demodulation means is output. Therefore, asynchronous data is transmitted in a synchronous manner, and an asynchronous terminal is connected to a synchronous communication environment. Thus, reliable data transfer can be performed.

The configuration of the modem according to the embodiment of the present invention will be described with reference to FIG. 2 in the case of a multi-modem. FIG. 2 is a block diagram showing a schematic configuration of the multi-modem according to the embodiment of the present invention. The multi-modem 3 according to the embodiment of the present invention includes a modem board 31 with a built-in clock and a CPU 32 with a built-in program. Here, the modem board 31 with a built-in clock corresponds to the demodulating means and the modulating means in the claims,
The PU 32 corresponds to an asynchronous / synchronous conversion unit.

The modem board 31 with a built-in clock realizes a conventional clock synchronous modem function. Specifically, the transmission data transmitted from the central control device 1 is forward (in FIG. 1, the central control device 1 side is forward,
The clock signal is received and demodulated by a clock-synchronous system from a modem having the opposite side (rear side), output to the base station 4 as received data, and modulated again by the clock-synchronous system and transmitted to the subsequent modem.

The reason why the demodulated received data can be directly output to the asynchronous base station 4 is that the start / stop bits of the asynchronous system are added before and after the transmission data in the clock synchronous system. This is because data is transmitted. Since the clock for demodulation follows the reception timing (RT), the reception speed at the base station 4 is:
Must be set in advance.

Conversely, the transmission data from the following modem is received and demodulated once in the clock synchronous system, and is modulated together with the clock synchronous transmission data output from the program built-in CPU 32 to be transmitted to the preceding modem. I do.
At this time, a clock for synchronization used at the time of demodulation is supplied to the CPU 32 with a built-in program.

The CPU 32 with built-in program inputs the data of the asynchronous (start-stop synchronization) system inputted from the base station 4 in the asynchronous system by discriminating the start / stop bits, temporarily stores the data, and temporarily stores the data.
The data is output to the clock built-in modem board 31 as transmission data of the clock synchronous system in synchronization with the clock signal from the external device.

Here, in order to input the data of the start-stop synchronization method from the base station 4, the output speed from the base station 4 and the input speed in the CPU 32 with a program must be set in advance. It is not necessary to match the speed with the transfer speed of the clock synchronous system.

A transmission data line from the CPU 32 with built-in program to the modem board 31 with built-in clock always transmits High (1) and drops to Lo (0) as a data transmission signal when transmitting data. The modem board 31 with a built-in clock is informed that data is to be sent. That is, this becomes the start bit in the asynchronous system, and from the next timing, 1 byte (8 bits) of data is transmitted in synchronization with the clock,
Further, at the next clock, the stop bit is dropped to Lo (0), the stop bit in the asynchronous system is transmitted, and the bit returns to High (1).

Next, the inside of the program built-in CPU 32 will be described with reference to FIG. FIG. 3 is a block diagram showing a configuration in the CPU with a built-in program of the modem of the present invention. The CPU 32 with a built-in program according to the present invention includes a transmission processing unit 35, an input processing unit 36, an interruption unit 37.
And an input ring buffer 38.

The input ring buffer 38 is a buffer for temporarily storing start-stop synchronization input data from the base station 4.
This is a program-like RAM area. The input ring buffer 38 stores a DTR flag (for example, 1
byte), GET pointer (for example, 1 byte), and PUT
A pointer (for example, 1 byte) and data (for example, 1 byte ×
n). FIG. 4 is a format diagram showing the configuration of the input ring buffer of the CPU with a built-in program of the modem of the present invention.

The DTR (Data Terminal Ready) flag is a flag for notifying the other party whether or not the terminal is in a transmittable state. In this example, the terminal receives data of start-stop synchronization from the base station 4 and receives an input ring buffer. 38 is a flag for determining whether or not data has been stored in 38 and whether or not the data can be transmitted. Specifically, it is set to 1 (ON) when there is data to be transmitted, and set to 0 (OFF) when there is no data to be transmitted, but may be reversed.

The GET pointer is input ring buffer 3
8 is a pointer indicating an address from which data is to be read. The PUT pointer is a pointer indicating an address at which data is to be stored in the input ring buffer 38.

The data is a ring-shaped buffer in which data is stored in order from data 1 and, when data n is stored, the next address is the head (data 1).

The input processing means 36 is asynchronous (start-stop synchronization)
Processing means for inputting the data of the method in an asynchronous manner,
More specifically, it receives start-stop synchronization data input from the base station 4, determines start / stop bits, and stores the input data in the input ring buffer. The input from the base station 4 is detected by detecting a start bit. Further, the output speed from the base station 4 and the input speed in the input processing means 36 need to be set in advance.

The specific processing operation of the input processing means 36 will be described with reference to FIG. FIG. 5 is a flowchart showing the operation of the input processing means of the CPU with a built-in program according to the present invention. The input processing performed by the input processing means of the CPU with a built-in program of the present invention is started when there is an input from the base station 4, and stores data one byte at a time while advancing the PUT pointer to the input ring buffer 38 (10
0) When the storage is completed, the DTR flag is set to ON (data is present), and the input processing ends.

The transmission processing means 35 is a processing means for transmitting data of the clock synchronous system. More specifically, the transmission processing means 35 reads data from the input ring buffer 38, adds a start / stop bit thereto, and 3
1 and output in synchronization with the clock supplied from 1. Since only the data is stored in the input ring buffer 38, an asynchronous start bit and a stop bit are added before and after the data so that the transmission data can be directly received by the asynchronous terminal. It is designed to send data.

The specific processing operation of the transmission processing means 35 will be described with reference to FIG. FIG. 6 is a flowchart showing the operation of the transmission processing means of the CPU with a built-in program according to the present invention. The transmission processing performed by the transmission processing means 35 of the CPU with a program according to the present invention includes an input ring buffer 38.
The presence / absence of data is determined by the DTR flag of (200),
When the DTR flag is ON and there is data to be transmitted (Y
es) performs transmission processing of clock synchronous data (20).
2).

Here, the transmission processing of the clock synchronous data specifically means that one byte of data is read from the address pointed to by the GET pointer of the input ring buffer 38 and, for example, the clock is read in accordance with the clock from the modem board 31 with a built-in clock. When the clock rises, first the start bit is output as transmission data to the modem board 31 with built-in clock, then the read data is output bit by bit to the modem board 31 with built-in clock as transmission data, and finally the stop bit is set. This is a process in which the GET pointer is advanced by one after being output to the clock built-in modem board 31 as transmission data.

Then, it is determined whether there is next transmission data (204). If there is (Yes), the process returns to step 2020 and repeats. It should be noted that whether or not there is next transmission data is determined by comparing the value of the GET pointer with the value of the PUT pointer, and if they are the same, it can be determined that there is no transmission data.

If there is no transmission data in the process 204 (No), the DTR flag is set to OFF (2).
06), the transmission processing of the transmission processing means 35 ends. In the process 200, if the DTR flag is OFF and there is no data to be transmitted (No), the transmission process of the mark bit is performed (210), and the transmission process of the transmission processing unit 35 ends.

Here, the transmission processing of the mark bit means that the CPU 32 with built-in program sends the modem board 3 with built-in clock.
This is a process of setting the transmission data line to High (1) to notify that there is no data to be transmitted.

The start timing of the transmission processing performed by the transmission processing means 35 is normally started at regular intervals, and when data is stored in the input ring buffer 38, an interrupt means described later is used. 37, it is assumed to be activated by an interrupt.

The interrupting means 37 includes a transmission processing means 35
And an input processing means 36 for performing an interrupt process. In particular, the processing 202 in the transmission processing means 35
The interrupt to the clock synchronous data transmission process is given the highest priority, and the transmission processing means is designed to prevent the data in the input ring buffer 38 from being overwritten with new start-stop synchronous data before being transmitted as clock synchronous data. 35
The execution of the processing is adjusted between the input processing means 36 and the input processing means 36.

Specifically, D of the input ring buffer 38
The TR flag is monitored, and when turned on, the input processing of the input processing means 36 is interrupted, the transmission processing means 35 is preferentially activated, and control is returned to the input processing means 36 when the transmission processing is completed. It has become. This prevents a situation in which the data in the input ring buffer 38 is overwritten with new start-stop synchronization data before being transmitted as clock synchronization data.

Next, a specific configuration example of the modem according to the embodiment of the present invention will be described with reference to FIG. 7 in the case of a multi-modem. FIG. 7 is a circuit diagram showing a specific configuration example of the multi-modem of the present invention. In FIG. 7, SIO
The I / F portion corresponds to the CPU 32 with a built-in program, and RD (Receive Data) of the card modems A1, A2 and A2.
AND that integrates terminal output and output from SIO I / F
The (logical product) circuit portion corresponds to the modem board 31 with a built-in clock. Here, the card modems A1 and A2 are general card modems that implement a clock synchronous modem function.

RS422 interface J2 or RS
Asynchronous (start-stop synchronization) data input from the H.232C interface J1 is discriminated in the SIO I / F, where the start / stop bits are determined and temporarily stored, and the start / stop bits for the asynchronous system are added. Clock synchronization is performed in accordance with the clock supplied from the card modem A2 and output as transmission data.
Input to the ND circuit.

In FIG. 7, the RT of the card modem A2
(Receive Timing) Use terminal output as clock
Supply to I / F. The clock of the RT terminal output is
The clock timing is generated according to the clock timing included in the received data received by the card modem A2.

On the other hand, the data received from the subsequent modem is
In the card modem A2, demodulation is once performed using RT (Receive Timing) as a clock, output from the RD terminal,
An AND circuit performs an AND operation on the clock-synchronous transmission data output from the SIO I / F, inputs the SD data to the SD terminal of the card modem A1, modulates the output, outputs the output from the SOUT terminal, and transmits the output to the modem ahead. It has become.

The data received from the modem in front is
The signal is demodulated in the card modem A1, output as it is to the RS422 interface J2 or the RS232C interface J1 as it is, and is input to the SD terminal of the card modem A2, modulated, output from the SOUT terminal, and transmitted to the subsequent modem. It is supposed to be.

Next, the operation of the modem according to the embodiment of the present invention will be described with reference to FIGS. In the multi-modem according to the embodiment of the present invention, asynchronous (start-stop synchronization) type data from the base station 4 is input to the program built-in CPU 32, and the input ring buffer 3 is input by the input processing means 36.
8 is stored.

The data stored in the input ring buffer 38 is read out by the transmission processing means 35,
The start / stop bits are added before and after, and are output to the clock built-in modem board 31 as transmission data of the clock synchronous system in synchronization with the clock from the clock built-in modem board 31.

In the modem board 31 with a built-in clock, the demodulated data of the clock synchronous system from the following modem and the transmit data of the clock synchronous system from the CPU 32 with the program are both modulated, and the clock is transmitted to the modem ahead. The transmission is performed in a synchronous manner.

On the other hand, clock synchronous transmission data from the front modem is received and demodulated by the modem board 31 with a built-in clock, output as it is to the base station 4 as asynchronous data, and is again modulated. It is sent to the subsequent modem.

While the modem according to the embodiment of the present invention has been described using a multimodem as an example, the same function can be realized with a single modem.

In the single modem according to the embodiment of the present invention, the asynchronous / synchronous conversion means determines the start bit and the stop bit for the data from the asynchronous terminal, temporarily stores the input data, and temporarily stores the stored data. In addition, a start bit and a stop bit are added to the data to output transmission data synchronized with the clock supplied from the modulation means, so that asynchronous data is transmitted in a synchronous manner, and an asynchronous terminal is connected to a synchronous communication environment. Thus, reliable data transfer can be performed.

In the schematic configuration of the single modem of the present invention, in the configuration diagram of FIG. 2, the modem board 31 'with a built-in clock is slightly different from the modem board 31 with a built-in clock of a multi-modem, and the communication partner of the clock synchronous system is a forward modem or a subsequent modem. The difference is that only a modem is used.

Next, a specific configuration example of the single modem according to the embodiment of the present invention will be described with reference to FIG. FIG. 8 is a circuit diagram showing a specific configuration example of the single modem of the present invention. 8, the SIO I / F portion corresponds to the CPU 32 with a built-in program as in the case of the multi-modem of FIG. 7, and the card modem A1 corresponds to the modem board 31 'with a built-in clock. Here, the card modem A1 is a general card modem that realizes a clock synchronous modem function.

The operation of the single modem of the present invention is as follows.
For the asynchronous (start-stop synchronization) data input from the RS422 interface J2 or the RS232C interface J1, the start / stop bits are determined in the SIO I / F and temporarily stored, and the start / stop bits for the asynchronous system are added. In this manner, clock synchronization is performed in accordance with the clock supplied from the card modem A1 and output as transmission data.
The signal is input to one SD terminal, modulated, output from the SOUT terminal, and transmitted to a preceding or succeeding modem.

In FIG. 8, ST2 of the card modem A1 is used.
(Signal Timing2) Use terminal output as clock for SIO
Supply to I / F. The clock output from the ST2 terminal is a clock timing independently generated by the card modem A1.

The data received from the preceding or succeeding modem is demodulated in the card modem A1, output from the RD terminal, and output as it is as asynchronous data.
The signal is output to the S422 interface J2 or the RS232C interface J1.

As a result, in the train radio system shown in FIG. 1, the asynchronous data output from the central controller 1 and each base station 4 to each modem is transmitted to the single modem 2 or the multi-modem 3 for the asynchronous start / stop. The data is converted to clock synchronous data in the form of adding a stop bit, transmitted between the modems in a clock synchronous method, and output to the central controller 1 and each base station 4 as it is. Will be output as

According to the modem of the embodiment of the present invention, asynchronous data from the central control unit 1 or the base station 4 is received in the asynchronous system, temporarily stored in the input ring buffer 38, and used for transmission between modems. Since the data is transmitted in the clock synchronous system in synchronization with the clock, the data of the asynchronous system can be reliably transmitted without being missed, and the reliability of communication can be improved.

Further, by performing synchronous / asynchronous conversion using the modem according to the embodiment of the present invention, communication between modems is unified into synchronous communication, and an environment in which synchronous communication terminals and asynchronous communication terminals coexist is constructed. There is an effect that can be done.

In the central control unit 1 and the base station 4, the data received from the modem is at a speed according to the communication clock between the modems and must be adjusted in advance. The transfer rate of the asynchronous data output to the CPU need not be adjusted to the reception speed, but may be adjusted to the speed of the input processing means 36 in the CPU 32 with a built-in program of the modem. Therefore, there is an effect that versatility can be expanded.

Further, if the modem of the present invention is used, there is no need to arrange a special device such as a synchronous / asynchronous converter, and there is an effect that a simple and economical system can be constructed.

[0059]

According to the present invention, the asynchronous / synchronous conversion means determines the start bit and the stop bit for the data from the asynchronous terminal, temporarily stores the input data, and stores the start bit in the stored data. And a multi-modem or a single modem that outputs transmission data synchronized with the clock supplied from the demodulating means or the modulating means by adding a stop bit and asynchronous data. Even if an asynchronous terminal is connected, the data transfer can be performed reliably.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a connection system of a train radio system using a modem according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a schematic configuration of a multi-modem according to an embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration inside a program built-in CPU of the modem of the present invention.

FIG. 4 is a format diagram showing a configuration of an input ring buffer of a CPU with a built-in program of the modem of the present invention.

FIG. 5 is a flowchart showing an operation of an input processing means of the CPU with a built-in program of the present invention.

FIG. 6 is a flowchart showing the operation of the transmission processing means of the CPU with a built-in program of the present invention.

FIG. 7 is a circuit diagram showing a specific configuration example of the multi-modem of the present invention.

FIG. 8 is a circuit diagram showing a specific configuration example of a single modem of the present invention.

FIG. 9 is an explanatory diagram showing a sampling method of a clock synchronous system.

FIG. 10 is an explanatory diagram showing a case in which start-stop synchronization data is sampled by a clock synchronization sampling method.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Central control device, 2 ... Single modem, 3 ... Multimodem, 4 ... Base station, 31 ... Modem board with a built-in clock, 32 ... CPU with a built-in, 35 ... Transmission processing means, 36 ... Input processing means, 37 ... Interruption means 38 input ring buffer

Claims (4)

[Claims] 1. A modem for transmitting data input from an asynchronous terminal in a clock synchronous manner, wherein a start bit and a stop bit are determined for data from the asynchronous terminal to temporarily store input data. And a modem for adding a start bit and a stop bit to the stored data when the stored data is modulated and output by a clock synchronous method. 2. A modulated signal transmitted from another modem,
What is claimed is: 1. A multi-modem for transmitting data input from an asynchronous terminal in a clock synchronous manner, receiving a modulated signal transmitted from said another modem, demodulating with a clock included in said modulated signal, and outputting demodulated data. Demodulating means for outputting the clock, and determining start bits and stop bits for data from the asynchronous terminal, temporarily storing input data, and modulating and outputting the stored data in a clock synchronous manner. At this time, an asynchronous / synchronous conversion unit that adds a start bit and a stop bit to the data to output transmission data synchronized with a clock from the demodulation unit, and a demodulated data from the demodulation unit or the asynchronous / synchronous conversion. Modulating means for modulating transmission data from the means and transmitting a modulated signal. Beam. 3. A single modem for transmitting data input from an asynchronous terminal in a clock synchronous manner, wherein a start bit and a stop bit are determined for data from the asynchronous terminal to temporarily store input data. ,
An asynchronous / synchronous converting means for adding a start bit and a stop bit to the data and outputting transmission data synchronized with a supplied clock when the accumulated data is modulated and output by a clock synchronous system; A modulating means for supplying a clock to the synchronous converting means, modulating the transmission data from the asynchronous / synchronous converting means, and sending out a modulated signal. 4. An asynchronous / synchronous conversion means for temporarily storing input data from an asynchronous terminal, a start bit and a stop bit for data from the asynchronous terminal, and Input processing means for reading the input data from the buffer, adding a start bit and a stop bit before and after the input data, and outputting the data in synchronization with a supplied clock; and 4. An asynchronous / synchronous conversion unit comprising: an interruption unit that monitors the presence or absence of data in the communication unit and generates an interruption signal that activates the transmission processing unit preferentially. modem.