JP2001085644A - Fabrication method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To disconnect or extend an interconnection on a semiconductor substrate easily by an arrangement wherein function test of a semiconductor device is performed by making holes above a plurality of electrode pads and applying a voltage or a signal to the plurality of electrode pads and then irradiating specified parts of a plurality of program interconnections, determined based on the test results, with an electron beam. SOLUTION: Prior to probe test, openings are made only at bonding pad parts and first time passivation is carried out to form a protective film. Probe test is then carried out under that state using an LSI tester and interconnection correction data obtained based on the test results is transmitted, on-line, from a tester to an interconnection correction apparatus. Subsequently, a wafer is coated with novolac based resin which is sensitized directly with an electron beam generated from an EB direct writing system and developed. At that moment of time, cutting points of each DRAM is exposed and a protective film and an uppermost Al interconnection layer are cut by etching.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a technique particularly effective when applied to a wiring repair technique of a dynamic RAM (random access memory) having a defect relieving function.

[0002]

2. Description of the Related Art The basic configuration is a memory array composed of a plurality of orthogonally arranged word lines and bit lines and a plurality of dynamic memory cells arranged in a grid at the intersections of these word lines and bit lines. There is a dynamic RAM. As one means for increasing the product yield of these dynamic RAMs, a so-called defect is provided in which a redundant word line and a redundant bit line are provided in a memory array and selectively replaced with a defective word line or a defective bit line in which an abnormality is detected. There is a rescue method, and there is a dynamic RAM having such a defect rescue function.

A dynamic RA having a defect relief function
For M, see, for example, Nikkei McGraw-Hill, 19
No. 209 of “Nikkei Electronics” dated June 3, 1985
Pp. 231 to 231.

[0004]

In a conventional dynamic RAM or the like having a defect relieving function as described above, a defective word line and a defective bit line replaced with a redundant word line or a redundant bit line are replaced with a memory. Left undisconnected from the array. Therefore, for example, when a current leak path is formed through a common source line or a bit line precharge circuit and these defective word lines or defective bit lines, the chip is functionally normal. This is a DC (direct current) defective product having a so-called standby current defect and a plate level defect. As a result, despite the provision of the defect rescue function, the remedy rate of a dynamic RAM or the like is not improved as expected, and there has been a problem that the cost reduction is limited.

On the other hand, a conventional dynamic RAM having a defect relieving function is provided in correspondence with a redundant word line or a redundant bit line, and a plurality of fuse means are cut in a predetermined combination so as to correspond to the redundant word line or the redundant word line. A plurality of defective address ROMs storing the defective addresses assigned to the redundant bit lines, and comparing these defective addresses with the addresses supplied at the time of memory access bit by bit, and when both addresses match, the corresponding redundant word line or A plurality of address comparison circuits for selectively setting a redundant bit line to a selected state. Dynamic RAM
As the capacity increases and the number of bits of the address signal increases, the number of required fuse means increases, and the required layout area as a defective address ROM or an address comparison circuit also increases. Further, the number of logic stages of the address comparison circuit and the like becomes deep, and a relatively long time is required from when the dynamic RAM is started until the redundant word line or the redundant bit line is selected. As a result, a chip area of a dynamic RAM or the like having a defect relieving function is increased, which hinders cost reduction and slows down the access time.

An object of the present invention is to provide a method of manufacturing a semiconductor device in which a desired wiring formed on a semiconductor substrate is easily cut or added. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0007]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. As a method of manufacturing a semiconductor device having a predetermined circuit, a plurality of electrode pads connected to the circuit, and a plurality of program wirings including an uppermost wiring layer connected to the circuit, Forming an insulating film, performing a test on the function of the semiconductor device by opening holes on the plurality of electrode pads and applying a voltage or a signal to the plurality of electrode pads, and forming a resist film on the surface of the semiconductor device. An opening is formed in the resist film by irradiating a predetermined portion of the plurality of program wirings determined based on the test with an electron beam, and using the opening to form the plurality of programs. A predetermined portion of the wiring is cut.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION FIG. 1 is a block diagram of a dynamic RAM to which the present invention is applied.
A block diagram of one embodiment is shown. FIG. 2 is a block diagram of one embodiment of the memory module MOD0 included in the dynamic RAM of FIG. An outline of the configuration and operation of the dynamic RAM according to this embodiment will be described with reference to these drawings. In addition,
The circuit elements constituting each block in FIGS. 1 and 2 are formed on one semiconductor substrate such as single crystal silicon, although not particularly limited.

In FIG. 1, the dynamic RAM of this embodiment is not particularly limited, but includes four memory modules MOD0 to MOD0 which occupy most of the semiconductor substrate surface.
MOD3 is a basic configuration. Although these memory modules are not particularly limited, as shown by the memory module MOD0, the main amplifier groups MAG0 to MAG
AG3, and a total of eight memory mats MAT0 to MAT7 arranged four by four with these main amplifier groups interposed therebetween. Although not particularly limited, the four memory mats MAT0 to MAT3 arranged on the right side of the main amplifier groups MAG0 to MAG3 are
To MG03, and the four memory mats MAT4 to MAT7 arranged on the left are grouped as memory mat groups MG01 to MG31, respectively.

Here, the memory modules MOD0-MOD
Each of the memory mats MAT0 to MAT7 constituting D3 is not particularly limited, but may be any of the memory mats MAT0 to MAT7 in FIG.
As represented by T0 and MAT4, a pair of memory arrays AR arranged across the sense amplifier SA are provided.
YL and ARYR, and a pair of X address decoders XDL and XDR provided corresponding to these memory arrays.
And a sense amplifier driving circuit CSD provided corresponding to the sense amplifier SA. X address decoder X
Although not particularly limited, the DL and XDR are supplied with an internal control signal XDG from the timing generation circuit TG and a predetermined predecode signal XP from an X predecoder XPD described later. Also, the sense amplifier SA
And the sense amplifier drive circuit CSD, although not particularly limited, the internal control signal SHL from the timing generation circuit TG.
, SHR, and PC, and corresponding memory mat select signals MS0 to MS7 from the memory mat select circuit MSL. The sense amplifiers SA of the memory mats MAT0 to MAT7 are connected to the main amplifier groups MAG0 to MAG via four sets of common I / O lines.
3 are coupled to four main amplifiers MA0 to MA3, respectively.

The main amplifier groups MAG0 to MAG3 are not particularly limited, but as shown by the main amplifier group MAG0 in FIG.
A3. Although not particularly limited, the internal control signals MAW and MAR are commonly supplied from the timing generation circuit TG to these main amplifiers, and the corresponding common I / O selection circuit IOSL supplies the corresponding common I / O.
Select signals AS0 to AS3 are supplied, respectively. The main amplifiers MA0 to MA3 further have corresponding data input signal lines DI0 to DI3 and data output signal lines DO0 to DO3.
Coupled to data input / output circuit DIO via DO3.

In this embodiment, the memory mat MAT
0 to MAT7 memory arrays ARYL and AR
Each of the YRs is not particularly limited, but has a so-called storage capacity of 256 kilobits, as described later. Therefore, each of memory mats MAT0 to MAT7 has a storage capacity of so-called 512 kilobits, and each of memory modules MOD0 to MOD3 has a storage capacity of so-called 4 megabits. As a result, the dynamic RAM of this embodiment has a so-called 16 megabit storage capacity.

On the other hand, the dynamic RAM of this embodiment
Although not particularly limited, four memory mats, one each specified by memory mat select signals MS0 to MS7, out of eight memory mats MAT0 to MAT7 constituting each memory module, are simultaneously selected. Is done. At this time, in the selected memory mat, as described later, four memory cells are simultaneously selected, and the corresponding main amplifier is connected via the corresponding complementary bit line and four sets of common I / O lines. They are respectively coupled to main amplifiers MA0 to MA3 forming a group. These main amplifiers are selectively activated according to the common I / O line selection signals AS0 to AS3, for example, the data input / output circuit DIO via the corresponding data input signal line DI0 or data output signal line DO0. Is connected.

Further, the dynamic RA of this embodiment
Although not particularly limited, M is selectively formed into a so-called × 1 bit or × 4 bit configuration by cutting a predetermined wiring in a predetermined combination as described later. When the dynamic RAM has a × 1 bit configuration, in the data input / output circuit DIO, four sets of common I / O lines are selectively selected according to the memory module selection signals NA0 to NA3, and writing or writing in 1-bit units is performed. A read operation is performed. At this time, although not particularly limited, the write data is input to the dynamic RAM via the data input / output terminal DIO0, that is, the data input terminal Din, and the read data is transmitted via the data input / output terminal DIO3, that is, the data output terminal Dout. You.

2. Memory array and sense amplifier and DC
Defect relief method and partial product configuration method 2.1. 3. Memory Array FIG. 3 is a circuit diagram of an embodiment of the memory array ARYL included in the memory mat MAT0 of the memory module MOD0 of the dynamic RAM shown in FIGS. 1 and 2. 4 and 5 show the memory array A of FIG.
A partial sectional structural view and a planar structural view of one embodiment of RYL are shown, respectively. Hereinafter, this memory array AR
A specific configuration and an outline of the operation of the memory array constituting the dynamic RAM according to this embodiment will be described by taking YL as an example. In the following circuit diagrams, MOSFETs (metal oxide semiconductor type field effect transistors, in which an arrow is attached to a channel (back gate) portion thereof.
FET is a general term for an insulated gate field effect transistor), which is a P-channel type and is distinguished from an N-channel MOSFET without an arrow.

In FIG. 3, a memory array ARYL is
Although not particularly limited, 256 word lines W0 to W255 and four redundant word lines WR0 to WR3 arranged in parallel in the vertical direction in FIG. bit line B 0~ B 1023
(Here, for example, the non-inverted bit line B0 and the inverted bit line B
The combined 0B representing underlined as complementary bit lines B 0. Further, a so-called inverted signal or an inverted signal line which is selectively set to a low level when it is made valid, such as the inverted bit line B0B, is indicated by adding a B to the end of its name. Hereinafter, the same) as well as 8 pairs of the redundant complementary bit line B R0~ B R7. At the intersections of these word lines and redundant word lines and the complementary bit lines and redundant complementary bit lines, 260 × 1032 dynamic memory cells are arranged in a grid. As a result, the memory array ARYL has a storage capacity of substantially 262144 bits, that is, a so-called 256 kilobits.

Each of the dynamic memory cells constituting the memory array ARYL includes an address selection MOSFET Qa and an information storage capacitor Cs, as shown in FIG. Address selection MOS of a total of 260 memory cells arranged in the same column of memory array ARYL
Drain of FETQa the corresponding complementary bit line B 0 to
The non-inverted or inverted signal line of the B 1023 or redundant complementary bit line B R0 to B R7 with a predetermined regularity are alternately bonded. The gates of the address selection MOSFETs Qa of a total of 1032 memory cells arranged in the same row are commonly coupled to corresponding word lines W0 to W255 or redundant word lines WR0 to WR3, respectively. The other electrode of the information storage capacitor Cs of all memory cells has
A predetermined plate voltage VPL is commonly supplied.

In this embodiment, the memory array ARY
Although the memory cells forming L are not particularly limited, FIG.
As shown in FIG. 2, a memory cell of a so-called stacked structure (stacked capacitor) type is used. The information storage capacitor Cs has a polysilicon plate electrode PL and a data storage layer formed with a predetermined insulating film IS interposed therebetween. It consists of an electrode SP. The address selection MOSFET Qa includes an N-type diffusion layer formed in a P-type well region PWELL of a P-type semiconductor substrate PSUB, that is, a drain D and a source S;
Word lines W0-W255 or redundant word lines WR0-WR
3 as a polysilicon gate layer. The drain D of the address selection MOSFET Qa is coupled to a non-inverting bit line B0 or the like made of tungsten polycide, and its gate, that is, a word line or a redundant word line is further connected to a shunt main word line MW0 to MW2.
55 or MWR0 to MWR3. A bit line selection signal line YS0 or the like made of tungsten polycide is formed between the non-inverted bit line B0 and the like and the main word line. These bit line selection signal lines (YSL)
Are arranged so as to penetrate eight memory mats arranged adjacent to each other in the direction in which the bit lines extend, as described later. Therefore, as shown in FIG. It is formed with a width.

Word lines W0-W255 and redundant word lines WR0-WR3 forming memory array ARYL
Although not particularly limited, as shown in FIG. 3, one of them is coupled to a corresponding X address decoder XDL or XDR, and is alternatively set to a high level selected state. The other side is coupled to the ground potential of the circuit via the corresponding word line clear MOSFETs Q25 and Q26, etc., and is kept at a low level like the ground potential of the circuit while the dynamic RAM is in the non-selected state. Such a clear operation of the word line and the redundant word line is selectively released by setting the dynamic RAM to the selected state and selectively setting the internal control signal WC0 or WC1 to the low level. Complementary bit lines B 0 to B 1023 and redundant complementary bit line B R0 to B R7 constituting the memory array ARYL is coupled to a corresponding unit circuit of the sense amplifier SA.

2.2. Sense Amplifier FIG. 6 is a circuit diagram showing one embodiment of the sense amplifier SA included in the memory mat MAT0 of the memory module MOD0 of the dynamic RAM shown in FIGS. 1 and 2. Taking this sense amplifier SA as an example, a dynamic RA
An outline of a specific configuration and operation of the sense amplifier constituting M will be described.

[0021] In FIG. 6, the sense amplifier SA is not particularly limited, a total of 1032 pieces provided corresponding to the complementary bit lines of the memory array ARYL and ARYR B 0~ B 1023 and redundant complementary bit line B R0 to B R7 Is provided. These unit circuits include a P-channel MOSFET Q1 and an N-channel MOSFET Q1.
A basic configuration is a unit amplifier circuit formed by cross-connecting a pair of CMOS inverter circuits each including one, a P-channel MOSFET Q2, and an N-channel MOSFET Q12. Each unit circuit of the sense amplifier SA is not particularly limited, but further includes an N-channel MOSFET Q13.
To a bit line precharge circuit consisting of
A switch MOSFET for bit line selection represented by channel MOSFETs Q20 and Q21 is provided.

When the internal control signal SHL is at a high level, the non-inverting and inverting input / output nodes of the unit amplifier circuit constituting each unit circuit of the sense amplifier SA are connected to the memory array ARYL via the left shared MOSFETs Q16 and Q17. Connected to the corresponding complementary bit line or redundant complementary bit line, and when the internal control signal SHR is set to the high level, the right side shared MOSFET Q18
And Q19 to the corresponding complementary bit line or redundant complementary bit line of the memory array ARYR. P-channel MOSFE constituting each unit amplifier circuit
The sources of TQ1 and Q2 are commonly coupled to a common source line CSP, and N-channel MOSFETs Q11 and Q1
The two sources are commonly coupled to a common source line CSN. A power supply voltage or a ground potential of the circuit is selectively supplied to these common source lines via corresponding drive MOSFETs of the sense amplifier drive circuit CSD. The unit amplifier circuits constituting each unit circuit of the sense amplifier SA are selectively activated by supplying the power supply voltage or the ground potential of the circuit to the common source lines CSP and CSN.
In this operation state, each unit amplifier circuit reads the minute read output from the 1032 memory cells coupled to the selected word line of the memory array ARYL or ARYR via the corresponding complementary bit line or redundant complementary bit line. The signal is amplified to be a high-level or low-level binary read signal.

The internal control signal PC is supplied from the timing generation circuit TG to the gates of the MOSFETs Q13 to Q15 constituting the bit line precharge circuit of the sense amplifier SA. Further, a common pre-charge voltage HVC is connected to the sources of the MOSFETs Q13 and Q14 which are connected in common.
Is supplied. The precharge voltage HVC is not particularly limited, but is set at a substantially intermediate potential between the power supply voltage of the circuit and the ground potential. The internal control signal PC is selectively set to a high level at a predetermined timing when the dynamic RAM is set to the non-selected state. At this time, the shared internal control signals SHL and SHR are both at a high level. Thereby, the MOSFETs Q13 to Q15
When the internal control signal PC is set to the high level, the internal control signal PC is selectively and simultaneously turned on, and the non-inverting and inverting input / output nodes of the corresponding unit amplifier circuit and the non-inverting and inverting of the complementary bit line or the redundant complementary bit line. The signal line is precharged to the precharge voltage HVC. Although not particularly limited, a similar common source line precharge circuit including N-channel MOSFETs Q22 to Q24 is provided between the common source lines CSP and CSN.

The other switch MOSFETQ20 and Q21 constituting each unit circuit of the sense amplifier SA is coupled to four pairs every four pairs of non-inverted or inverted signal line of the common I / O lines I O0~ I O3. In addition, these switches M
The gates of the OSFETs are sequentially coupled in common four pairs at a time.
A corresponding bit line selection signal YS0 to YS255 or a redundant bit line selection signal Y from the address decoder YD0 or the like.
R0 to YR1 are supplied respectively. Thereby, four sets of adjacent switch MOSFETs Q20 and Q21 are
When the corresponding bit line selection signal or redundant bit line selection signal is alternatively set to the high level, it is selectively and simultaneously turned on, and the non-inversion of the corresponding four unit amplifier circuits of the sense amplifier SA is performed. and selectively connects the inverting input node and the common I / O lines I O0~ I O3.

2.3. DC Defect Relief Method FIG. 7 is a partial circuit diagram for explaining the DC defect rescue method in the memory array ARYL included in the memory mat MAT0 of the memory module MOD0 of the dynamic RAM of this embodiment and its peripheral portion. Shown in FIG.
7 shows an evaluation graph of the DC defect remedy method of FIG. FIGS. 9 to 13 show sense amplifiers SA associated with the cutting points CP3 to CP6 shown in FIG.
Are respectively shown in partial sectional structural view and plan structural view. With reference to these figures, a specific method for relieving DC defects of the dynamic RAM of this embodiment and its features will be described. The DC defect relief shown below is
The same is applied to the memory array ARYR forming a pair and other memory arrays ARYL and ARYR constituting another memory mat or memory module.

In FIG. 7, D of the dynamic RAM is
The C failure is not particularly limited, but generally is caused by undesired short-circuit failures at the following four locations. (1) A short circuit between the word line WLm or the like and the word line selection level supply line, that is, the high voltage VCH due to the short circuit resistor RS1. At this time, when the dynamic RAM is set to the non-selection state, the high voltage VCH is switched to the short-circuit resistance RS1, the word line W
A leakage current path is formed from Lm and the word line clear MOSFET Q26 or the high voltage VCH through the short-circuit resistor RS1 and the word line reset MOSFET Q27, and the standby current of the dynamic RAM increases, resulting in DC failure. This means that the inverted bit line BLB
Occurs similarly. (2) Short circuit between the word line WLm or the like and the non-inverted bit line BL or the like due to the short circuit resistance RS2. At this time, when the dynamic RAM is set to the non-selected state, the precharge level supply line HVC switches the precharge MOSFET Q13, shared MOSFET Q16, non-inverted bit line BL, short-circuit resistance RS2, word line WLm, and word line clear MOS.
FET Q26 or precharge level supply line HV
C to precharge MOSFET Q23, common source line CSP, MOSFET Q2, precharge MOSFET
A leak current path is formed through TQ14 and Q13, shared MOSFET Q16, non-inverted bit line BL, short-circuit resistance RS2, word line WLm and word line clear MOSFET Q26, and the standby current of the dynamic RAM increases, resulting in DC failure. This also occurs for the inverted bit line BLB. (3) Short circuit between the non-inverted bit line BL or the like and the bit line selection signal line YSn or the like by the short circuit resistor RS3. At this time, when the dynamic RAM is set to the non-selected state, the precharge MOSFET is connected to the precharge level supply line HVC.
Q13, short-circuit resistance RS3 and bit line selection signal line YS
n, or from the precharge level supply line HVC to the precharge MOSFET Q23, the common source line CSP,
A leakage current path is formed through the MOSFET Q2, the precharge MOSFETs Q14 and Q13, the short-circuit resistance RS3, and the bit line selection signal line YSn, and the standby current of the dynamic RAM increases, resulting in DC failure. This also occurs for the inverted bit line BLB. (4) Short circuit between the inversion bit line BLB or the like and the shared signal line SHL due to the short circuit resistor RS4. At this time, when the dynamic RAM is set to the non-selected state, the precharge MOSFET Q1 is connected to the precharge level supply line HVC.
4, from the short-circuit resistor RS4 and the shared signal line SHL, or from the precharge level supply line HVC to the precharge M
OSFET Q23, common source line CSP, MOSFE
TQ1, precharge MOSFETs Q13 and Q14,
A leak current path is formed via the short-circuit resistor RS4 and the shared signal line SHL, and the standby current of the dynamic RAM increases, resulting in DC failure. This also occurs for shared signal line SHR. (5) A short circuit between the inversion bit line BLB or the like and the precharge control signal line PC due to the short circuit resistor RS5. At this time, when the dynamic RAM is set to the non-selected state, the precharge MOSFET is connected to the precharge level supply line HVC.
Q14, short-circuit resistance RS5 and precharge control signal line P
A leakage current path via C is formed, the standby current of the dynamic RAM increases, and DC failure occurs.
The word line clear MOSFET corresponding to the word line
It is also conceivable to cut off a part of the current path by cutting between Q26 and Q26. In this case, however, the cut word line becomes a floating state, and the information from the non-inverted or inverted signal line of the corresponding complementary bit line is output. Since the capacitance of the storage capacitor is visible, there is a problem that the capacitance balance of the complementary bit line is lost.

However, the dynamic type R of this embodiment
In the AM, by selectively combining and cutting the next plurality of cutting points according to the content of the fault, the corresponding current path is cut off, the standby current of the dynamic RAM is reduced, and the DC failure is reduced. The so-called DC defect remedy is solved. That is, (1) disconnection point CP1, that is, X address decoder XD
Between the output node of the word line drive circuit WDm or the like corresponding to the word line WLm or the like in which a defect such as L has occurred and the word line selection level supply line, that is, the high voltage VCH. (2) The cutting point CP2, that is, the word line W in which the defect has occurred
Lm or the like and the high voltage VCH. (3) The cut points CP3 and CP4, that is, the non-inverted and inverted signal lines of the defective bit line and the sense amplifier S
Between the corresponding unit circuit of A. (4) The cut point CP5, that is, between the sources of the P-channel MOSFETs Q1 and Q2 of the unit amplifier circuit corresponding to the bit line in which the defect of the sense amplifier SA has occurred and the common source line CSP. (5) The cutting point CP6, that is, the bit line precharge circuit corresponding to the bit line in which the defect of the sense amplifier SA has occurred, that is, between the precharge MOSFETs Q13 and Q14 and the precharge level supply line HVC.

As is well known, the product yield of a dynamic RAM or the like after defect repair is reduced due to the occurrence of DC failure due to the undesired short-circuit failure. That is, when the so-called non-defective product rate after defect repair by the conventional redundancy method is Yo, the DC defect density in the memory array is Di, and the memory array area is Sm, the product yield Y of the dynamic RAM or the like after defect relief is , Y = Yo · exp (−Di · Sm). Therefore, when a dynamic RAM of 64 megabits is predicted, as shown in FIG. 8, even if the DC defect density Di is 5 (pieces / cm ² ), for example, the product yield by the conventional defect remedy is the function non-defective rate, Decreases to about 15%, despite the fact that the recoverable yield is about 55%. In the dynamic RAM according to this embodiment, most of the DC failures can be eliminated by cutting a plurality of cut portions in a predetermined combination and cutting the leak current path, so that so-called DC defect relief is realized. As a result, the product yield of the dynamic RAM is improved toward the non-defective product rate, that is, the rescue yield, as indicated by the arrow in FIG.

Incidentally, the dynamic type R of this embodiment
The cutting at the cutting points CP1 to CP6 in the AM is not particularly limited, but is realized by directly or indirectly cutting the uppermost metal wiring layer, that is, the aluminum wiring layer using a wiring correction device described later. For this reason, for example, in the case of the cutting locations CP3 and CP4, although not particularly limited, as shown in FIGS. 9 and 10, the non-inverting bit line B formed of tungsten polycide or the like is used.
L and the like are cut in advance at each cutting point, and are further connected via the uppermost aluminum wiring layer AL1. Thus, only by cutting the uppermost aluminum wiring layer AL1, it is possible to substantially cut the non-inverted bit lines BL and the like. On the other hand, in the case of the cutting portion CP5, although not particularly limited, as illustrated in FIG. 11, the common source line CSP formed with a large wiring width by the uppermost aluminum wiring layer AL1 is aligned with the elliptical cutting region CE. Substantial cutting is realized by boring. Therefore, the sources S1 and S2 of the P-channel MOSFETs Q1 and Q2 constituting each unit amplifier circuit of the sense amplifier SA are
As shown in FIG. 12, the uppermost aluminum wiring layer AL1, that is, the cutting region CE is provided via the metal pad MP.
Is joined inside. Further, in the case of the cutting point CP6,
Although not particularly limited, as shown in FIG. 13, an uppermost aluminum wiring layer is provided between the diffusion layer where the sources S13 and S14 of the bit line precharge MOSFETs Q13 and Q14 are formed and the precharge level supply line HVC. A lead line formed of AL1 and easily cutable is provided.

FIGS. 14 and 15 show two other embodiments for realizing the disconnection of the wiring for repairing the DC defect. 14, MOSFETs Q13 and Q14 forming a bit line precharge circuit of sense amplifier SA
, The gate of which receives the output signal of the inverter circuit N2, that is, the unit control circuit VC1, although not particularly limited.
A channel MOSFET Q28 (switch means) is provided. Although the unit control circuit VC1 is not particularly limited,
It includes N-channel MOSFETs Q29 and Q30 provided in series between the power supply voltage and the ground potential of the circuit, and another N-channel MOSFET Q31 provided in parallel with these MOSFETs Q29 and Q30. The gate of the MOSFET Q29 has an internal control signal R
1 is supplied and the gate of MOSFET Q30 is coupled to the supply voltage of the circuit. Circuit power supply voltage and MOSFET
The wiring provided between the drains Q29 and Q31 that are commonly coupled is formed as a cutting point CP7 via the uppermost aluminum wiring layer AL1. MOSFE
The commonly coupled drains of TQ29 and Q31 are further coupled to the input terminal of inverter circuit N1. The output signal of the inverter circuit N1 is supplied to the inverter circuit N2 and to the gate of the MOSFET Q31.

When the wiring corresponding to the disconnection point CP7 is not in the disconnected state, the output signal of the inverter circuit N2 is at the high level. At this time, in the sense amplifier SA, the MOS
FET Q28 is turned on, and MOSFETs Q13-
The bit line precharge circuit consisting of Q15 functions normally. On the other hand, when the wiring corresponding to the cutting location CP7 is cut by a predetermined wiring correction device, the inverter circuit N2
Becomes low level, and the MOSFET Q28 is turned off. Therefore, the precharge MOSFE
The sources of TQ13 and Q14 and the precharge level supply line HVC are substantially disconnected, and the leak current path formed through these is indirectly disconnected.
That is, the disconnection of the wiring by this method is an effective means when it is not possible to directly disconnect the wiring because the layout of the portion including the portion to be disconnected is very complicated.

In the embodiment shown in FIG. 15, the MO shown in FIG.
Switch means corresponding to SFET Q28, ie, MOS
The FET Q32 and the unit control circuit UC2 can be shared by a plurality of bit line precharge circuits, and an increase in the number of circuit elements can be suppressed.

2.3. Configuration of Partial Product The dynamic RAM of this embodiment is, as described above,
It has four memory modules MOD0-MOD3, and each memory module has a main amplifier group MAG0-MAG.
And four memory mat groups MG00 and MG01 to MG30 and MG31 arranged symmetrically with the three memory mats 3 interposed therebetween. In this embodiment, these memory modules and memory mat groups are configured to be selectively invalidated by cutting predetermined wiring. As a result, a normal memory module or memory mat group having no defect is selectively made effective, in other words, an abnormal memory module or memory mat group having a defect is selectively separated, and a partial product of a dynamic RAM is manufactured. Can be configured.

That is, for example, when two memory modules MOD2 and MOD3 in which a defect is detected are invalidated, the remaining two normal memory modules MOD0 and MOD3 are disabled.
With OD1, a dynamic RAM partial product having a so-called 8-megabit storage capacity can be configured. In this case, for example, by fixing the Y address signal AY11 of the most significant bit to a low level, the selection operation of the memory modules MOD2 and MOD3 can be prohibited. On the other hand, for example, when the four memory mat groups MG01 to MG31 arranged on the right side of the main amplifier groups MAG0 to MAG3 are invalidated, the remaining four normal memory mat groups MG00 to MG30 are used.
A dynamic RAM partial product having a so-called 8-megabit storage capacity can be constructed. In this case, for example, the X address signal AX11 of the most significant bit
Is fixed to a low level, the selection operation of the memory mat groups MG01 to MG31 can be prohibited.

FIG. 16 is a circuit diagram showing one embodiment of the memory mat MAT0 constituting the memory module MOD0 of the dynamic RAM to which the present invention is applied. The memory module MOD0 includes the memory mat M
The eight memory mats MAT0 to MAT7 including AT0 are selectively invalidated by invalidating them, and the memory mat group MG00 is selected by invalidating four memory mats MAT0 to MAT3 including the memory mat MAT0. Invalidated. Hereinafter, the memory mat MAT
A specific method for selectively invalidating the memory module MOD0 or the memory mat group MG00 using 0 as an example will be described.

Referring to FIG. 16, memory mat MAT0
Is, as described above, a pair of memory arrays ARYL and ARYR arranged symmetrically with the sense amplifier SA interposed therebetween.
And a pair of X address decoders XDL and XDR provided corresponding to these memory arrays and a sense amplifier driving circuit CSD. In this embodiment, as shown in FIG. 16, the word lines and redundant word lines (WL) constituting the memory arrays ARYL and ARYR are cut off points CP59 and CP60 or CP69 made of the uppermost aluminum wiring layer AL1. And CP7
0, etc., to the corresponding X address decoder XDL or XDR. Further, shared signal lines SHL and SHR and common source lines CSP and CSN provided between the sense amplifier SA and the sense amplifier driving circuit CSD are provided.
Similarly, the precharge level supply line HVC and the precharge control signal line PC are similarly connected to the cutting points CP61 and CP65 formed of the uppermost aluminum wiring layer AL1.
To CP68, and the non-inverted signal line IO and the inverted signal line IOB of the common I / O line
Coupled to main amplifier group MAG0 via P62-CP64. The cutting points CP59 to CP70 are:
Although not particularly limited, they are arranged substantially in a straight line, and the efficiency of the cutting process by the wiring correction device is improved.

When a plurality of abnormalities are detected in the memory mat MAT0 and cannot be remedied by redundancy switching or the like, the entire memory mat MAT0 is determined to be defective. Then, a dynamic RAM partial product is constituted by another normal memory module or memory mat group, and wiring correction data for separating the abnormal memory module or memory mat group is transmitted online from the test apparatus to the wiring correction apparatus. You. As a result, in a plurality of memory mats including the memory mat MAT0, the cutting points CP59 to CP70 are cut, and these memory mats are invalidated. As a result, in the memory mat which is invalidated, most of the current paths are cut off, thereby achieving low power consumption as a dynamic RAM partial product.

3. X-system and Y-system selection circuit and redundant switching system The dynamic RAM of this embodiment is, as described above,
It has a so-called 16 megabit storage capacity. When the dynamic RAM has a so-called × 1 bit configuration,
The address is a 12-bit X address signal A supplied in a time-division manner via address input terminals A0 to A11.
X0 to AX11 and Y address signals AY0 to AY1
1 is alternatively specified. Of these, the X address signals AX9 to AX11 of the upper 3 bits are supplied to eight memory mats MAT0 to MAT provided in each memory module.
It is provided to designate T7 alternatively. Further, the next bit X address signal AX8 is used for alternately specifying the memory array ARYL or ARYR in each memory mat, and the remaining eight bits of the X address signal AX0 to AX8 are provided.
Numeral 7 is provided for alternatively designating 256 word lines in each memory array. Further, the upper two bits Y
The address signals AY10 and AY11 are used for selecting the main amplifier groups MAG0 to MAG3, that is, the memory modules MOD0 to MOD3 by the data input / output circuit DIO, and the lower two bits of Y address signals AY0 and AY1 are provided.
Is common I / O lines I O in each memory module
It is subjected to selection of 0 to I O3. The remaining 8 bits of the Y address signals AY2 to AY9 are used to selectively designate substantially 1024 complementary bit lines constituting each memory array, four by four.

On the other hand, the dynamic RAM of this embodiment
As described above, the memory mats MAT0 to MAT7
In response to provided a pair of memory arrays ARYL and ARYR, These memory arrays, four redundant word lines WR0~WR3 and eight sets of redundant complementary bit line B R0 to
And B R7 is provided. In this embodiment, switching of these redundant word lines and redundant complementary bit lines to defective word lines or defective complementary bit lines is performed by a so-called decode that directly switches the logical condition of the X address decoder or the Y address decoder as described later. It is realized by the method. The switching is not particularly limited, but is performed independently for each memory mat, and is performed in units of four word lines or four sets of complementary bit lines grouped together. Hereinafter, the configuration of the X-system and Y-system selection circuits of the dynamic RAM of this embodiment and the redundancy switching method will be described with reference to the block diagrams of FIGS. 1 and 2 and the circuit diagrams of FIGS.

3.1. X-system selection circuit and redundant word line switching system The X-system selection circuit of the dynamic RAM is not particularly limited, but an X address decoder X provided corresponding to the memory arrays ARYL and ARYR of each memory module.
DL and XDR, and an X address buffer XAB, a refresh address counter RFC, an X predecoder XPD, and a memory mat selection circuit MSL which are provided commonly to these X address decoders. Of these, one input terminal of the X address buffer XAB is
Although not particularly limited, it is coupled to address input terminals A0 to A11, and the other input terminal is supplied with refresh address signals AR0 to AR9 of 10 bits from a refresh address counter RFC. The X address buffer XAB is further supplied with an internal control signal XL from the timing generation circuit TG.

When the dynamic RAM is set to the normal operation mode, the X address buffer XAB is supplied to the X address buffer XAB in a time division manner through the address input terminals A0 to A11.
The address signals AX0 to AX11 are fetched according to the internal control signal XL and held. Also, when the dynamic RAM is set to the refresh mode, the refresh address signals AR0 to AR9 supplied from the refresh address counter RFC are fetched and held. Then, based on these address signals, internal address signals X0 to X11 are formed. Among these, the internal address signals X9 to X11 of the upper three bits are supplied to the memory mat selection circuit MSL, the internal address signal X8 of the next bit is supplied to the timing generation circuit TG, and the internal address signals X0 to X7 of the remaining eight bits are X Predecoder XP
D.

A memory mat selection circuit MSL selects memory mats MAT0 to MAT7 in each memory module based on 3-bit internal address signals X9 to X11 supplied from X address buffer XAB. The signals MS0 to MS7 are alternatively formed.
Further, the X predecoder XPD is provided with an X address buffer X.
The internal address signals X0 to X7 supplied from AB are combined and decoded by 2 bits or 3 bits, and the predecode signals XPD, that is, X0B to X3B and AX20 to
AX27 and AX50 to AX57 are formed alternatively. The internal address signal X8 supplied to the timing generation circuit TG is provided for selectively forming the internal control signal SHL or SHR for sharing.

Next, X address decoders XDL and XD
R is not particularly limited, but as shown in FIGS. 17 and 18, the word lines W0 to W2 of the memory array ARYL are
55 and a total of 260 word line drive circuits WD0 to WD2 provided corresponding to redundant word lines WR0 to WR3.
55 and WDR0 to WDR3. Although not particularly limited, these word line driving circuits are grouped into groups of four corresponding to the word line groups, and a total of 65 unit X address decoders UXD corresponding to each word line driving circuit group.
0 to UXD63 and UXDR are provided.

The word line drive circuits WD0 to WD255 and WDR0 to WDR3 are supplied with an internal control signal WPH from the timing generation circuit TG in common, as shown in FIG. From the corresponding inverted predecode signals X0B to X3
B are supplied respectively. In addition, four word line drive circuits WD0 to WD3 to WD60 to WD63 and WDR0 to WDR3 constituting each word line drive circuit group have corresponding unit X address decoders UXD0 to UXD.
63 and UXDR commonly supply the output signal thereof, that is, the word line group selection signals WG0 to WG63 or WGR. Word line drive circuits WD0-WD2
55 and WDR0-WDR3, but not limited thereto, the corresponding inverted predecode signals X0B-X3B are at the low level and the corresponding word line group selection signal WG0
To WG63 or WGR are set to the high level, so that the corresponding word lines W0 to W
255 or the redundant word lines WR0 to WR3 are alternatively set to a high level such as the high voltage VCH.

Unit X address decoders UXD0-UXD
Although not particularly limited, 63 is provided in series-parallel form between the inverter circuit N3 and the ground potential of the circuit as shown by the unit X address decoder UXD0 in FIG. Many N
Channel MOSFETs Q33 to Q35 are included. Of these, the gates of the MOSFETs Q33 and Q34 are connected to the predecode signals AX20 to AX from the X predecoder XPD.
27 and AX50 to AX57 are supplied in a predetermined combination, and the output signal of the inverter circuit N5, that is, the internal control signal XDG0 is supplied to the gate of the MOSFET Q35. The internal control signal XDG0 is not particularly limited, but is selectively set to the high level when the internal control signal XDG is set to the high level and the corresponding memory mat select signal MS0 is set to the high level. At this time, the output signal of the inverter circuit N3, that is, the word line group selection signal WG0 and the like are selectively set to the high level by setting the predecode signals AX20 to AX27 and AX50 to AX57 to the high level in a corresponding predetermined combination. You. As a result, the word line group designated by the internal address signals X2 to X7 is selectively set to a selected state, and the inverted predecode signals X0B to X3B, that is, out of the four word lines included in the word line group, , One word line specified by the internal address signals X0 and X1 is alternatively selected. Although not particularly limited, the input terminal of the inverter circuit N3 and the MOSFET Q3
The wiring to the drain of No. 3 is formed as a cutting point CP9 via the uppermost aluminum wiring layer AL1, and is used for separating the defective word line group.

On the other hand, unit X address decoders UXDR corresponding to redundant word lines WR0-WR3 are not particularly limited, but a total of 18 N channels provided in series-parallel form between inverter circuit N4 and the ground potential of the circuit. MO
Includes SFETs Q36 to Q53. Among them, the MOSFET Q provided in parallel between the internal nodes n1 and n2
Although not particularly limited, corresponding predecode signals AX20 to AX27 are sequentially supplied to the gates of 36 to Q43. Although not particularly limited, the wiring between the internal node n1 and the drain of each MOSFET is formed via the uppermost aluminum wiring layer AL1, and the cutting point CP
10 to CP17. Similarly, MOSFETs Q44-Q provided in parallel between internal nodes n2 and n3.
The corresponding predecode signal AX50
To AX57 are sequentially supplied. The wiring between the internal node n2 and the drain of each MOSFET is formed via the uppermost aluminum wiring layer AL1, and the cutting point C
P10 to CP17. The gate of MOSFET Q52 is not particularly limited, but is coupled to the ground potential of the circuit and to the power supply voltage of the circuit via resistor R1. The wiring between the gate of the MOSFET Q52 and the ground potential of the circuit, and the wiring between the resistor R1 and the power supply voltage of the circuit are both formed via the uppermost aluminum wiring layer AL1, and are cut off points CP26 and CP27, respectively. You. The internal control signal XDG0 is supplied to the gate of the MOSFET Q53. In addition, MOSFET Q5
The gate potential of No. 2 is not particularly limited, but after being ORed with other similar signals, as the internal control signal SIG,
The signal is supplied to the signature circuit SIG.

In the initial state of the dynamic RAM in which the cutting points CP9 to CP27 are not cut, the MO
The gate potential of the SFET Q52, that is, the internal control signal SI
G is at a low level such as the ground potential of the circuit. Therefore, MOSFET Q52 is turned off, and unit X address decoder U provided corresponding to the redundant word line group is provided.
XDR has virtually no effect.

When a short-circuit failure of a word line or the like is detected by a function test of a dynamic RAM in a wafer state, the test apparatus allocates a redundant word line according to a predetermined algorithm. In addition, wiring correction data for switching a word line group including a defective word line to a redundant word line group is created, and transmitted to a wiring correction device online, as described later. Based on the wiring correction data, the wiring correction device, for example, a corresponding unit X address decoder UX
The cutting point CP9 of D0 is cut, and the cutting points CP10 to CP17 and CP18 to CP25 of the unit X address decoder UXDR are all cut except for the necessary one, for example, CP17 and CP25, and finally the cutting point CP26 is cut. . As a result, in the dynamic RAM, the MOSFET Q52 is turned on,
The output signal of the unit X address decoder UXDR, that is, the word line group selection signal WGR is the same as the selection condition of the replaced word line group, in other words, for example, both the predecode signals AX20 and AX50 are set to the high level. And is selectively set to a high level. Thereby, the word line group including the defective word line is replaced with the redundant word line group, and the redundant switching of the word lines is realized.

3.2. Switching system between Y-system selection circuit and redundant complementary bit line Although the dynamic RAM of this embodiment is not particularly limited, as shown in FIG.
G00 and MG10, MG01 and MG11, MG20
And a total of four Y address decoders YD0 to YD3 provided corresponding to MG30 and MG21 and MG31.
Is provided. These Y address decoders include a Y address buffer YAB, a Y predecoder YPD, a memory module selection circuit MOSL, and a common I / O selection circuit IOS.
Together with L, it constitutes a Y-system selection circuit of the dynamic RAM.

The Y address buffer YAB takes in the Y address signals AY0 to AY11 supplied in a time-division manner via the address input terminals A0 to A11 in accordance with the internal control signal YL. The signals Y0 to Y11 are formed. Of these, the internal address signals Y10 and Y11 of the upper 2 bits are applied to the memory module selection circuit MOSL, and the internal address signals Y0 and Y1 of the lower 2 bits are applied to the common I / O selection circuit IOS.
L, and the remaining 8 bits of the internal address signals Y2 to Y9 are supplied to a Y predecoder YPD.

The memory module selection circuit MOSL has Y
Based on 2-bit internal address signals Y10 and Y11 supplied from the address buffer YAB, memory module select signals NA0 to NA3 for selectively activating the memory modules MOD0 to MOD3 are formed alternatively. , And the data input / output circuit DIO. Further, the common I / O selection circuit IOSL is configured to output common I / O lines IO0 to IO0 based on 2-bit internal address signals Y0 and Y1.
Common I / O selection signals AS0 to select IO3
AS3 is formed alternatively, and the main amplifier groups MAG0 to MAG are formed.
Supply to AG3. Further, the Y predecoder YPD is
Although not particularly limited, the internal address signals Y2 to Y9 are set to 2
By decoding by combining bits or 3 bits, the predecode signal YP, that is, Y0 to Y7, A
Y50 to AY57 and AY80 to AY83 are formed alternatively.

Next, Y address decoders YD0 to YD3
Although not particularly limited, a total of 256 NOR gate circuits NO1 to NO1 provided corresponding to each complementary bit line group, that is, bit line selection signals YS0 to YS255, as represented by Y address decoder YD0 in FIG. NO2
And a total of 32 unit Y address decoders UYD0 to UYD0 to UYD0 to U
YD31. It also includes two NOR gate circuits NO3 and NO4 provided corresponding to each redundant complementary bit line group, that is, bit line selection signals YR0 and YR1, and two unit Y addresses provided corresponding to these NOR gate circuits. Decoders UYDR0 and UYDR1 are included. Among them, the NOR gate circuits NO1 to NO2
Although there is no particular limitation, adjacent eight are grouped. One input terminal of each of the eight NOR gate circuits NO1 to NO2 and the like constituting each group is supplied with a corresponding predecode signal Y0 to Y7, and the other input terminal is supplied with a corresponding NAND gate circuit NA2. That is, the output signals YG0 to YG31 of the unit Y address decoders UYD0 to UYD31 are commonly supplied.

Although not particularly limited, predecode signals AY80 to AY83 and AY50 to AY57 are supplied to the first and second input terminals of the NAND gate circuit NA2 in a predetermined combination. The third input terminal is coupled to the power supply voltage of the circuit and to the ground potential of the circuit via a resistor R4. The wiring between the third input terminal of the NAND gate circuit NA2 and the power supply voltage of the circuit and the wiring between the resistor R4 and the ground potential of the circuit are both formed via the uppermost aluminum wiring layer AL1. And CP37. Thereby, the unit Y address decoder UYD0
Output signals YG0-YG31 of the predecode signal AY50
To AY57 and AY80 to AY83 are selectively set to low level on condition that they are set to high level in a corresponding predetermined combination. Then, on the condition that the corresponding output signals YG0 to YG31 are at a low level and the corresponding predecode signals Y0 to Y7 are at a low level, bit line selection signals YS0 to YS255 are alternatively set to a high level. , Common I / O to which the corresponding four complementary bit lines of memory array ARYL selectively correspond
It is connected to line I O0~ I O3.

On the other hand, one input terminal of NOR gate circuits NO3 and NO4 provided corresponding to bit line selection signals YR0 and YR1 for the redundant complementary bit line is not particularly limited, but as shown in FIG. Coupled to the ground potential of the circuit via eight N-channel MOSFETs Q54 to Q57 in a parallel form, and a resistor R3
To the power supply voltage of the circuit. The other input terminal of these NOR gate circuits has a corresponding NAND gate circuit NA3, that is, a unit Y address decoder UYDR0.
Alternatively, the output signal YGR0 or YGR1 of UYDR1 is supplied. The gates of the MOSFETs Q54 to Q57,
Corresponding predecode signals Y0 to Y7 are supplied. Although not particularly limited, MOSFETs Q54 to Q57
Are formed through the uppermost aluminum wiring layer AL1, and are connected to the cutting points CP28 to CP28.
CP31 and the like and CP32 to CP35 and the like.

Unit Y address decoders UYDR0 and UYDR0
First and second input terminals of a NAND gate circuit NA3 constituting YDR1 are coupled to output terminals of inverter circuits N6 and N7, respectively. The third input terminal is coupled to the ground potential of the circuit and to the power supply voltage of the circuit via a resistor R5. The wiring between the third input terminal of the NAND gate circuit NA3 and the ground potential of the circuit and the wiring between the resistor R5 and the power supply voltage of the circuit are both formed via the uppermost aluminum wiring layer AL1. And CP39. The input terminal of the inverter circuit N6 is coupled to the ground potential of the circuit via four N-channel MOSFETs Q58 to Q61 arranged in parallel, and further coupled to the power supply voltage of the circuit via a resistor R6. MOSFETQ58-Q61
Of the corresponding predecode signals AY80 to AY80
Y83 are supplied respectively. In addition, these MOSF
The wiring between the drain of ET and the input terminal of the inverter circuit N6 is formed via the uppermost aluminum wiring layer AL1, and is cut at each of the cut points CP40 to CP43.
It is said. Similarly, the input terminal of the inverter circuit N7 is
8 N-channel MOSFETs Q6 in parallel
2 to Q69 to the ground potential of the circuit, and further to the power supply voltage of the circuit via a resistor R7. MOS
The corresponding predecode signals AY50 to AY57 are supplied to the gates of the FETs Q62 to Q69, respectively. The wiring between the drains of these MOSFETs and the input terminal of the inverter circuit N7 are both formed via the uppermost aluminum wiring layer AL1, and are cut off points CP44 to CP51, respectively.

In the initial state of the dynamic RAM in which the disconnection points CP28 to CP51 are not all disconnected, the unit Y address decoders UYDR0 and UYDR1
Is fixed at the ground potential of the circuit, that is, at a low level, and its output signals YGR0 and YGR1 are fixed at a high level. Therefore, the bit line selection signals YR0 and YR1 are fixed at the low level, and the unit Y address decoder UYDR
0 and UYDR1 have virtually no effect.

When a short circuit failure or the like is detected in any of the complementary bit lines in the function test of the dynamic RAM in the wafer state, first, a redundant complementary bit line is allocated by the test apparatus, and the related wiring correction data is transferred. It is transmitted to the correction device. And a Y address decoder Y
In D0, the cutting points CP29 to CP31 and CP3
2 to CP35 are all cut except for the required one, and the cut points CP40 to CP43 and CP44 to CP51
Are cut, except for the required one, and the cutting point CP38 is cut. As a result, the unit Y
The address decoder UYDR0 or UYDR1 becomes substantially effective, and the bit line selection signal YR0 or YR1 is used under the same selection conditions as the replaced complementary bit line group, in other words, the predecode signals AY50 to AY57 and AY80 to AY83 correspond. And the corresponding predecode signal Y0
To a high level, provided that .about.Y7 is at a low level. Thereby, the complementary bit line group including the defective complementary bit line is replaced with the redundant complementary bit line group, and the redundant switching of the complementary bit line is realized.

As is clear from the above description of the X-system and Y-system selection circuits, the redundancy switching in the dynamic RAM of this embodiment is performed by the X address decoder XDL or the X address decoder XDL.
The predetermined wiring of the DR or Y address decoders YD0 to YD3 is efficiently realized by being selectively cut by a wiring correction apparatus which receives wiring correction data in-line from a test apparatus which performs a probe test in a wafer state. . Needless to say, this dynamic R
Redundant switching in AM is based on the conventional dynamic R
There is no need for a comparison and collation operation between the defective address performed in the AM and the address supplied at the time of memory access, and no hardware is required for the operation. For this reason, in the dynamic RAM of this embodiment, the time required to select a word line or a complementary bit line is shortened regardless of the presence or absence of redundant switching, and the access time of the dynamic RAM is correspondingly shortened. At the same time, the number of circuit elements required for redundant switching is reduced, and the chip area of the dynamic RAM is reduced.

3.3. Application to Redundancy Switching System by Address Comparison and Collation FIG. 20 is a partial block diagram in the case where the wiring disconnection by the wiring correction device is applied to a conventional dynamic RAM employing a redundancy switching system by address comparison and comparison. 21 and 22 show a partial circuit diagram and a sectional structure diagram of one embodiment of the defective address ROM included in the dynamic RAM of FIG. 20, respectively.

In FIG. 20, a dynamic RAM
Includes four defective address ROMs (ROM0 to ROM3) provided corresponding to redundant word lines WR0 to WR3 and address comparison circuits XAC0 to XAC3, and further provided corresponding to redundant bit line selection signals YR0 and YR1. Two defective address ROMs (ROM 4 and RO
M5) and the address comparison circuits YAC0 and YAC1
Is provided. These defective address ROMs and address comparison circuits operate in the same manner as the conventional dynamic RAM except for the following points, and selectively set the corresponding redundant word line or redundant complementary bit line to a selected state. .

That is, in this embodiment, the defective address ROMs (ROM0 to ROM5) are represented by the defective address ROM (ROM0) in FIG.
For example, 8 provided corresponding to each bit of the defective address
The unit fuse circuits UFC0 to UFC7 are provided. In addition, as shown in FIG. 22, these unit fuse circuits are formed through the uppermost aluminum wiring layer AL1 and are formed at cutting locations C which function as substantial fuse means.
P52 to CP58. Unit fuse circuit U
Non-inverting and inverting signal of the complementary output signal E X00~ E X07 of FC0~UFC7 the corresponding cut points CP52~C
By cutting P58, the level is selectively set to a high level or a low level, respectively. As a result, these unit fuse circuits function as a ROM (read only memory) for storing a defective address assigned to a redundant word line or a redundant complementary bit line.

In this embodiment, the defective address ROM
(ROM0 to ROM5) provided at a cutting point CP52
CP58 and the like are cut by a high-precision wiring correction device. Therefore, these cut portions can be formed with a layout pitch significantly smaller than that of the conventional fuse means formed using polysilicon. As a result, the required layout area of the defective address ROM is correspondingly reduced, and the chip area of the dynamic RAM is reduced.

4. Power Circuit and Internal Voltage Trimming Method In the dynamic RAM according to this embodiment, circuit elements constituting the memory array and its peripheral circuits are becoming finer and larger in capacity. Be seen. Therefore, most internal circuits of the dynamic RAM use the internal power supply voltage VCL having a relatively small absolute value such as +3.3 V as its operation power supply voltage, and the step-down circuit VD for forming the internal power supply voltage VCL has Provided. On the other hand, in the dynamic RAM of this embodiment, a method is employed in which a predetermined substrate back bias voltage VBB is applied to a P-type semiconductor substrate to control the operating characteristics of the MOSFET to stabilize the operation. A substrate potential generation circuit VBBG for forming voltage VBB is provided. Furthermore, in the dynamic RAM of this embodiment, as described above, the predetermined high voltage VCH whose absolute value is larger than the internal power supply voltage VCL is selectively transmitted to the designated word line, thereby selecting the word line. , And a high voltage generating circuit VCHG for generating the high voltage VCH is provided. Hereinafter, configurations of the step-down circuit VD and the substrate potential generating circuit VBBG and a method of trimming the internal power supply voltage VCL and the substrate back bias voltage VBB will be described.

4.1. Step-Down Circuit and Trimming Method of Internal Power Supply Voltage FIG. 23 shows a step-down circuit V of the dynamic RAM shown in FIG.
A circuit diagram of one embodiment of D is shown. In FIG. 23, a step-down circuit VD is a differential MOS
Three operational amplifier circuits OA1 to OA having a basic configuration of FET
A3 and a reference potential switching circuit VLS which also has a differential MOSFET as a basic configuration, and forms a predetermined internal power supply voltage VCL based on an external power supply voltage VCC supplied via an external terminal VCC. In this embodiment, the external power supply voltage VCC is not particularly limited, but is +5.0 V
And the internal power supply voltage VCL is
As described above, the voltage is set to + 3.3V.

The gate of one differential MOSFET Q70 constituting the operational amplifier circuit OA1 of the step-down circuit VD is supplied with a constant voltage VRN from a constant voltage generating circuit (not shown), and the drain thereof is a P-channel type. Output MOSFET Q3. The source of output MOSFET Q3 is coupled to external power supply voltage VCC, and its drain is coupled to reference potential output node VL via a P-channel MOSFET Q4 whose gate receives internal control signal TVLK. Through R16 to the ground potential of the circuit. The common coupled nodes of two adjacent resistors of these series resistors are connected to N-channel MOSFETs Q72-Q
79 is coupled to the gate of the other differential MOSFET Q71. The gates of the MOSFETs Q72 to Q79 are
Although not particularly limited, corresponding test pads TP1 to TP
8 respectively. Also, the corresponding resistors R16 to
It is coupled to external power supply voltage VCC via R23 and to the ground potential of the circuit via corresponding resistors R24 to R31. The wiring between the resistors R16 to R23 and the external power supply voltage VCC is formed via the uppermost aluminum wiring layer AL1, and is made to be a cutting point CP71 to CP78, respectively. Similarly, the wiring between the resistors R24 to R31 and the ground potential of the circuit is formed via the uppermost aluminum wiring layer AL1, and is cut at CP79 to CP86, respectively.

When the disconnection points CP71 to CP86 are not disconnected and the dynamic RAM is in the initial state, the MOSFETs Q72 to Q79 apply high-level test control such as the external power supply voltage VCC to the corresponding test pads TP1 to TP8. The signal is alternatively turned on by the supply of the signal. At this time, the reference potential VL is divided by the combined resistance RH of the series resistance on the reference potential output node VL side of the MOSFETs Q72 to Q79 turned on and the combined resistance RL of the series resistance on the ground potential side of the circuit. After that, as the feedback voltage VRF, the differential MOSFET Q7
1 gate. Feedback voltage VRF is constant voltage VR
When it is lower than N, the drain voltage of the differential MOSFET Q70, that is, the gate voltage of the output MOSFET Q3 is lowered. Therefore, the conductance of output MOSFET Q3 is increased, and reference potential VL, ie, feedback voltage VR
F is raised. On the other hand, when the feedback voltage VRF is the constant voltage VRN
When it is higher, the drain voltage of the differential MOSFET Q70, that is, the gate voltage of the output MOSFET Q3 is raised. Therefore, the conductance of output MOSFET Q3 is reduced, and reference potential VL, ie, feedback voltage VRF
Is lowered. That is, the operational amplifier circuit OA1 acts to match the potentials of the feedback voltage VRF and the constant voltage VRN, and as a result, acts to set the reference potential VL to a potential of VL = VRN × (1 + RH / RL). Becomes

The reference potential VL is supplied to the gate of one differential MOSFET Q82 forming the operational amplifier circuit OA2 and to the gate of one differential MOSFET Q84 forming the operational amplifier circuit OA3. The operational amplifier OA2 has a relatively large conductance P
It includes a channel type output MOSFET Q6 and has a relatively large current supply capability. And dynamic type R
AM is set to the selected state, and the internal control signal LC is set to the high level to be selectively set to the operation state.
It acts to make L equal to the internal power supply voltage VCL.
On the other hand, the operational amplifier circuit OA3 includes a P-channel type output MOSFET Q7 having a relatively small conductance and has a relatively small current supply capability. The operational amplifier circuit OA3 is constantly in an operating state, and similarly acts to make the reference potential VL coincide with the internal power supply voltage VCL. As a result, the internal power supply voltage VCL becomes Potential.

As described above, the values of the combined resistors RH and RL are selectively switched by supplying a high-level test control signal to the test pads TP1 to TP8. Although not particularly limited, these test control signals are supplied from a test apparatus in a dynamic RAM probe test performed in a wafer state. The test apparatus creates wiring correction data for cutting the cutting points CP71 to CP86 based on the test results, and sends the data to the wiring correction apparatus inline. Then, according to the wiring correction data sent from the test device, the wiring correction device performs the above-described cutting point C.
P71 to CP86 are selectively combined and cut. Thereby, the reference potential VL is trimmed to the optimum level.

4.2. Substrate Potential Generating Circuit and Trimming Method of Substrate Back Bias Voltage FIG. 24 is a circuit diagram of an embodiment of the substrate potential generating circuit VBBG of the dynamic RAM shown in FIG. In FIG. 24, substrate potential generating circuit VBBG includes, but is not limited to, a level detecting circuit LVC, an oscillating circuit OSC, and a charge pump circuit CP. VBB is formed.

The level detection circuit LVC of the substrate potential generation circuit VBBG is not particularly limited, but is provided in series between the input terminal of the inverter circuit N6 acting as a level determination circuit and the substrate back bias voltage supply point VBB. N-channel MOSFETs Q86 to Q88. Of these, the inverted signal of the internal control signal VBTB is supplied to the gate of the MOSFET Q86, although not particularly limited, and the gates and drains of the MOSFETs Q87 and Q88 are in a diode form by being commonly coupled. An N-channel MOSFET is connected between the commonly coupled gate and drain of MOSFET Q87 and the commonly coupled gate and drain of MOSFET Q88.
Q89 is provided, and an N-channel MOSFET Q90 is provided between the commonly coupled gate and drain of MOSFET Q88 and the substrate back bias voltage supply point VBB. The gates of these MOSFETs Q89 and Q90 are coupled to corresponding test pads TP9 and TP10, respectively. Also, the corresponding resistors R32 and R3
3 and to the substrate back bias voltage supply point VBB via corresponding resistors R34 and R35. Resistance R32 and R33
And the power supply voltage of the circuit are formed by the uppermost aluminum wiring layer AL1 and each of the cut points CP
87 and CP88. Similarly, resistors R34 and R
The wiring between 35 and the substrate back bias voltage supply point VBB is formed by the uppermost aluminum wiring layer AL1, and is made to be a cutting point CP89 and CP90, respectively.

When the disconnection points CP87 to CP90 are not disconnected and the dynamic RAM is in the initial state, the MOSFETs Q89 and Q90 apply high-level test control such as the internal power supply voltage VCL to the corresponding test pads TP1 to TP8. The signal is selectively turned on by the supply of the signal. At this time, MOSFETs Q87 and Q88 are selectively enabled by turning off corresponding MOSFETs Q89 or Q90, whereby the determination level of substrate back bias voltage VBB by inverter circuit N6 is selectively set. That is,
The output signal of the inverter circuit N6 is, for example, MOSFET
Q89 and Q90 are both turned off and MOSFET
When both Q87 and Q88 are valid, the absolute value of the substrate back bias voltage VBB is selected by making it smaller than 2 × Vthn (where Vthn indicates the threshold voltage of an N-channel MOSFET; the same applies hereinafter). And the level detection circuit LVC
Are selectively made low level. Further, for example, one of the MOSFETs Q89 and Q90 is turned off, and the MOSFETs Q87 and Q8 are turned off.
8 is made valid, the absolute value of the substrate back bias voltage VBB is made smaller than Vthn to be selectively set to a low level, whereby the inverted output signal VBSB of the level detection circuit LVC is selectively set. Set to low level. That is, by selectively turning off or on the MOSFETs Q89 and 90, the determination level of the level detection circuit LVC, that is, the substrate back bias voltage VBB of the substrate potential generation circuit VBBG is selectively trimmed. .

The inverted output signal VB of the level detection circuit LVC
SB is supplied to one input terminal of the NAND gate circuit NA4 of the oscillation circuit OSC, although not particularly limited. The other input terminal of the NAND gate circuit NA4 is supplied with an inverted internal control signal R1B which is selectively set to a low level when the dynamic RAM is set to the selected state. The oscillation circuit OSC further includes a so-called ring oscillator in which the inverter circuit N7 and the two NAND gate circuits NA5 and NA6 are coupled in a ring shape. The output signal of the NAND gate circuit NA4 is commonly supplied to the other input terminals of the NAND gate circuits NA5 and NA6.
As a result, the ring oscillator including the NAND gate circuits NA5 and NA6 outputs the absolute value of the substrate back bias voltage VBB when the output signal of the NAND gate circuit NA4 is at a high level, in other words, the inverter circuit N4.
6, when the inverted output signal VBSB of the level detection circuit LVC is set to a low level, or when the dynamic RAM is set to the selected state and the inverted internal control signal R1B is set to the low level, the operating state is selectively set. Thus, a pulse signal OSCV having a predetermined frequency is formed.

The output signal of the oscillation circuit OSC, that is, the pulse signal OSCV is supplied to one electrode of the boost capacitor C1 constituting the charge pump circuit CP via a drive circuit including four NAND gate circuits and an inverter circuit. The other electrode of the boost capacitance C1 is coupled to the ground potential of the circuit via an N-channel MOSFET Q91 in the form of a diode, and is connected to a substrate back bias voltage supply point via an N-channel MOSFET Q92 also in the form of a diode. Connected to VBB. When the pulse signal OSCV is at a low level, one electrode of the boost capacitor C1 is pushed up to a high level such as the internal power supply voltage VCL. This high level is
The voltage is transmitted to the other electrode of the boost capacitor C1,
The potential is Vth due to the clamping action of FET Q91.
n. When the pulse signal OSCV is changed to a high level, one electrode of the boost capacitor C1 is set to a low level such as the ground potential of the circuit. This low level is transmitted to the other electrode of the boost capacitance C1, whereby the potential is set to a negative potential such as-(VCL-Vthn). The negative potential of the other electrode of the boost capacitor C1 is transmitted to the substrate back bias voltage supply point VBB via the MOSFET Q92. As a result, the value of the substrate back bias voltage VBB is set to a negative potential of VBB = − (VCL−2 × Vthn). Needless to say, the absolute value of the set potential of the substrate back bias voltage VBB exceeds the determination level of the level detection circuit LVC. Therefore, when the potential of the substrate back bias voltage VBB reaches the set potential, the operations of the oscillation circuit OSC and the charge pump circuit CP are automatically stopped on condition that the dynamic RAM is not in the selected state.

The substrate back bias voltage VBB is supplied to the P-type semiconductor substrate PSUB and is used to control the operation characteristics and the like of the MOSFET. The level of the substrate back bias voltage VBB gradually rises due to the flow of a leak current through the semiconductor substrate, and its absolute value eventually becomes smaller than the determination level of the level detection circuit LVC. As a result, the inverted output signal VBSB of the level detection circuit LVC
Is set to the low level again, and the above operation is repeated.
As described above, the determination level for the substrate back bias voltage VBB of the level detection circuit LVC, that is, the substrate potential generation circuit VBBG, is a high-level or low-level test on the test pad TP9 or TP10 in a dynamic RAM probe test or the like in a wafer state. It is selectively switched by supplying a control signal. Then, based on the test results, the cutting points CP87 to CP87
Wiring correction data for selectively cutting 90 is generated by a test device, and a cutting process based on the wiring correction data is executed by a predetermined wiring correction device.
As a result, the determination level of the level detection circuit LVC and thus the substrate potential generation circuit VBBG is fixed, and the trimming ends.

5. Timing Generating Circuit and Delay Time Trimming Method The dynamic RAM according to this embodiment includes a timing generating circuit TG for forming the above-described various internal control signals. Although not particularly limited, the timing generation circuit TG includes a row address strobe signal R as an activation control signal.
ASB, column address strobe signal CASB, write enable signal WEB, and output enable signal OEB
, And the internal address signal X8 is supplied from the X address buffer XAB. The timing generation circuit TG
Various internal control signals are formed based on the start control signal and the internal address signal X8, and a dynamic RA signal is generated.
M to each part. Note that the output enable signal OEB
Are selectively enabled when the dynamic RAM has a × 4 bit configuration, as described later.

Incidentally, the dynamic type R of this embodiment
The AM timing generation circuit TG is not particularly limited, but includes an internal control signal PA for driving the sense amplifier.
And a plurality of delay circuits DL for forming internal control signals YDG for driving the Y address decoder and internal control signals MAW and MAR for driving the main amplifier, and for setting the timing of these internal control signals. . In this embodiment, all or some of these delay circuits DL are not particularly limited, but as shown in FIG. 25, three inverter circuits N for transmitting an input signal S are provided.
9 to N11. The output signal of the inverter circuit N10 is a non-inverted delay signal SD, and the inverter circuit N11
Is an inverted delay signal SDB. Between the output terminal of the inverter circuit N9 and the ground potential of the circuit, although not particularly limited, the N-channel MOSFETs Q93
Four sets of series circuits including Q96 and capacitors C2 to C5 are provided in parallel. MOSFET Q93 ~
The gate of Q96 is connected to corresponding test pads TP11 to TP
14 respectively. Also, the corresponding resistor R36
To R39, and to the ground potential of the circuit via corresponding resistors R40 to R43. The wiring between the resistors R36 to R39 and the power supply voltage of the circuit is formed via the uppermost aluminum wiring layer AL1, and is made to be a cutting point CP91 to CP94, respectively. Similarly, wiring between the resistors R40 to R43 and the ground potential of the circuit is formed via the uppermost aluminum wiring layer AL1, and is cut at CP95 to CP98, respectively.

In the initial state of the dynamic RAM in which the cutting points CP91 to CP98 are not both in the cutting state,
MOSFETs Q93 to Q96 are connected to corresponding test pads T
P11 to TP14 are selectively turned on by supplying a high-level test control signal. At this time, the output terminals of the inverter circuit N9 are selectively coupled with the capacitors C2 to C5 corresponding to the MOSFETs Q93 to Q96 which are turned on, whereby the level change speed of the output signal, that is, the input of the delay circuit DL, The delay time for the signal S is selectively switched. As a result, the rises of the internal control signals PA and YDG and MAW and MAR are selectively switched, and the drive timing of the sense amplifier, Y address decoder, or main amplifier is switched. Although these timing settings are not particularly limited, they are tried in a dynamic RAM probe test in a wafer state,
The wiring correction data created based on this test result is sent to the wiring correction device in-line. Then, the corresponding cutting portions CP91 to CP98 are selectively cut, and the trimming of the drive timing ends.

6. Signature Circuit and Trimming Method of Its Discrimination Level As described above, the dynamic RAM of this embodiment has four redundant word lines WR0 to WR3 and eight sets of redundant complementary bit lines corresponding to the memory arrays ARYL and ARYR. B R0 to B R7 are provided, these redundant word lines and redundant complementary bit lines called defect repair is carried out by selectively be assigned to the defective word line or defective complementary bit line. Dynamic RAM of this embodiment
Is provided with a signature function capable of externally identifying after the completion of the product that the defect relief by the redundant word line or the redundant complementary bit line has been performed, and a signature circuit SIG for that purpose is provided. In this embodiment, although the determination of the presence / absence of defect repair by the signature circuit SIG is not particularly limited, there is a change in the standby current of the dynamic RAM by applying a predetermined high voltage to the data input / output terminal DIO3, that is, the data output terminal Dout. It is done by measuring whether or not.

Although not particularly limited, the signature circuit SIG may have a data input / output terminal D as shown in FIG.
IO3, that is, includes a resistor R44, N-channel MOSFETs Q97 to Q99, and a P-channel MOSFET Q8 provided in series between the data output terminal Dout and the ground potential of the circuit. MOSFET Q
The gates and drains of the transistors Q97 and Q98 are in the form of a diode by having their gates and drains connected in common.
Are supplied with the internal power supply voltage VCL. The gate of the MOSFET Q99 is supplied with an inverted signal of the internal control signal SIG formed by taking the logical sum of the redundancy switching signal of each address decoder by the inverter circuit N12. This internal control signal SIG is
As described above, when any one of the redundant word lines or redundant complementary bit lines repairs a defect, the level is selectively set to a high level. An N-channel MO is provided between the commonly coupled gate and drain of MOSFET Q97 and the commonly coupled gate and drain of MOSFET Q98.
An SFET Q100 is provided, and an N-channel MOSFET Q101 is connected between the commonly coupled gate and drain of MOSFET Q98 and the source of MOSFET Q8.
Is provided. These MOSFETs Q100 and Q1
01 are connected to corresponding test pads TP15 and TP15.
16 respectively. Also, the corresponding resistor R45
And R46 to the supply voltage of the circuit, and to the ground potential of the circuit via corresponding resistors R47 and R48. The wiring between the resistors R45 and R46 and the power supply voltage of the circuit is formed by the uppermost aluminum wiring layer AL1, and is cut at CP99 and CP10, respectively.
It is set to 0. Similarly, the wiring between the resistors R47 and R48 and the ground potential of the circuit is the uppermost aluminum wiring layer A
It is formed by L1 and is made to be a cutting point CP010 and CP102, respectively.

When the disconnection points CP99 to CP102 are not disconnected and the dynamic RAM is in the initial state, the MOSFETs Q100 and Q101 apply a high-level test control signal such as the internal power supply voltage VCL to the corresponding test pad TP15 or TP16. Are selectively turned on by being supplied. At this time, MOSFE
TQ97 and Q98 are the corresponding MOSFET Q100
Alternatively, when Q101 is turned off, it is selectively enabled, whereby the identification level of the signature circuit SIG for the high voltage test control signal supplied from the data input / output terminal DIO3 is selectively set. That is,
For example, when MOSFETs Q100 and Q101 are both turned off and MOSFETs Q97 and Q98 are both enabled, a high voltage test supplied from data input / output terminal DIO3 is connected between data input / output terminal DIO3 and the ground potential of the circuit. The level of the control signal is 2 × Vthn + V
thp (where VthP is a P-channel MOSFE
T threshold voltage) and MOSFET Q
When the signal 99 is turned on, in other words, when the defect repair is not performed by the redundant word line or the redundant complementary bit line and the internal control signal SIG is set to the low level, a current is selectively passed. On the other hand, for example, MOSFET Q100
Or either of Q101 is turned off and MOSFET
When either Q97 or Q98 is validated,
A selective connection between the data input / output terminal DIO3 and the ground potential of the circuit when the level of the high voltage test control signal supplied from the data input / output terminal DIO3 exceeds Vthn + Vthp and the MOSFET Q99 is turned on. Current is passed through the That is, the data input / output terminal DIO3
By supplying the above-described test control signal of a predetermined high voltage and measuring the change in the standby current of the dynamic RAM, it is possible to identify whether or not the dynamic RAM has been switched redundantly after the package is enclosed.

As described above, the data input / output terminal DIO3
The identification level of the signature circuit SIG with respect to the high-voltage test control signal supplied through the test pad TP1
5 and TP16 are selectively switched by supplying a high-level test control signal. Such switching is not particularly limited, but is attempted in a dynamic RAM probe test in a wafer state, and wiring correction data created based on the test result is sent to the wiring correction device in-line. The trimming of the identification level of the signature circuit SIG is completed by selectively cutting the corresponding cutting points CP99 to CP101.

7. Switching system between data input / output circuit and bit configuration As described above, the dynamic RAM of this embodiment
It comprises four main amplifier groups MAG0 to MAG3, and these main amplifier groups and data input signal lines DI0 to DI3
A data input / output circuit DIO coupled via data output signal lines DO0 to DO3. In this embodiment, the dynamic RAM is not particularly limited, but its bit configuration is selectively changed to a × 1 bit configuration or a × 4 bit configuration by cutting a predetermined wiring in a predetermined combination. 4x dynamic RAM
In the case of the bit configuration, write and read data are input or output to the barrel via the data input / output terminals DIO0 to DIO3. Also, dynamic RAM
Has a × 1 bit configuration, write data is input through the data input / output terminal DIO0, that is, the data input terminal Din, and read data is input to the data input / output terminal DIO3, that is, the data output terminal Dout, although not particularly limited. Output via

The data input / output circuit DIO is not particularly limited, but includes four data input buffers DIB0 to DIB0 provided corresponding to the data input / output terminals DIO0 to DIO3.
B3 and data output buffers DOB0 to DOB3. Of these, the data input buffers DIB0 to DIB0
The input terminal of B3 is a corresponding data input / output terminal DIO0.
To DIO3, and their output terminals are respectively coupled to corresponding data input signal lines DI0 to DI3 on condition that the dynamic RAM has a × 4 bit configuration. Although not particularly limited, dynamic type R
When AM has a × 1 bit configuration, the output terminals of data input buffer DIB0 are commonly coupled to substantially all data input signal lines DI0 to DI3, and memory module select signal NA0 is connected to these data input signal lines. ~ N
A write signal is transmitted alternatively according to A3. on the other hand,
The input terminals of the data output buffers DOB0 to DOB3 are
The corresponding data output signal lines DO0 to DO3 are coupled to respective output terminals, and the output terminal thereof is a dynamic RAM of × 4.
The data input / output terminals DIO0 to DIO3 are coupled to each other on condition that they have a bit configuration.
When the dynamic RAM has a × 1 bit configuration,
The input terminals of the data output buffer DOB3 are commonly connected to substantially all data output signal lines DO0 to DO3,
A read signal output via these data output signal lines is alternatively transmitted to a data input / output terminal DIO3 in accordance with memory module selection signals NA0 to NA3. When the dynamic RAM has a × 1 bit configuration, the memory module selection signals NA0 to NA3 are alternatively set to a high level in accordance with upper two bits of Y address signals AY10 and AY11, and the dynamic RAM has a × 4 bit configuration. Is set to a high level all at once.

As shown in FIG. 27, data input buffers DIB0 to DIB3 of data input / output circuit DIO have NAND gate circuits NA7 to NA7 whose one input terminals are coupled to corresponding data input / output terminals DIO0 to DIO3. NA10 respectively. An internal control signal R1 which is selectively set to a high level at a predetermined timing when the dynamic RAM is selected is commonly supplied to the other input terminals of these NAND gate circuits.
Further, there is no particular limitation between the other input terminals of the NAND gate circuits NA8 to NA10 constituting the data input buffers DIB1 to DIB3 and the ground potential of the circuit.
Channel MOSFETs Q102 to Q104 are provided, respectively. The commonly coupled gates of these MOSFETs are coupled to the circuit power supply voltage via a resistor R50 and to the circuit ground potential via a resistor R51. The wiring between the resistor R50 and the power supply voltage of the circuit is
Formed by the uppermost aluminum wiring layer AL1,
This is a cutting point CP107. Similarly, a wiring between the resistor R51 and the ground potential of the circuit is formed by the uppermost aluminum wiring layer AL1, and is set as a cutting position CP108. Similarly, the wiring between the drains of the MOSFETs Q102 to Q104 and the internal control signal line R1 is similarly formed by the uppermost aluminum wiring layer AL1, and serves as cutting points CP104 to CP106, respectively.

The cutting points CP104 to CP108 are:
When the product specification of the dynamic RAM, that is, its bit configuration is determined, it is selectively cut by the wiring correction device. That is, when the dynamic RAM has a × 4 bit configuration, the cutting points CP104 to CP106 and CP108 are not cut off, and the cutting point CP1 is not cut.
07 is disconnected. Therefore, MOSFET Q1
02 to Q104 are all turned off, and internal control signal R1 is transmitted in common to the other input terminals of NAND gate circuits NA7 to NA10 of data input buffers DIB0 to DIB3. As a result, the data input buffers DIB0 to DIB0
DIB3 is all valid and the data input / output terminal DIO
The 4-bit write data input through 0 to DIO3 is transmitted to corresponding data input signal lines DI0 to DI3. At this time, in the timing generation circuit TG,
Although not particularly limited, as shown in FIG.
Disconnection point CP provided between circuit 49 and the ground potential of the circuit
103 is disconnected, and the output enable signal OEB is made valid.

On the other hand, when the dynamic RAM has a × 1 bit configuration, the cutting point CP107 is not cut,
The cutting points CP104 to CP106 and CP108 are cut. Therefore, MOSFETs Q102 to Q10
4, the internal control signal R1 is not transmitted to the other input terminals of the NAND gate circuits NA8 to NA10 constituting the data input buffers DIB1 to DIB3. As a result, the data input buffers DIB1 to DIB
3 is invalid, and 1-bit write data input from the data input / output terminal DIO0 via the data input buffer DIB0 is transmitted in common to the data input signal lines DI0 to DI3. At this time, in the timing generation circuit TG, the cut point CP103 is not cut, and the input terminal of the inverter circuit N13 is fixed at the low level via the resistor R49. As a result, the internal control signal CE is fixed at a high level, and the dynamic RAM does not need the output enable signal OEB.

8. Wiring Correction Device and Processing Steps As described above, the dynamic RAM of this embodiment is provided with a plurality of cutting locations, and these cutting locations are selectively cut in a predetermined combination by the wiring correction device. , DC defect relief, redundancy switching, trimming of operation characteristics, or switching of product specifications are selectively realized. In this embodiment, the wiring correction device includes:
Although not particularly limited, it is configured on the basis of an EB direct writing apparatus, an FIB apparatus, or a laser repair apparatus, and is connected to a test apparatus online.

8.1. Wiring Correction Device FIG. 28 shows the EB constituting the wiring correction device of this embodiment.
A performance comparison diagram of the direct writing device, the FIB device, and the laser repair device is shown. Of these, the EB direct drawing device
EB generated by the electron gun, accelerated and focused (Er
By controlling the direction of travel of the electron beam by a deflection system using electromagnetic deflection or electrostatic deflection, for example, the resist applied on the chip is directly removed, and predetermined wiring is cut or added. Since the EB direct writing apparatus uses an electron beam, the beam diameter can be made extremely small, and has a high resolution performance. The control unit includes a central processing unit CPU, a dynamic RAM
Can be connected online with a test device that performs a probe test in the manufacturing process.

On the other hand, the FIB apparatus is an FIB (Focused) generated by, for example, a gallium metal ion source.
Ion Beam), that is, scanning of a high-performance focused ion beam, allows cutting of wiring by sputter etching and FIB / CVD (Chemical Vap).
or Deposition). High resolution performance comparable to EB direct drawing equipment. Also, E
Like the direct-write B apparatus, it has a control unit composed of a central processing unit CPU, and can be connected online with a test apparatus in the process of manufacturing a dynamic RAM.

Further, the laser repair device cuts the polysilicon or the like formed on the chip by, for example, controlling the deflection of the laser beam generated by the semiconductor laser-excited solid. Although it is not suitable for adding a metal wiring layer having a high reflectivity or a new wiring, it is possible to realize a cutting process with relatively low accuracy at a relatively low cost. Like the EB direct writing apparatus and the FIB apparatus, the apparatus includes a control unit including a central processing unit CPU, and can be connected online with a test apparatus in a dynamic RAM manufacturing process.

8.2. Connection between Wiring Correction Device and Test Apparatus FIG. 29 is a connection diagram of an embodiment between the wiring correction apparatus and the test apparatus of this embodiment. This drawing shows a part of the process of manufacturing the dynamic RAM, and shows the wiring repair device DWE and the test device TE.
Are combined online in this manufacturing process.

In FIG. 29, the test apparatus TE employs, but is not limited to, a stored program method, and performs a function test of a plurality of dynamic RAMs formed on the wafer WF in a wafer state via a prober. .
Then, the performance and operation characteristics of the dynamic RAM are determined by the functional test, and a failure of a word line or a complementary bit line constituting the memory array is detected. The test apparatus TE determines trimming conditions for level setting and timing setting based on these test results, and allocates redundant word lines or redundant complementary bit lines. After a while
The wiring correction data TD for a plurality of cutting locations prepared in the dynamic RAM is created and transmitted online to the wiring correction device DWE. Note that the wiring correction data regarding the cutting location may be created in the wiring correction device DWE based on the test results obtained by the test device TE.

The wiring repair device DWE is provided with the test device TE.
Wafer W according to wiring correction data TD supplied from
Cutting is performed by selectively combining a plurality of cutting locations provided in the dynamic RAM on F. Wiring correction device DW
E includes a storage device for holding the corresponding wiring correction data until the wafer WF to be subjected to wiring correction is moved from the test apparatus TE. In this embodiment, each of the cutting points of the dynamic RAM is entirely formed by the uppermost aluminum wiring layer AL1, or a part thereof is connected at least at each cutting point via the uppermost aluminum wiring layer AL1. You. Note that the wiring correction device DWE may have a function of adding a new wiring, or may perform a so-called batch process of wiring correction data obtained by the test device TE.

8.3. Processing Steps FIG. 30 is a partial processing step diagram of one embodiment in which the wiring correction apparatus of this embodiment is configured based on an EB direct drawing apparatus. FIG. 31 is a partial process fixing diagram of an embodiment in which the wiring correction apparatus of this embodiment is configured based on an FIB apparatus or a laser repair apparatus. With reference to these drawings, an outline of processing steps related to wiring cutting using the wiring correction device will be described.

In FIG. 30, a wafer which has been subjected to a series of pattern forming steps for forming a dynamic RAM on a semiconductor substrate is not particularly limited, but first, in a H ₂ (hydrogen) atmosphere, in order to prepare for process damage. At about 400 degrees Celsius, for example. Further, in order to prepare for the probe test, only the bonding pad or the test pad portion is opened, the first passivation is performed, and a protective film of about 2000 (angstrom) is formed. In this state, a probe test is performed by a test device, that is, an LSI tester, and wiring correction data created based on the test result is transmitted from the test device to the wiring correction device online. Next, a resist coating process is performed on the wafer, and a resist (photosensitive agent) made of, for example, a novolak-based resin is applied. This resist is directly exposed to an electron beam generated from an EB direct writing apparatus and then subjected to a developing process. At this time, the cut portions of each dynamic RAM to be cut are exposed, and the silane (SiL) protective film and the uppermost aluminum wiring corresponding to these cut portions are exposed by the next SiL dry etching and AL dry etching. The layer AL1 is cut. Finally, after the resist on the wafer is removed and the second passivation is performed, a probe test is again performed by the LSI tester,
The function and performance of the dynamic RAM are confirmed.

On the other hand, when the wiring correction device is configured based on the FIB device or the laser repair device, as shown in FIG. 31, the dynamic RAM is used in accordance with the wiring correction data transferred from the test device, that is, the LSI tester.
Is cut directly by the ion beam generated from the FIB device or the laser beam generated from the laser repair device. Then 2
After the second passivation, a probe test is again performed by the LSI tester, and the dynamic RA
The function and performance of M are confirmed.

As shown in the present embodiment, by applying the present invention to a semiconductor integrated circuit device such as a dynamic RAM having a defect relief function and a wiring repair device therefor, the following operation and effect can be obtained. Can be (1) A probe test of a chip on which a dynamic RAM or the like is formed is performed in a wafer state by a predetermined test device, and the result is used as wiring correction data as an EB direct drawing device, FIB device, or laser repair device. To directly or indirectly cut or add corresponding wiring on the chip based on these wiring correction data, thereby efficiently switching the internal form of the dynamic RAM or the like. Is obtained. (2) In the above item (1), by connecting the test apparatus and the wiring correction apparatus online, a dynamic RA
The effect of further reducing the number of test steps in the manufacturing process of M or the like is obtained. (3) In the above item (1), by forming all or a part of the wiring to be cut or added via the uppermost metal wiring layer, the wiring correction by the wiring correction device can be efficiently realized. The effect is obtained. (4) By using the wiring correction of the above items (1) to (3) for cutting a leakage current path through a defective element or circuit replaced with a redundant element or circuit, a dynamic R
It is possible to obtain an effect that DC defects after redundancy switching of AM or the like can be relieved, and the product yield can be significantly increased. (5) A dynamic RAM is used in which the wiring correction described in the above items (1) to (3) is used in a so-called decoder redundancy switching method in which a logic condition of an address decoder is directly switched to replace a defective element or circuit with a redundant element or circuit. And the like, and an effect that efficient redundancy switching can be realized without impairing the high-speed operation and without significantly increasing the chip area. (6) The wiring correction of the above items (1) to (3) is used for cutting the fuse means provided in the defective address ROM, thereby substantially reducing the layout pitch of the fuse means and providing redundancy by address comparison and collation. The effect of reducing the chip area of a dynamic RAM or the like employing the switching method can be obtained. (7) The dynamic RA configured by using the normal part of the internal circuit to perform the wiring correction of the above items (1) to (3)
By utilizing the current path formed through another part of the partial product such as M which is not normal, the power consumption of the partial product can be reduced. (8) The wiring correction in the above items (1) to (3) is performed by setting the level of the internal power supply voltage formed by the step-down circuit, the level setting of the substrate back bias voltage formed by the substrate potential generating circuit, or the timing generation. By using it for setting the timing of the internal control signal formed by the circuit or setting the discrimination level for the test control voltage of the signature circuit, it is possible to obtain the effect that the operating characteristics of the dynamic RAM and the like can be efficiently switched and trimmed. (9) By using the wiring correction of the above items (1) to (3) for switching product specifications such as a bit configuration, it is possible to efficiently switch product specifications such as a dynamic RAM. Can be (10) According to the above items (1) to (9), the chip area, the operating current, and the number of test steps are reduced without impairing the high-speed performance of a dynamic RAM or the like, and the cost and power consumption are reduced. The effect that it can be obtained is obtained.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the above embodiment, and various modifications can be made without departing from the gist of the invention. Needless to say, there is. For example, in FIG. 1 and FIG. 2, the block configuration of the dynamic RAM can take various embodiments, and its storage capacity, that is, the number of bits of the address signal, and the names and combinations of the start control signal and the internal control signal are as follows. There is no restriction by the embodiment. Also, the units constituting the partial product can be set arbitrarily, and the combination thereof is also arbitrary. The dynamic RAM does not require the use of the shared sense method, and its bit configuration may be, for example, a × 8 or × 16 bit configuration. In FIG. 7, the number of cut points for realizing DC defect relief can be added or reduced as necessary, and each cut point can be formed, for example, through a second layer or a lower aluminum wiring layer or another type of wiring layer. May be formed. Various methods for realizing the cutting or addition of the device structure and the wiring at each cutting position may be considered. In FIG. 16, the cutting for separating the abnormal part of the partial product may be substantially limited to a minimum number of wirings forming a current path, or conversely, for example, a memory array or a memory mat or a memory module to be separated. May be unconditionally cut off the entire uppermost aluminum wiring layer formed around the semiconductor device. 17 to 19
In the above, the logical configuration for setting the redundant word line or the redundant complementary bit line to the selected state is not limited by these embodiments. Further, the number of redundant word lines or redundant complementary bit lines provided in each memory array is also arbitrary. FIG.
In FIGS. 3 to 26, the number of test pads provided in each trimming circuit, that is, the precision and range in which trimming can be performed can be arbitrarily set, and a specific method of trimming can employ various embodiments. In FIG.
The specific method of switching the bit configuration of the dynamic RAM is arbitrary, and the input / output level and the operation mode of the dynamic RAM may be switched by a similar method. In FIG. 28, the wiring correction device can be configured based on a device other than the EB direct drawing device, the FIB device, and the laser repair device.
Does not limit the method of practicing the present invention. The specific circuit configuration of each part shown in each circuit diagram, the conductivity type of MOSFET and the like, the voltage and polarity of each power supply voltage, and the like can take various embodiments.

In the above description, the case where the invention made mainly by the present inventor is applied to a dynamic RAM, which is a field of application as the background, has been described.
The present invention is not limited to this, and can be applied to, for example, various semiconductor storage devices such as a multi-port RAM and a static RAM, and general-purpose or dedicated logic integrated circuits such as a gate array integrated circuit. INDUSTRIAL APPLICABILITY The present invention can be widely applied to a semiconductor integrated circuit device having at least a redundant element or a circuit, or a semiconductor integrated circuit device requiring wiring correction for trimming or the like and effective means.

[0100]

According to the present invention, a functional test of a chip on which a dynamic RAM or the like is formed is performed in a wafer state by a predetermined test device, and the result is used as wiring correction data as an EB direct drawing device, FIB device, or laser repair device. Is transmitted online to the wiring correction device. Then, by directly or indirectly cutting or adding the corresponding wiring on the chip based on these wiring correction data, the defective element or circuit is replaced with a redundant element or circuit, and the defective element or circuit is replaced via the defective element or circuit. The current path formed as a result is cut off. In addition, cutting or adding such wiring,
The present invention is applied to separation of a defective portion when a partial product is configured, and switching of operating characteristics of a predetermined internal circuit or product specifications. Thereby, the defective element or circuit can be switched to the redundant element or circuit without sacrificing the access time of the dynamic RAM or the like and the required layout area is increased, and the defective element or circuit switched to the redundant element or circuit can be easily realized. And a current path formed through these defective elements or circuits can be cut off. Furthermore, an abnormal part such as a dynamic RAM which can constitute a partial product can be easily separated to promote low power consumption, and the operation characteristics of the internal circuit such as the dynamic RAM can be improved without providing a fuse means. Product specifications can be switched. As a result, the chip area, operating current and test man-hours can be reduced without impairing the high-speed performance of a dynamic RAM or the like having a defect rescue function, and cost reduction can be promoted. In addition, the product yield can be significantly increased.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a dynamic RAM to which the present invention is applied.

FIG. 2 is a block diagram showing one embodiment of a memory module included in the dynamic RAM of FIG. 1;

FIG. 3 is a partial circuit diagram showing one embodiment of a memory array included in the memory module of FIG. 2;

FIG. 4 is a partial sectional structural view showing one embodiment of the memory array of FIG. 3;

FIG. 5 is a partial plan view showing an embodiment of the memory array of FIG. 3;

FIG. 6 is a partial circuit diagram showing one embodiment of a sense amplifier included in the memory module of FIG. 2;

FIG. 7 is a partial circuit diagram showing one embodiment of a cutting place for DC defect relief of the dynamic RAM of FIG. 1;

FIG. 8 is an evaluation graph for comparing and evaluating the DC defect remedy method of the dynamic RAM of FIG. 1;

9 is a partial plan view showing an embodiment of a part where a part of the sense amplifier of FIG. 6 is cut.

FIG. 10 is a partial sectional structural view showing one embodiment of a cutting portion in FIG. 9;

FIG. 11 is a partial plan view showing another embodiment of another cutting portion of the sense amplifier of FIG. 6;

FIG. 12 is a partial cross-sectional structural view showing one embodiment of a cutting portion in FIG. 11;

FIG. 13 is a partial plan structural view showing another embodiment of another cutting portion of the sense amplifier of FIG. 6;

FIG. 14 is a partial circuit diagram illustrating another embodiment of the sense amplifier included in the memory module of FIG. 2;

FIG. 15 is a partial circuit diagram showing still another embodiment of the sense amplifier included in the memory module of FIG. 2;

FIG. 16 is a circuit diagram showing one embodiment of a cutting portion for configuring a partial product of the dynamic RAM of FIG. 1;

FIG. 17 is a circuit diagram showing one embodiment of a word line drive circuit of an X address decoder included in the memory module of FIG. 2;

FIG. 18 is a circuit diagram showing one embodiment of a unit X address decoder of the X address decoder included in the memory module of FIG. 2;

FIG. 19 is a partial circuit diagram showing one embodiment of a Y address decoder of the dynamic RAM of FIG. 1;

FIG. 20 is a partial block diagram showing one embodiment in which the present invention is applied to a conventional dynamic RAM employing a redundant switching system based on address comparison and collation.

21 is a partial circuit diagram showing one embodiment of a defective address ROM included in the dynamic RAM of FIG. 20;

FIG. 22 is a partial sectional structural view showing one embodiment of the defective address ROM of FIG. 21;

FIG. 23 is a partial circuit diagram showing one embodiment of a step-down circuit included in the dynamic RAM of FIG. 1;

FIG. 24 is a partial circuit diagram showing one embodiment of a substrate potential generating circuit included in the dynamic RAM of FIG. 1;

FIG. 25 is a circuit diagram showing one embodiment of a delay circuit included in the timing generation circuit of the dynamic RAM of FIG. 1;

FIG. 26 is a circuit diagram showing one embodiment of a signature circuit included in the dynamic RAM of FIG. 1;

FIG. 27 is a partial circuit diagram showing one embodiment of a data input / output circuit included in the dynamic RAM of FIG. 1;

FIG. 28 is a performance comparison diagram showing one embodiment of a wiring correction device used for wiring correction of the dynamic RAM of FIG. 1;

FIG. 29 is a connection diagram showing one embodiment of the wiring correction device and the test device of FIG. 28;

FIG. 30 is a partial processing step diagram showing an embodiment in the case where the wiring correction apparatus of FIG. 28 is configured based on an EB direct drawing apparatus.

FIG. 31 is a partial processing step diagram showing one embodiment in which the wiring correction device of FIG. 28 is configured based on an FIB device or a laser repair device.

[Explanation of symbols]

MOD0-MOD3 ... memory module, MG00
To MG30 and MG01 to MG31: Memory mat group, MAT0 to MAT7: Memory mat, AR
YL, ARYR: memory array, SA: sense amplifier, XDL, XDR: X address decoder, C
SD: sense amplifier drive circuit, MAG0 to MAG3
... Main amplifier group, MA0 to MA3 ... Main amplifier, YD0 to YD3 ... Y address decoder, XA
B: X address buffer, RFC: Refresh address counter, XPD: X predecoder, M
SL: memory mat selection circuit, YAB: Y address buffer, YPD: Y predecoder, IOSL
... Common I / O selection circuit, MOSL ... Memory module selection circuit, DIO ... Data input / output circuit, S
IG: signature circuit, TG: timing generation circuit, VD: step-down circuit, VBBG: substrate potential generation circuit, VCHG: high voltage generation circuit. Qa ...
Address selection MOSFET, Cs: information storage capacitor, Q1-Q8: P-channel MOSFET, Q
11 to Q104: N-channel MOSFET, R1
To R51: resistor, C1 to C5: capacitor, N
1 to N15 ... Inverter circuit, NA1 to NA10
..Nand gate circuits, NO1 to NO4... NOR gate circuits. W0-W255, WL ... word line, WR0
... WR3... Redundant word lines, MWR0 to MWR3.
Main word lines, B 0~ B 1023, B L ··· complementary bit lines, YS0, YSL · · · bit line selection signal lines,
PL: plate electrode, IS: insulating film, SP
・ Information storage electrode, PWELL ... P well area, PS
UB: P-type semiconductor substrate. RS0 to RS5: short-circuit resistance, CP0 to CP108: cutting point. AL1 ...
・ Aluminum wiring layer, SHL, SHR: Shunt signal line, LOCOS: Locos, CSP: Common source line, S, S1 to S2, S13 to S14: Source, D, D1 to D2, D13 ~ D14 ... drain,
G1 to G2 gate. MP: Metal pad, C
E: cutting region, NWELL: N-well region. P
C: precharge control signal line, HVC: precharge level supply line, VC1 to VC2: unit control circuit. WD00 to WD03, WDR0 to WDR3 ... word line drive circuit, UXD0, UXDR ... unit X address decoder, UYD0, UYDR0 to UYDR1, ...
A unit Y address decoder; ROM0-ROM5 ...
Defective address ROM, XAC0-XAC3, YAC0
YAC1... Address comparison circuit. UFC0 to UFC7
... Unit fuse circuits, OA1 to OA3 ... Operational amplifier circuits, VLS ... Reference potential switching circuits, TP1
TP16: test pad, LVC: level detection circuit, OSC: oscillation circuit, CP: charge pump circuit. DL: delay circuit. DIB0-DIB3 ...
Data input buffer, DOB0 to DOB3... Data output buffer. TE: test device, DWE: wiring correction device, TD: wiring correction data, WF: wafer, LSI: chip (large-scale integrated circuit device).

 ──────────────────────────────────────────────────の Continued on front page (72) Inventor Kazuya Ito 2326 Imai, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. (72) Inventor Wataru Arakawa 2326, Imai, Ome-shi, Tokyo Hitachi, Ltd. (72) Inventor Yoshinobu Nakagome 1-280 Higashi Koigakubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd.

Claims (7)

[Claims] 1. A method of manufacturing a semiconductor device, comprising: a predetermined circuit, a plurality of electrode pads connected to the circuit, and a plurality of program wirings including an uppermost wiring layer connected to the circuit. Forming an insulating film on the plurality of program wirings and opening holes on the plurality of electrode pads, and testing a function of the semiconductor device by applying a voltage or a signal to the plurality of electrode pads; Forming a resist film on the surface of the semiconductor device, and irradiating a predetermined portion of the plurality of program wirings determined based on the test with an electron beam to form an opening in the resist film; Cutting a predetermined portion of the plurality of program wirings by using an opening of the resist film. 2. The method according to claim 1, wherein the step of cutting a predetermined portion of the program wiring further includes forming a hole in the insulating film at a predetermined portion of the plurality of program wirings by using an opening of the resist film as a mask. Forming a portion, and cutting a predetermined portion of the plurality of program wirings using the insulating film as a mask. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the step of forming an opening in the insulating film is performed by removing the insulating film by dry etching. 4. The method according to claim 1, wherein the plurality of program wirings are metal wirings. 5. The method according to claim 4, wherein the metal wiring is made of aluminum. 6. The method according to claim 1, wherein the opening of the resist film is formed by irradiating the electron beam with a predetermined portion of the resist film being exposed by the electron beam. After that, the method is performed by developing the semiconductor device. 7. The method for manufacturing a semiconductor device according to claim 1, wherein the cutting of the program wiring is performed by etching.