JP2001084798A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory having a function for easily localizing a fault causing failure of row select line. SOLUTION: A switching circuit 7 is provided between a row decoder 6 and a memory cell array 1 and a decision can be made whether a fault detected through test is present in a row decoder or a memory cell array by switching a word line 3 selected by the row decoder 6. A circuit for dividing each word line in the memory cell array along the row direction of the memory cell array 1 is provided and the fault in the memory cell array 1 can be localized furthermore by dividing the memory cell array 1 into a plurality of blocks. The time required for localizing a fault can be shortened significantly through use of the switching circuit and the dividing circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a test circuit for specifying a range of a defective portion of a row selection line failure.

[0002]

2. Description of the Related Art A configuration of a row selection line of a conventional semiconductor memory device and a problem in a test thereof will be described with reference to FIG. The semiconductor memory device shown in FIG.
, A memory cell 2, a word line (row selection line) 3, a bit line 4, a row decoder 5 for selecting the word line 3 by a row address, and a word driver 6. In addition, the conventional semiconductor memory device includes a column decoder, a control circuit for input / output data, and the like. However, the description is omitted because it is not directly related to the present invention.

A memory cell array 1 is an aggregate of memory cells 2 for storing information. When a specific memory cell 2 is selected, address information of a word line 3 to which each memory cell 2 is connected is input to a row decoder 5. Then, the selection is performed by selecting the word line 3. Input / output of storage information to / from the memory cell is performed by sending a control signal for driving the memory cell 2 via the word driver 6 and the word line 3 or the like.

However, in the test of the semiconductor memory device, even if a row selection line failure occurs, the range including the failure location is included in the row decoder 5 (including the word driver 6).
, Or within the range of the memory cell array 1.

[0005]

As described above, in the conventional semiconductor memory device, even if a row selection line failure occurs during the test, is the range including the failed portion included in the row decoder (including the word driver)? Or it cannot be specified whether it is inside the memory cell array.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and has a function of easily specifying a range including a faulty portion which is a cause of a row selection line defect detected during a test. It is an object to provide a semiconductor memory device.

[0007]

SUMMARY OF THE INVENTION A semiconductor memory device according to the present invention is provided between a row decoder and a memory cell array in order to specify a range including a faulty portion which causes a row selection line defect detected at the time of the test. Is provided with a switching circuit, and by switching the word line selected by the row decoder, it is possible to specify whether the range including the fault location is the row decoder or the inside of the memory cell array.

Further, a dividing circuit for dividing each word line of the memory cell array along the column direction of the memory cell array is provided, and the memory cell array is divided into a plurality of memory blocks along the column direction. It is characterized in that the range of the fault location included in the inside is further narrowed down.

More specifically, a semiconductor memory device according to the present invention comprises a memory cell array arranged in a matrix along a row direction and a column direction, and a row selection line arranged on the memory cell array along the row direction. A semiconductor memory device having a row decoder for selecting a row selection line of a predetermined row address from the row selection line; a circuit for switching the row selection line disposed between the memory cell array and the row decoder; A circuit for dividing a row selection line disposed in the memory cell array along a column direction of the memory cell array;

Preferably, the row selection line switching circuit switches the row selection line selected by the row decoder to any one of other selection lines different from each other.

Preferably, the row selection line switching circuit includes a row selection line selected by the row decoder, except when the row selection line has the highest row address of the memory cell array. And if the row selection line selected by the row decoder has the highest row address of the memory cell array, the highest row selection line is changed to the lowest row. It is characterized by switching to a row selection line of an address.

Preferably, the switching circuit for switching the row selection line includes a row selection line selected by the row decoder, except when the row selection line has the lowest row address of the memory cell array. Is switched to the row selection line of the row address, and if the row selection line selected by the row decoder has the lowest row address of the memory cell array, the lowest row selection line is changed to the highest row. It is characterized by switching to a row selection line of an address.

Preferably, the division circuit for the row selection line is arranged along a column direction of the memory cell array,
The row selection lines are divided along the column direction of the memory cell array.

Conventionally, a defective row selection line has a wide range including a failed portion, and it has taken a long time to perform a failure analysis for narrowing down the failed portion. By using the method, the time required for specifying the failure location can be greatly reduced, and the failure factor can be analyzed with a high probability.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings. The first embodiment of the present invention will be described with reference to FIG.
An embodiment will be described. In the first embodiment, a configuration example of the row selection line of the present invention and its characteristics will be described.

The semiconductor memory device shown in FIG. 1 has a memory cell array 1a, 1b, a memory cell 2, a word line 3,
A bit line 4, a row decoder 5, a word driver 6,
A switching circuit 7 including transistors QA1 to QA9 and QB1 to QB9, a dividing circuit 8a including transistors QC1 to QC9, and a dividing circuit 8b including transistors QD1 to QD9.
Consists of

The features of the semiconductor memory device shown in FIG. 1 are as follows.

(1) Row decoder 5 (including word driver 6, the same applies hereinafter) and memory cell array 1 (1a in FIG. 1)
And a switching circuit 7 including transistors QA1 to QA9 and QB1 to QB9.

(2) The memory cell array 1a and the memory cell array 1b are divided by a dividing circuit 8a including transistors QC1 to QC9.

(3) A transistor Q is connected between the Vss common line (normally grounded) and the terminating ends of the word lines WL1 to WL9.
A dividing circuit 8b consisting of D1 to QD9 is arranged.

Here, transistors QA1 to QA9 and QB1
When a row selection line defect occurs when the row decoder 5 selects a word line 3 based on a row address, the switching circuit 7 including the switching circuit 7 switches the word line to another adjacent word line. Switching is performed, and similarly, a test is performed to determine whether or not a row selection line failure occurs.

Since there is a low probability that a defective portion causing a row selection line defect is similarly included in an adjacent word line, if a row selection line defect similarly occurs even when the word lines are switched, the row selection line defect is determined. It can be determined that the failure location causing the failure is included in the row decoder 5.

The dividing circuit 8a including the transistors QC1 to QC9 is connected to the selected word line 3 in which the row selection line defect has occurred.
Is divided into two by using the dividing circuit 8a, and if the row selection line defect disappears, it can be understood that the failure site causing the row selection line defect is on the side of the memory cell array 1b of the selected word line. Thus, the memory cell array 1
It becomes possible to narrow down the range of the failure point in a and 1b.

The dividing circuit 8b composed of the transistors QD1 to QD9 prohibits writing and reading by applying a voltage of the Vss common line to each word line of the unselected memory cell array, and This is a division circuit for disconnecting each word line from the Vss common line so as to enable writing and reading.

As described above, the switching circuit 7 of the first embodiment has a function of switching a selected word line in which a row selection line failure has occurred to an adjacent word line. However, the switching circuit 7 does not necessarily switch to an adjacent word line. No need. A similar purpose can be achieved by switching to one of the other different word lines. In this way, even if, for example, the cause of the row selection line defect is a short circuit between adjacent word lines, it can be correctly determined as a failure on the memory cell array side.

Changing the transistor circuit of the switching circuit 7 so as to switch to one of the other different word lines can be easily analogized from the configuration of the switching circuit 7 shown in FIG.

Next, a second embodiment of the present invention will be described. In the second embodiment, a normal operation of the semiconductor memory device of the present invention will be described. In the normal operation of the semiconductor memory device of the present invention shown in FIG.
The transistors constituting the dividing circuits 8a and 8b operate as follows.

(A) In the switching circuit 7, the signal A of the switching circuit 7 is set to "H" (high level) in order to directly connect the output terminal of the word driver to each word line of the corresponding memory cell array. QA1 to QA9 are turned on. The signal B of the switching circuit 7 is set to "L" (low level) to turn off the transistors QB1 to QB9, excluding the word line switching function of the switching circuit 7.

(B) In the division circuit 8a, the corresponding word lines of the memory cell arrays 1a and 1b are directly connected to each other to form an integrated memory cell array.
The signal C of "a" is set to "H" to turn on the transistors QC1 to QC9.

(C) Integrated memory cell array 1
In order to set a and b to a selected state in which writing and reading can be performed, the signal D of the dividing circuit 8b is set to "L" to disconnect the memory cell arrays 1a and 1b from the Vss common line.

In this manner, the semiconductor device of the present invention shown in FIG. 1 having the switching circuit 7 and the dividing circuits 8a and 8b can be operated in the same manner as the conventional semiconductor memory device shown in FIG.

Next, a third embodiment of the present invention will be described. In the third embodiment, a description will be given of a specific operation of the semiconductor memory device of the present invention for identifying a failure location of a row selection line failure.

First, a case will be described in which it is specified whether a range including a fault location is a row decoder (including a word driver) or an inside of a memory cell array.

The transistors constituting the switching circuit 7 and the dividing circuits 8a and 8b shown in FIG. 1 are set to the normal operation state described in the second embodiment, and the semiconductor memory device is tested. The word line WLi corresponding to the i-th row address from the lowest (i = 1 to 1 in FIG. 1)
Suppose that a row selection line defect occurs in 8).

At this time, while the "H" of the signal C and the "L" of the signal D of the dividing circuit described in (b) and (c) above are maintained, the signal A of the switching circuit 7 is changed to "L". , B are switched to "H" and the transistors QA1 to QA9 are turned off and the transistors QB1 to QB9 are turned on, the selected word line WLi corresponding to the i-th row address becomes the adjacent higher address WLi + 1. Is switched to.

When the selected word line WLi corresponds to the highest row address (when i = 9 in FIG. 1), the selected word line corresponds to the lowest row address from WL9 by the switching operation. Is switched to WL1.

After performing such a switching operation, a test is performed again, and the word line WL corresponding to the i-th row address is
If the row selection line failure of i (i = 1 to 9 in FIG. 1) disappears, it is determined that the failure location is within the range of the memory cell arrays 1a and 1b. After performing such a switching operation, a test is performed again. If the row selection line defect is maintained, it is determined that the failed portion is within the range of the row decoder (including the word driver).

In the switching circuit 7 shown in FIG. 1, the case where the selected word line is switched to the adjacent upper address side has been described, but it is needless to say that the selected word line can be similarly switched to the adjacent lower address side. Nor.

Next, a description will be given of a means for further specifying which area of the memory cell array contains a fault when it is determined that the range including the fault location is the memory cell array.

The transistors constituting the switching circuit 7 and the dividing circuits 8a and 8b shown in FIG. 1 are set to the normal operation state described in the second embodiment, and the semiconductor memory device is tested. It is assumed that a selection line defect has occurred.

At this time, while the "H" of the signal A and the "L" of the signal B of the switching circuit previously described in (a) are maintained, the signal C of the dividing circuit 8a is set to "L", A dividing operation for separating the cell array 1b is performed. Also, the signal D of the dividing circuit 8b is set to "H", and the separated memory cell array 1b is connected to the Vss common line, and this is set as a non-selected block.

After performing such a division operation, a test is performed again, and if the row selection line defect disappears, it is determined that the failed portion is within the range of the memory cell array 1b. Also,
After performing such a division operation, a test is performed again, and if the row selection line defect is maintained, it is determined that the failed portion is within the range of the memory cell array 1a.

The present invention is not limited to the above embodiment. For example, in the first to third embodiments, the case where the dividing circuit 8a divides the memory cell array into two in the column direction has been described, but it is not always necessary to divide the memory cell array into two. The memory cell array is arranged along the column direction by n
By dividing (n is a natural number of 2 or more),
It is possible to narrow down the range of the failure location of the row selection failure in the memory cell array.

In the first and third embodiments, the switching circuit for switching the selected word line to the adjacent upper or lower word line except for the word line corresponding to the uppermost or lowermost row address. However, it is not always necessary to switch to an adjacent word line. As described in the first embodiment, the same purpose can be achieved by switching to any one of the other different word lines.

If, for example, the switching circuit is arranged between a row decoder and a word driver, a failure in the word driver can be specified. In addition, various modifications can be made without departing from the spirit of the present invention.

[0046]

As described above, according to the semiconductor memory device of the present invention, the switching circuit is provided between the row decoder and the memory cell array, and the switching operation of the word line selected by the row decoder is performed. It is possible to specify whether the range of the faulty portion of the row selection line defect detected in the above is the row decoder or the inside of the memory cell array.

Further, a dividing circuit for dividing each word line of the memory cell array along the column direction of the memory cell array is provided, and a dividing operation for dividing the memory cell array into a plurality of blocks is performed so that the memory cell array is divided into a plurality of blocks. It is possible to further narrow down the range of the failure location to be performed.

Conventionally, analysis of a row selection line defect has taken a long time to narrow down because the configuration area of a semiconductor memory device for which a failure location is to be specified is wide. The use of the semiconductor memory device provided with the dividing circuit can significantly reduce the time required for specifying the failure location, and can determine the cause of the failure with a high probability.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a row selection line of a semiconductor memory device according to first to third embodiments of the present invention.

FIG. 2 is a diagram showing a configuration of a row selection line in a conventional semiconductor memory device.

[Explanation of symbols]

 1, 1a, 1b memory cell array 2 memory cell 3 word line 4 bit line 5 row decoder 6 word driver 7 switching circuit 8a, 8b dividing circuit

Claims (5)

[Claims] 1. A memory cell array arranged in a matrix along a row direction and a column direction, a row selection line arranged in the memory cell array along the row direction, and a predetermined row address from the row selection line. A row decoder for selecting a row selection line of the following: a switching circuit for switching the row selection line disposed between the memory cell array and the row decoder; A semiconductor memory device, comprising: a circuit for dividing a row select line disposed in the memory cell array; 2. The semiconductor device according to claim 1, wherein the row selection line switching circuit switches the row selection line selected by the row decoder to one of other different selection lines. Storage device. 3. The row selection line switching circuit according to claim 1, wherein the row selection line selected by the row decoder has an uppermost row address in the memory cell array unless the row selection line has an uppermost row address. If the row selection line is switched to the row selection line of the address and the row selection line selected by the row decoder has the highest row address of the memory cell array, the highest row selection line is set to the lowest row address. 2. The semiconductor memory device according to claim 1, wherein switching to a row selection line is performed. 4. The row selection line switching circuit, wherein the row selection line selected by the row decoder has a lower row address of the memory cell array unless the row selection line has the lowest row address. If the row selection line is switched to the row selection line of the address and the row selection line selected by the row decoder has the lowest row address of the memory cell array, the lowest row selection line is changed to the highest row address. 2. The semiconductor memory device according to claim 1, wherein switching to a row selection line is performed. 5. The row selection line dividing circuit is arranged along a column direction of the memory cell array, and divides the row selection line along a column direction of the memory cell array. 5. The semiconductor memory device according to any one of 1 to 4.