JP2001078190A - Image processor and its control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an image processor that can conduct orthogonal transform for multi-dimension with a simple configuration and its control method. SOLUTION: A linear DCT processor apples linear orthogonal transform to image data received from a buffer memory 101 in the unit of blocks via a changeover switch 102 in an initial state and a memory 104 store the resulting data. Then the data stored in the memory 104 and receiving transposition conversion are read and fed back to the switch 102 via a changeover switch 105, the linear DCT processor apples transform processing in a direction orthogonal to that of the preceding transform to the feedback date and the processed data are outputted externally via the memory 104 and the changeover switch 105.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus and a control method thereof, and more particularly to an image processing apparatus for performing an orthogonal transformation process in image compression coding and a control method thereof.

[0002]

2. Description of the Related Art An image data compression / encoding apparatus performs coordinate transformation of image data from a spatial domain to a frequency spatial domain using orthogonal transform means, and reduces the amount of information by a quantizing means in the frequency domain. Data compression is being performed.

The orthogonal transform means is a discrete cosine transform (commonly called D
CT) is the mainstream, and an outline of a hardware configuration of a two-dimensional DCT that handles an image is as shown in FIG. Was.

In FIG. 4, reference numeral 401 denotes a buffer memory for reading image data mainly in units of blocks of an arbitrary size; 402 and 404: a one-dimensional DCT processing device;
03 is a memory for reading out image data in block units mainly in the transposed order, 405 is a quantization processing device, and 406 is a memory for reading out image data in block units after quantization in zigzag scan order. is there.

A method of performing two-dimensional DCT processing on image data in such a configuration will be described.

[0006] The input image data is temporarily stored in a buffer memory 401 and then read out in a raster scan order in units of blocks of a predetermined size (for example, 8 × 8 pixels).

[0007] The block image data read from the buffer 401 is input to a one-dimensional DCT processing device 402 and orthogonally transformed in a horizontal direction (or a vertical direction).

The one-dimensional DCT-processed image data is temporarily stored in a memory 403, read out in a transposition order (inversion of rows and columns) in a matrix, and input to a one-dimensional DCT processing unit 404. , Vertical (or horizontal)
Is orthogonally transformed into two-dimensional (horizontal and vertical) D
The CT processing is completed.

[0009] The image data (DCT coefficients) coordinate-transformed from the two-dimensional space domain to the two-dimensional frequency domain in this way is input to the quantization device 405, and the quantized data in which the frequency is arbitrarily weighted is given. Quantization (compression) processing is performed by the quantization table.

[0010] The quantized DCT coefficients are stored in a memory 406.
After the temporary storage, the zigzag
The data is read out in the order of scanning or the like, transmitted through an encoding process such as variable-length encoding, or recorded on various media.

On the other hand, when the encoding apparatus supports inter-frame (or field) encoding, as shown in FIG. 4, the quantized DCT coefficients are transmitted not only to the memory 403 but also to the local decoder. Is also input and after local decoding processing,
It is configured to be stored as prediction reference data and used for motion vector search (motion compensation) and the like.

Therefore, DCT processing units 402 and 40 apply to image (pixel) data input at a constant rate.
4 and the quantization device 405 are independent of each other, and as described above, since the processing from the two-dimensional DCT to the quantization is a flow operation (open loop), the image necessary for the two-dimensional DCT processing is There is a restriction that storage means for transposition (order change) of data and storage means for rearranging DCT coefficients in an order suitable for encoding must be provided independently, and in recent years, the processing speed of hardware has been improved. The problem is shifting to circuit design, that is, power consumption, rather than processing capability.

However, in the configuration of FIG. 4, two memories 406 for transposition (memory 403 in FIG. 4) and zigzag scanning are indispensable in terms of hardware configuration, which is an obstacle to a demand for reducing the circuit scale. Was.

In addition, in the conventional hardware configuration, the processing capability of the processing side can often have a margin with respect to the input image data rate, and the memory in the encoder (403 and 406 in FIG. 4). And a DCT processor (402,
Since it is inevitable that the operation rate of 404) decreases, hardware over-specification has been a problem, such as operation at an operation clock lower than the hardware performance.

The present invention has been made in view of such a problem, and an object of the present invention is to provide an image processing apparatus capable of performing a multidimensional orthogonal transformation with a simple configuration and a control method thereof.

[0016]

To solve this problem, for example, an image processing apparatus according to the present invention has the following arrangement. That is, input means for inputting image data in block units, conversion means for performing one-dimensional orthogonal transformation on image data in block units, memory for storing the block data converted by the conversion means, and supply to the conversion means A first input unit that selects one of a block input from the input unit or a block transposed and read from the memory, and supplying the block from the memory to the first selection unit. Alternatively, there is provided a second selecting means for selecting either one of output to the outside and a control means for controlling selection of the first and second selecting means.

[0017]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings.

FIG. 1 shows a block diagram of the apparatus according to the embodiment.

In FIG. 1, reference numeral 101 denotes a buffer memory (for block division), and reference numeral 102 denotes a two-input / one-output switch. 103 is a one-dimensional DCT processing device, 104 is a temporary storage device (memory), 105 is a one-input / two-output switch, and 106 is a memory.
This is a control device that controls the switch. The control of reading and writing of the memories (101, 104) by the controller 106 is performed by raster scan (in units of lines).
Is the default.

Here, a general expression of the two-dimensional DCT operation is shown.

Z = ADA ^T (1) Z ^T = ((AD) · AT) ^T = A · (AD) ^T (2) X = (AD) ^T (3) A: DCT transformation matrix A ^T : The above matrix Transposition of A D: Image data (block) Z: Image data after two-dimensional DCT processing (DCT coefficient block) The input image data is temporarily stored in the buffer memory 101. The image data stored in the buffer memory 101 is read out in the order of raster scan in units of blocks of a predetermined size, which is a unit of encoding, under the control of the control device 106, and is input to the changeover switch 102.

The changeover switch 102 is connected to the control device 10
Under the control of No. 6, there is an ability to select an input to the one-dimensional DCT processing device 103 at the next stage.

It is assumed that the initial state of the changeover switches 102 and 105 is the terminal (1) in FIG. Buffer memory 1
The image data in block units read from block 01 is sent to the one-dimensional D through the unit (1) of the changeover switch 102.
The data is input to the CT processing device 103 and subjected to one-dimensional DCT processing.

On the other hand, when the control device 106 completes the transmission of the image data for one block to the changeover switch 102, it stops reading from the memory 101 and shifts the terminal (1) of the changeover switch 102 to the (2) side. Switch.

As a result, the data subjected to the one-dimensional DCT processing is temporarily stored in the memory 104, and then the control device 106
Is read out in the transposition order (row and column are inverted and raster scan order) by the control device of
05 again via the terminal (1)
2 terminal (2).

The controller 160 sets the terminal of the changeover switch 105 to (1) when reading of one block of data after the one-dimensional DCT processing from the memory 104 is completed.
(2) (see FIG. 5).

In the above processing, the calculation of X = (AD) ^T shown in the above equation (3) is completed.

As described above, the changeover switch 10
Since 2 has been switched to the terminal (2) side at this point,
The block subjected to the one-dimensional DCT processing and read out in the transposition order is input again to the one-dimensional DCT processing device 103 via the two switches (105, 102), and subjected to the second DCT processing as described above. You.

The block after the second one-dimensional DCT processing corresponds to Z ^T = A · (AD) ^T in the above equation (2).

The block subjected to the second one-dimensional DCT processing is again stored in the memory 1 under the control of the controller 106.
After being temporarily stored in the switch 04, it is read out in the order of transposition and output as a two-dimensional DCT coefficient block (DCT coefficient) via the switch terminal (2) side of the changeover switch 105 (formula (1)). Is completed).

According to the present invention, when the DCT coefficients after the second one-dimensional DCT processing are read out from the memory 104 in which the DCT coefficients are temporarily stored, an arbitrary order such as zigzag scanning is set and read out together with transposition as necessary. It is possible to program the controller 106 to do so.

<Second Embodiment> FIGS. 2 and 3 show a second embodiment according to the present invention.

In FIG. 2, reference numerals 201 and 205 denote buffer memories (for block division), 202 denotes a two-input / one-output selector switch, 203 denotes a one-dimensional DCT processor,
4 is a quantizer, 206 is a transposition memory, 207 is a one-input / two-output switch, and 208 is a control device that controls each memory and switch.

With respect to the general formula of the two-dimensional DCT, the formulas (1) to (3) described in the first embodiment are similarly referred to in the second embodiment.

The changeover switches 202, 205, 2
07 are assumed to be terminals (1) (FIG. 2)
reference).

In the above configuration, the input image data is temporarily stored in the buffer memory 201.
The image data stored in the memory 201 is read out in the order of raster scan in units of blocks of a predetermined size, which is a unit of encoding, under the control of the control device 208, and is supplied to the changeover switch 202.

The changeover switch 202 is connected to the control device 20
8 has a function of selecting an input to the one-dimensional DCT processing device 203 at the next stage.

Up to this point, it is completely the same as the first embodiment described above.

The image block read from the buffer memory 201 is input to the one-dimensional DCT processing device 203 via the terminal (1) of the switch terminal 202, and subjected to one-dimensional DCT processing.

On the other hand, the controller 208 stops reading the data from the buffer memory 201 when the transmission of one block of image data to the switch 202 is completed, and switches the switch 202 from the terminal (1) to the terminal (2). Output a control signal for

At this point, since the switch 205 is set to the terminal (1) side as described above, the one-dimensional DCT
The block subjected to the one-dimensional DCT processing by the processing device 203 is stored in the memory 206 via the terminal (1) of the switch 205, bypassing the quantizer 204.

The one-dimensional DCT-processed blocks stored in the memory 206 are read out in the order of transposition under the control of the control device 208, and are returned to the terminal (2) of the switch 202 via the terminal (1) of the switch 207. Supplied.

Further, when the controller 208 detects the completion of reading all the data of the one-dimensional DCT-processed block from the memory 206, it switches the switches 205 and 207 from the terminals (1) to (2) in the initial state. A control signal is output so as to switch between them.

In the processing so far, the calculation of X = (AD) ^T shown in the equation (3) is completed as in the first embodiment.

As described above, at this point the switch 202
Has been switched from the terminal (1) in the initial state to the terminal (2) under the control of the control device 208, the one-dimensional DCT-processed block supplied via the switch 207 is again supplied via the terminal (2) of the switch 202. The data is input to the one-dimensional DCT processing device 203 and subjected to one-dimensional DCT processing again.

For the block that has been subjected to the second one-dimensional DCT process, the calculation shown in the equation (2) of the first embodiment is completed.

Therefore, at this point, the desired two-dimensional D
Transformed CT processing result (two-dimensional DCT coefficient) (Z
^T = ((AD) ・ A ^T ) ^T = A ・ (AD) ^T ). As described above, since the switch 205 has been switched to the terminal (2) side at this time, the two-dimensional DCT coefficient (transposition) is input to the quantizer 204, and a predetermined weighted quantization is performed for each frequency. Quantization (compression) in table
After being processed, it is stored in the memory 206 again via the terminal (2) of the switch 205. Here, the DCT coefficient input to the quantizer 204 is output from the one-dimensional DCT processor 203 in a transposed state, that is, the horizontal and vertical components are inverted as described above. The layout of the table also corresponds to it.

The two-dimensional DCT coefficients quantized (compressed) by the quantizer 204 are input to the memory 206 again, and then read out in the order of transposition and zigzag scanning under the control of the control unit 208. Then, it is configured to be output as a two-dimensional DCT-processed coefficient block via the terminal (2) of the switch 207 (see FIG. 6).

Next, the temporal operation of the one-dimensional processor 203 and the memory 206 in FIG. 2 will be described (see FIGS. 2 and 3).

Assume that time t ₀ shown in FIG. 3 is the start time of the one-dimensional DCT processing of a certain block.

The one-dimensional DCT process started at the time t ₀ completes the one-dimensional DCT process for one block at the time t ₁ (reference numeral 31 in FIG. 3).

On the other hand, for a certain block, the time t ₀
In the one-dimensional DCT processing started in step (1), the pixel data of the block to be subjected to the DCT processing is sequentially written to the memory as soon as the DCT processing ends, but at time t ₀ + Δt in FIG. Is the write start time of the data after the DCT processing is completed (reference numeral 32 in FIG. 3).

That is, from time t ₀ to t ₁ , the block is subjected to one-dimensional DCT processing, and from time t ₀ + Δt to t ₁ + Δt, all data of the block subjected to the one-dimensional DCT processing is obtained. The data is written to the memory 206 (reference numeral 32 in FIG. 3).

As described above, at time t ₁ + Δt, one-dimensional DC
One block data is written in T the treated simultaneously and end, and starts reading a one-dimensional DCT processing data written in the memory at transposed order (reference numeral 33 in FIG. 3), from the time t ₂ The second one-dimensional DCT processing is started (reference numeral 34 in FIG. 3).

In the same manner as described above, the second one-dimensional DCT
The data that has been processed is sequentially written into the memory (reference numeral 35 in FIG. 3).
Is a time represented by _tv in FIG. 3, and the memory alternately performs both read and write operations by time sharing (see FIG. 7).

That is, at time t _v during the period between states 33 and 35 in FIG. Under the control of the control device 208 in FIG. 2, the memory is set to the read mode, and the one-dimensional DCT
Data is read from the memory in units of processing of the processing device (period I in FIG. 7). II. Next, the control device 208 starts a one-dimensional DCT process on the read data (period II in FIG. 7). III. When the DCT of the first processing unit is completed in the DCT processing of II, the control unit 208 changes the memory to the write mode, and performs the DCT-processed data (part of a block) for each processing unit.
Is written into the memory 206.

The second embodiment (FIG. 2) is configured so that I to III are repeated for each block.

As a result, the block read from time t ₁ + Δt to t _2r is subjected to the second one-dimensional DCT processing from time t ₂ to t ₀ , and from time t ₂ + Δt t ₃ + Δt
All the data of the block that has completed the second one-dimensional DCT process is written into the memory 206 again (FIG. 3).
35).

Hereinafter, reference numerals 37 to 41 in FIG. 3 are repetitions of the reference numerals 31 to 35 in FIG. 3 described above, and a compression / encoder including multidimensional DCT processing is realized by the hardware configuration described above. Things.

The encoding device described in the above embodiment may be incorporated in a device such as a digital camera, or may be incorporated in other devices. Also,
The present invention may be applied to a system including a plurality of devices (for example, a host computer, an interface device, a reader, and a printer).

[0061]

As described above, according to the present invention, a multidimensional DCT processing apparatus can be realized with a simple configuration. Since the memory required for the transposition and the zigzag scan can be shared, the total hardware amount can be reduced and the power consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an initial state of an apparatus according to a first embodiment and a block configuration diagram thereof.

FIG. 2 is an initial state of a device according to a second embodiment and its block configuration diagram.

FIG. 3 is a diagram showing a timing chart relating to DCT processing in a second embodiment.

FIG. 4 is a functional block diagram of a conventional encoder.

FIG. 5 is a diagram showing a second state of the switches 102 and 105 in FIG.

FIG. 6 shows switches 202, 205, 20 in FIG.
FIG. 7 is a diagram showing a second state of FIG.

FIG. 7 is a diagram showing an R / W timing chart of a memory 206 in FIG. 2;

Claims (5)

[Claims] An input unit for inputting image data in block units; a conversion unit for performing one-dimensional orthogonal transformation on the image data in block units; a memory for storing the block data converted by the conversion unit; First selecting means for selecting either a block input from the input means or a block transposed and read from the memory, and a block supplied from the memory to the first selecting means. An image processing apparatus, comprising: a second selection unit that selects one of the first and second output units; and a control unit that controls selection of the first and second selection units. 2. The control unit selects the input unit as an input target of the first selection unit in a first stage, and selects a block supplied from the second selection unit in a next stage. The image processing apparatus according to claim 1, wherein: 3. An input unit for inputting image data in block units, a conversion unit for performing one-dimensional orthogonal transformation on the image data in block units, a memory for storing the block data converted by the conversion unit, First selecting means for selecting either a block input from the input means or a block transposed and read from the memory, and a block supplied from the memory to the first selecting means. And a second selecting means for selecting either of the first and second selecting means, the first and second selecting means according to a predetermined timing. A control method for an image processing apparatus, comprising a control step of switching an object. 4. An input unit for inputting image data in block units, a conversion unit for performing one-dimensional orthogonal transform on the image data in block units, and a quantization unit for quantizing the block data converted by the conversion unit. A memory for storing a block converted or quantized by the conversion unit; and a block supplied to the conversion unit, the block input from the input unit, or the block transposed and read from the memory. A first selection unit for selecting either one of the blocks to be supplied to the memory; and a second selection unit for selecting either a block converted by the conversion unit or a block quantized by the quantization unit. And third selecting means for selecting either to supply from the memory to the first selecting means or to output to the outside. An image processing apparatus comprising: a control unit that controls selection of the first to third selection units. 5. An input unit for inputting image data in block units, a conversion unit for performing one-dimensional orthogonal transformation on image data in block units, and a quantization unit for quantizing the block data converted by the conversion unit. A memory for storing a block converted or quantized by the conversion unit; and a block supplied to the conversion unit, the block input from the input unit, or the block transposed and read from the memory. A first selection unit for selecting either one of the blocks to be supplied to the memory; and a second selection unit for selecting either a block converted by the conversion unit or a block quantized by the quantization unit. And third selecting means for selecting either to supply from the memory to the first selecting means or to output to the outside. An image processing apparatus comprising: a control step of controlling selection of the first to third selection units in accordance with a predetermined timing.