JP2001077725A - Correlator, matched filter, and terminal device using the matched filter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the processing speed of signals without causing any large increase in power consumption, to improve the signal processing quantity and information transmission amount, and to process signals of multiple series by the same circuit in a correlator and a matched filter. SOLUTION: This correlator 1 is equipped with a signal delay block 2 which delays pieces of analog signal input data different in signal input time behind their input time and outputs them, a correlator unit 3 in which four stages of correlation cumulative quantizers 6 for finding cross-correlation between the analog signal input data from the signal delay block 2 and codes are connected in a pipeline shape, a code generation block 4 which outputs the code to the respective correlation cumulative quantizers 6, and an output process block 5 which integrates partial correlation values outputted from the correlation cumulative quantizer 6 in the 4th stage as the final stage of the correlator unit 3 and finds one correlation value from the integrated value.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a correlator and a matched filter for inputting continuous analog input signal data in time series, multiplying the time series data by a code, and using the matched filter. It relates to a terminal device. The matched filter is suitably implemented as a matched filter of a receiving unit in a terminal device (wireless communication device) using a spread spectrum method.

[0002]

2. Description of the Related Art A so-called direct spread spectrum communication system in which an information signal is multiplied by a wide band spreading code and transmitted to return to a narrow band signal by despreading at the time of reception, has a superior fading characteristic and a greater number of subscribers. Research has been actively conducted for practical use as a new system of a mobile communication system, having excellent characteristics such as accommodating persons.

In the above-mentioned direct spread spectrum communication system,
In order to demodulate a signal in a receiver, a signal processing process called synchronization acquisition for synchronizing with a spreading code is required. The process called synchronization acquisition means that the received signal is despread in the receiver, and the despread code used for demodulation is synchronized with the spread code included in the received signal.

As the despreading means, a method using a filter called a matched filter and a method using a so-called sliding correlator are known. In the method using a sliding correlator, generally,
Although the circuit is simple, it has an essential problem relating to the reception performance of the receiver such that the time required for synchronization acquisition is long, and a matched filter is generally used.

As such a matched filter, a conventional Y filter is used.
FIG. 16 shows a configuration example of a tap matched filter. In FIG. 16, dm and rm represent a spread spectrum reception signal and a correlation signal at time point m, respectively, and pn represents a spread code having a period Y (n = 0, 1, 2,..., Y-1). Assuming that the section length (chip section length) of the spreading code pn is Tc, the received signal dm is temporally sampled at a period equal to the chip section length Tc. In the spreading code pn, between pn and pn + 1, pn + 1 indicates the past code. For other signals, for example, dm and dm + 1 for the received signal dm, dm
Indicates a past signal.

Assuming that the section length (symbol section length) of data to be spread on the transmission side is Ts, the spreading ratio Z is Z = Ts between the chip section length Tc and the symbol section length Ts.
/ Tc. As shown in FIG. 16, in a normal matched filter, the number of taps Y is equal to the diffusion ratio Z. Less than,
In order to simplify the description of the operation, the received signal dm is a signal in a baseband.

The delay circuit d includes Y-1 delay elements di.
(I = 1, 2,..., Y-1) are connected in cascade, and the reception signal dm is input to the delay element d1. The delay time in each delay element di is equal to the chip section length Tc. Then, the output dm-i of each delay element di
And the input signal dm are multiplied by a spreading code pn by a multiplying circuit mn, and all outputs of the multiplying circuit are mutually added by an adding circuit k. This gives the spreading code p
The correlation signal rm for the period Ts of one cycle of n is obtained.

A general spreading code pn is “+1” or “−”.
1 ”, the ordinary multiplication circuit mn is
The polarity of the input to the addition circuit k is inverted according to the spreading code pn, and the output dm-i of each of the delay elements di and the input signal dm are output. As understood from the configuration in FIG. 16, inside the matched filter, the spread code pn is fixed, and the cross-correlation function with the received signal dm that is shifted for each chip section length Tc is calculated. When the phase of the received signal dm coincides with the phase of the spreading code pn, the absolute value of the correlation signal rm becomes the maximum value. Due to the periodicity of the received signal dm and the spreading code pn, a point in time at which this phase coincides comes every Ts of the symbol section length, and that point in time becomes a synchronization phase, which is used for synchronization acquisition and synchronization tracking. As described above, the despreading using the matched filter can always be performed in the period Ts of one period of the spreading code pn.
There is no need to perform an operation to match the phase with the above.

As a matched filter of another spread spectrum receiver, for example, Japanese Patent Application Laid-Open No. 9-83486 discloses a method in which a weighted addition using an PN code is performed on an analog input signal, and the addition result is output as an analog output signal. The product-sum operation unit is provided, the analog output of the product-sum operation unit is intermittently held, the peak of the held analog signal is detected, and the timing of the detected peak value is determined.
A technique is disclosed in which an analog / digital converter digitizes a peak value of an analog signal only at the timing of the peak value.

With such a configuration, the operation speed of the analog / digital converter can be minimized, and as a result, power consumption is reduced.

Further, as another filter circuit, for example, IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol.
0, No.12, 1995, P1350-1356 “A 20-Msample / s Swit
ched-Capacitor Finite-Impulse-Response Filter Usin
ga Transposed Structure. "contains a switched capacitor
A technique is disclosed in which an FIR filter using a circuit is configured, a multiplication of an input signal and a code is performed, a 4-stage analog addition of a partial correlation value is performed by a pipeline method, and a correlation value is output.

According to the technique disclosed in the above-mentioned paper, a correlation value in the case of a short tap number can be analog-calculated with low power consumption.

Further, as another matched filter, Japanese Patent No. 2773075 discloses a technique of a matched filter which outputs a correlation value by using a CCD which is a charge transfer element as an analog shift register. With this configuration, the correlation value in the case of a short number of taps can be analog-calculated with low power consumption.

[0014]

The matched filter is
The feature is that the synchronization acquisition time is short. However,
There is a problem that the circuit scale becomes large. That is,
When the configuration of FIG. 16 is realized by a digital circuit, the addition circuit k
However, there is a problem that the circuit scale becomes large. This is because a digital multi-input addition circuit can be realized only by a combination of two-input addition circuits. When the number of taps is Y, at least Y-1 two-input addition circuits are required. That's why. Further, as the chip section length Tc becomes shorter, higher speed operation is required, so that there is a problem that current consumption increases.

In order to solve these problems, attention has been paid to an analog matched filter using an inverting amplifier circuit as described in Japanese Patent Application Laid-Open No. 9-83486.

However, Japanese Patent Application Laid-Open No. Hei 9-83486 describes the above.
In the configuration described in Japanese Patent Application Laid-Open Publication No. H10-209, the power consumption in the baseband processing unit can be reduced by suppressing the operation speed of the analog / digital converter, but a circuit for detecting the peak of the analog signal becomes complicated. As described above, since the peak value detected by the analog output signal is converted from analog to digital, there is a problem that the peak value detection accuracy is low despite the complicated peak detection. Therefore, there is a problem that an analog spread spectrum received signal cannot be demodulated with high accuracy.

Further, in the configuration disclosed in the above-mentioned paper,
Since this is an example of a small number of taps of four stages, a large dynamic range is not required for the analog adder, but in order to use it as a matched filter, it is necessary to add 256 to 512 partial correlation values. In such a multi-stage configuration, the further the partial correlation value is accumulated on the subsequent stage, in order to not saturate the accumulated partial correlation value,
Analog adders require a large dynamic range. For this reason, there is a problem that the power consumption in the adder increases, and the power consumption cannot be reduced by lowering the power supply voltage. In addition, in order to simplify the processing of the correlation output in a subsequent circuit, an analog / digital converter for converting the correlation output into a digital output requires a high resolution, and its configuration is complicated and power consumption is increased. Problems arise.

Further, the configuration described in Japanese Patent No. 2773075 does not cause any problem in the case of a PN code having a small number of taps, but requires a large number of partial correlations to be used as an actual matched filter. It is necessary to add values, and the amount of charge that must be stored increases,
There is a problem that S / N deteriorates. Also in this case, in order to simplify the processing of the correlation output in the subsequent circuit,
An analog / digital converter for converting to a digital output is required.

On the other hand, in order to solve the above problem, a configuration of a matched filter provided with a plurality of correlation accumulation quantizers can be considered as will be described later. The signal processing time, that is, the operating speed of the operational amplifier used in the circuit, determines the speed.If more information is to be transmitted in the same circuit, the operating speed of the operational amplifier must be increased, and as a result, the power consumption is greatly reduced. Will increase. Note that being limited by the operation speed of the operational amplifier has the following meaning. When the operational amplifier performs a process of charging a capacitor according to an input, for example, the time required for the process depends on the processing speed of the operational amplifier. And the processing speed is the same circuit,
The current varies according to the current flowing through the circuit, that is, the power consumption.
To perform the same processing on a signal sequence with a short chip interval, the operational amplifier is required to have a high speed.
Conversely, if the power consumption is limited to a certain level, the chip interval of the signal sequence that can be processed accordingly is limited.

Further, when the same processing is to be performed on several signals, it is necessary to prepare the same circuit for each signal. As a result, the chip area and cost increase. Occurs. Further, there is a possibility that a variation in the correlation output result due to a variation in circuit characteristics may occur.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to increase a signal processing speed without significantly increasing power consumption, and to reduce a signal processing amount and an information transmission amount. It is another object of the present invention to provide a correlator, a matched filter, and a terminal device using the matched filter, which are capable of processing a plurality of series of signals with the same circuit.

[0022]

A correlator according to the present invention comprises:
In order to solve the above-described problem, in a correlator that inputs one or a plurality of continuous analog signal input data in a time series and multiplies the time series data by a code, the signal input times are different from each other. Signal delay means for delaying a plurality of analog signal input data with respect to an input time and outputting the data, and M correlation means for obtaining a cross-correlation between the code and the analog signal input data from the signal delay means are cascaded. Are output from the correlator unit connected in M stages, code generation means for outputting a code to each of the correlator units, and correlator units in the M th stage, which is the last stage of the correlator unit, continuously or at regular intervals. Output processing means for integrating the partial correlation values and calculating one correlation value from the integrated values.

Also, the matched filter according to the present invention is
In order to solve the above-mentioned problem, in a matched filter which inputs one or a plurality of continuous analog signal input data in a time series and multiplies the time series data by a code, the signal input time is A signal delay means for delaying a plurality of different analog signal input data with respect to an input time and outputting the same, and M correlation means for obtaining a cross-correlation between the analog signal input data from the signal delay means and a code are cascaded. A filter block in which correlator units connected in M stages by connection are arranged in an I-sequence in parallel, code generating means for outputting a code to each of the correlating means, and a correlation of the M-th stage which is the last stage of the correlator unit Output processing means for integrating partial correlation values output continuously or at regular intervals from the means, and obtaining one correlation value from the integrated value,
When calculating the cross-correlation between the analog signal input data and the code in each of the correlator means, the same is applied to each of the I correlator means at the K-th stage (K = 1, 2,. Analog signal input data is input, and codes corresponding to mutually different chip sections are input to each of the I-th correlating means in the K-th stage of each correlator unit.

According to each of the above configurations, since the signal delay means is provided, the analog signal input data can be appropriately delayed with respect to the input time and output to the correlator unit which is the main signal processing area. In the correlator unit, M stages of correlating means are sequentially connected and operate in a pipeline system. This makes it possible for each correlation means to perform signal processing in a longer time than the code chip section. Therefore, as a whole correlator or a matched filter, signal processing can be performed at a higher speed than the performance of the operational amplifier used for signal processing.

For example, in a first embodiment of the present invention to be described later, a processing time four times as large as that in the conventional case is allowed and secured. In other words, by using a processing circuit having an operation speed equivalent to that of the conventional correlation means, it becomes possible to perform signal processing for high-speed data transmission that is four times that of the related art.

Further, according to each of the above-described configurations, it is possible to perform most of the data processing on a plurality of streams of analog signal input data with the same circuit element. Therefore,
In this case, it is possible to reduce the difference in the processing result due to the circuit variation.

The fact that the correlating means are connected in M stages by cascade connection means that M correlating means are sequentially connected in a pipeline system.

In the correlator and the matched filter according to the present invention, the signal delaying means includes a plurality of sample-and-hold circuits grouped into M groups according to the number of the M correlating means; And M signal selecting means for selecting one circuit from the plurality of sample and hold circuits and outputting the selected signal.
preferable. Thus, a desired delay operation can be realized with a relatively simple circuit configuration, and the signal delay means can be easily integrated on the same substrate as the substrate on which the correlator unit is formed.

In the correlator and the matched filter of the present invention, when the ratio of the length of the signal processing time in each of the correlating means to the chip section is U, each of the signal selecting means includes a selected sample hold circuit. It is preferable that the analog signal input data is sequentially output to the corresponding correlation means at a time interval U times the chip section. This allows each correlation means
Signal processing can be performed using a calculation processing time that is U times longer than the input rate of the analog signal input data input data. In other words, the same circuit element as the conventional circuit element can be used as the correlator or the matched filter as a whole to perform data processing at a higher speed than the conventional circuit.

In the correlator and the matched filter of the present invention, the number of input signal sequences is two or more, and each of the plurality of sample and hold circuits grouped into the M groups is It has one or more sample-and-hold circuits that sample and hold the signal of the signal sequence, and each of the signal selection means selects the sample-and-hold circuit by switching the signal sequence in order, and serves as the K + 1-th stage correlation means. The corresponding signal selection means is:
It is preferable to select a sample and hold circuit that holds analog signal input data belonging to a signal sequence processed in the time unit in which the K-th correlator performs the immediately preceding signal processing. As a result, a plurality of signal sequences to be processed can be processed by one correlator or one matched filter, and the circuit area and power consumption can be reduced.

Further, in the correlator and the matched filter of the present invention, each of the M correlation means is constituted by a correlation accumulation quantizer, and each correlation accumulation quantizer is provided with an analog signal input data, a code and a code. Multiplying means for calculating the product of the above, analog adding means for integrating the multiplication result of the multiplying means and the analog addition value from the correlation accumulation quantizer at the preceding stage, Analog subtraction means for subtracting a voltage obtained by digital-to-analog conversion of the digital output of the correlation accumulator and analog for performing analog-to-digital conversion by comparing the operation result of the analog subtraction means with a predetermined reference voltage / Digital conversion means, and a digital output for converting the result of the analog / digital conversion means into an analog signal and outputting the voltage to a correlation accumulation quantizer at the next stage. Digital / analog converting means, and digital adding means for adding the digital output of the analog / digital converting means and the digital output of the correlation accumulator up to the preceding stage, and the M number of digital signals in the correlator unit are provided. In the correlation accumulation quantizer, it is preferable that each digital output and the residual of the analog quantity are sequentially transmitted to the next stage correlation accumulation quantizer. by this,
The correlation means in the correlator unit can be easily connected in a pipeline manner, and low power consumption and high-speed operation can be realized. Also, while performing analog / digital conversion,
By performing the integration of the analog residual, the problem of the dynamic range limited by the power supply voltage or the like can be greatly reduced.

Further, in the correlator and the matched filter according to the present invention, the output processing means is connected to an M-th correlating means, which is the last stage of the correlator unit, and the M-stage correlator is provided for one basic period of the code An output processing unit that performs a process of integrating the analog residual output output from the eye correlation means and a process of performing analog / digital conversion on the integration result, and converts the digital output obtained by the analog / digital conversion into It is preferable to add to the digital output from the digital addition means of the M-th correlation means. Thus, a plurality of partial correlation values output from the correlator unit can be integrated to obtain one final correlation value. Also, by extracting a digital value from the sum of the analog residuals of the partial correlation values, it is possible to improve the accuracy of the output correlation value.

[0033] In the correlator and the matched filter according to the present invention, the output processing means includes a signal distributing means for distributing each analog residual output from the correlator unit to a subsequent stage, and the signal distributing means. Signal holding means for holding the analog residual distributed by the above as a holding signal, and a holding signal included in one basic cycle belonging to one signal sequence from a plurality of holding signals held by the signal holding means. Holding signal selection means,
Holding signal adding means for adding the holding signal selected by the holding signal selecting means; and analog / digital converting means for analog / digital converting the added holding signal added by the holding signal adding means. Is preferred. As a result, when processing a plurality of series of signals, most of the signal processing process can be performed by the same circuit, and the effect of circuit variation which is a problem when using a plurality of circuits is reduced. Can be.

Further, in the correlator and the matched filter according to the present invention, the output processing means includes one analog residual signal from the last correlating means and an analog residual signal corresponding to the immediately preceding analog residual signal. An analog adding means for integrating the difference and an arithmetic result of the analog adding means,
Analog subtraction means for subtracting a subtraction voltage obtained by digital / analog conversion of the immediately preceding digital output, and analog / digital conversion for performing analog / digital conversion by comparing a calculation result of the analog subtraction means with a predetermined reference voltage Means, digital / analog converting means for converting the output result of the analog / digital converting means into analog, and outputting to the analog subtracting means as a subtraction voltage for the next analog residual signal, and the result of the analog / digital converting means And a digital adder for adding the result of addition of the digital adder up to the immediately preceding analog residual signal. Thereby, the output processing means can be configured almost in the same manner as the circuit configuration of the correlation accumulation quantizer in the correlator unit, and the circuit can be driven at the same drive timing (clock) as the correlator unit. Become. Furthermore, by performing analog / digital conversion while integrating the analog residual, the problem of the dynamic range limited by the power supply voltage or the like can be greatly reduced.

Further, in the correlator and the matched filter of the present invention, the number of signal sequences processed by one of the correlator units is two or more, and a plurality of output signals of the one correlator unit are output. The output processing means for processing the partial correlation value of the sequence distributes the partial correlation value to a corresponding output processing unit according to the number of output processing units equal to the number of the signal sequences and the signal sequence to which the partial correlation value belongs. It is preferable to adopt a configuration including a sequence selection unit. Thus, a single correlator unit can perform signal processing on a plurality of series of analog signal input data, and can reduce the difference in processing results due to circuit variations.

In the matched filter according to the present invention, the parallel number I of the correlator units is equal to the spreading factor N, and the code generation means generates a PN code, and generates a PN code for the generated PN code. It is preferable that codes corresponding to mutually different chip sections are input to the K-th correlating means of the correlator unit. As a result, the correlation operation using a different code order for one signal sequence required for the operation as a matched filter can be performed.
It can be executed in a short time corresponding to one basic code period.

In the matched filter according to the present invention, when the code generation means is based on a Hadamard sequence and the number of code cycles obtained by the Hadamard sequence is Q, the parallel number I Is equal to the number of cycles Q, the code generation means generates a code by a Hadamard sequence,
For the generated Hadamard code, it is preferable that codes corresponding to mutually different chip sections are input to each of the K-th correlators of the I-series correlator unit. This makes it possible to execute a correlation operation in a different code order for one signal sequence required for the operation as a matched filter in a short time corresponding to one basic code period.

Further, the terminal device of the present invention has a receiving unit corresponding to a communication system of a spread spectrum system, wherein the matched filter of the present invention is used for a synchronization process of a received signal in the receiving unit. I have.

According to the above configuration, in the terminal device,
Higher speed / higher density data processing can be performed as compared with the related art, or more accurate synchronization processing can be realized by sharing most of the signal processing circuits for a plurality of series of signals. be able to.

[0040]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [Embodiment 1] The first embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 is a block diagram showing an electrical configuration of the correlator 1 of the present embodiment. The correlator 1 of the present embodiment includes a signal delay block (signal delay unit) 2, a correlator unit 3,
It comprises a code generation block (code generation means) 4 and an output processing block (output processing means) 5.

The signal delay block 2 is a circuit for delaying continuous analog signal input data input in a time series by a certain time with respect to the signal input and outputting the data to the correlator unit 3. The correlator unit 3 is a circuit that performs processing to be described later on the analog signal input data and outputs a plurality of calculated partial correlation values to the output processing block 5. The correlator unit 3 has a four-stage correlation accumulation quantizer (correlation accumulator). Means 6). The code generation block 4 is a circuit that generates and distributes a code to be supplied to each correlation accumulation quantizer 6 in the correlator unit 3. The output processing block 5 is a circuit that obtains a final correlation output from a plurality of partial correlation values output from the correlator unit 3.

The signal delay block 2 includes 16 sample / hold circuits 7 to which analog signals are input, and 4 circuit selecting means (signal selecting means) 8. The 16 sample and hold circuits 7 are divided into four groups, and each group is composed of four sample and hold circuits 7. Each of the four circuit selecting means 8 corresponds to the above four groups, and is connected to the four sample and hold circuits 7 of the corresponding group. Each circuit selecting means 8 selects one of the four connected sample-and-hold circuits 7 based on the input sample-and-hold circuit selection signal, and sends the hold value to the corresponding correlation accumulation quantizer 6. Output.

As described above, the correlator unit 3 is provided with the four-stage correlation accumulator / quantizer 6, and the correlator 1 of this embodiment is constituted by one correlator unit 3. I have. The code generation block 4 is a code generator (not shown) that generates a basic 16-chip code.
And a distribution means (not shown) for appropriately distributing each code to each correlation accumulation quantizer 6.

FIG. 2 is a block diagram showing a basic configuration of one stage of the correlation accumulation quantizer 6. The correlation accumulation quantizer 6 includes a multiplication unit 11, an addition unit (an analog addition unit and an analog subtraction unit). Means) 12, comparison means (analog / digital conversion means) 13, digital adder (digital addition means)
14 and digital / analog conversion means 15.

In each correlation accumulation quantizer 6, the input signal from the circuit selecting means 8, that is, the analog signal input data X (i) at the time t (i) sampled at the clock cycle Tc is subjected to code generation. The corresponding correlation code a (i) from block 4 is multiplied by the multiplication means 11.
Then, the output is subjected to analog addition by the adding means 12 with the analog residual at the preceding stage. Here, the analog residual is a difference between the analog added value and the value obtained by digital / analog conversion of the quantized value. The analog residual signal input to the adding means 12 in the first-stage correlation accumulation quantizer 6 is a reference voltage.

The comparing means 13 compares the magnitude of the preset reference level with the analog added value outputted from the adding means 12, and digitizes the analog added value by outputting the result. The output of the comparing means 13 is input to both the digital adder 14 and the digital / analog converting means 15.

The digital adder 14 serves as a counter
The digital output from the comparison means 13 is added to the digital output from the preceding stage, and the digital output is output as a new added value.
Each of the correlation accumulators, in addition to the digital output, converts the analog addition value and the digital amount quantized by the comparison means 13 into digital / analog conversion means 15.
The analog-converted D / A converted value is output to the next stage. In FIG. 1, the number of connection lines between the adjacent correlation accumulation quantizers 6 is simplified to one.

In FIG. 2, “Z ⁻¹ ” indicates a time delay in consideration of each of the above-mentioned processing times performed in the correlation accumulation quantizer 6. Is this Z
Processing is completed within the delay time corresponding to ^-1 , and the processing result is output to the next stage. Since the correlation accumulation quantizer 6 is cascade-connected and of a pipeline type, it outputs the processing result and starts the next processing in response to the processing result from the preceding stage.

The number and the configuration of the correlation accumulation quantizers 6 can be variously changed in accordance with the code configuration, the setting of the signal processing time in one correlation accumulation quantizer 6, and the like. It is. Also, the number of chips in one basic cycle of the code can be applied to an arbitrary multiple of 4 when the correlation accumulation quantizer 6 has a four-stage configuration.
The case where the number of chips in the basic cycle is 16 will be described.

The output (partial correlation value) of the correlation accumulation quantizer 6 at the last stage is input to the output processing block 5. The output processing block 5 is a circuit that integrates partial correlation outputs from the correlator unit 3 that are divided into four and output for one code basic period, and outputs the result as one correlation output. Although various configurations of the output processing block 5 are conceivable, the correlator 1 of the present embodiment has a configuration including an output processing unit including an integral quantization unit as shown in FIG. With this configuration, the configuration of the output processing block 5 can be similar to the configuration of the correlation accumulation quantizer 6 shown in FIG.

As shown in FIG. 3, the output processing block 5
Is a digital adder 21 for adding the digital output of the partial correlation output output from the correlator unit 3
And an analog adder (analog adding means / analog subtracting means) 22 for adding the analog residual output from the correlator unit 3, and a reference level set for the integration result of the analog adder 22. A comparison unit (analog / digital conversion unit) 23 for performing analog / digital conversion by performing comparison to obtain a digital output; and a digital / analog conversion of the result of the analog / digital conversion and inverting the sign to an analog adder 22. Digital / analog converter (digital / analog conversion means) 24 for output
And is provided. In the output processing block 5, the digital adder 21, the analog adder 22, the comparing means 23, and the digital / analog converter 24 operate as the integral quantizing means to constitute an output processing unit.

The processing in the output processing block 5 is performed for each integration processing of the analog residual, and the processing is performed on the partial correlation value corresponding to one basic cycle of the code, thereby obtaining 1
A digital output as one correlation value and a final analog residual will be obtained.

Next, the signal processing operation of the correlator 1 of the present embodiment will be described.

As shown in FIG. 4, the 16 sample-hold circuits 7 of the signal delay block 2 sample the analog signal input data in units of the chip time Tc, and hold the sampled data. In FIG. 4, each of the 16 sample-hold circuits 7 is represented by (z, u). Here, z represents the number of the group to which the sample and hold circuit 7 belongs, in other words, the stage number of the corresponding correlation accumulation quantizer 6. U indicates the number of the order of the sample and hold circuits 7 in each group. Therefore, in this case, z = 1, 2, 3, 4 can be taken, and u = 1, 2, 3, 4 can be taken. The hold value is represented as Dm, where m indicates the order of the analog signal input data.

Each of the four circuit selecting means 8 of the signal delay block 2 is connected to four connected sample-and-hold circuits 7.
, One sample hold circuit 7 is selected according to the sample hold circuit selection signal, and the hold value is output to the correlator unit 3.

In the correlator unit 3, the correlation accumulation quantizer 6 receiving the output data Dm of the sample and hold circuit 7 supplies, in addition to the analog input signal Dm, a code output from the code generation block 4, The digital output and analog residual of the preceding correlation accumulation quantizer 6 are input. Then, in the adding means 12 of each correlation accumulation quantizer 6, the value obtained by multiplying the analog input signal Dm by the sign and the analog residual at the preceding stage are analog-added. The added value thus obtained is digitized by the comparison means 13 which is an analog / digital conversion means and a low-resolution quantizer. This digital value is added to the digital output from the previous stage in the digital adder 14, and is digitally output to the next stage as a new added value. The analog addition value output from the addition means 12 and the comparison means 1
The value obtained by digital / analog conversion of the digital quantity quantized in 3 by the digital / analog conversion means 15 is output to the next stage.

In the correlator 1 of the present embodiment, the analog signal input data is sampled and held by the sample and hold circuit 7, so that the data can be output to the correlator unit 3 with a certain delay from the input time. As a result, as described later, each correlation accumulation quantizer 6 can perform arithmetic processing on one piece of data using a processing time (4 * Tc) four times the chip time Tc. ing.

In the following description, the correlation accumulation quantizer 6 at each stage is represented by (y, z). Where y is
The number of the correlator unit 3 is shown. Since the correlator 1 of this embodiment has a configuration including one correlator unit 3, it takes a value of y = 1. Also, z represents the stage number of the correlation accumulation quantizer 6, and in the correlator 1 of the present embodiment, z =
Take 1, 2, 3, 4 Further, the code input to the correlation accumulation quantizer 6 at the n-th stage is represented as ak (1, n). Here, k indicates the order of the codes.

In the correlator 1 of the present embodiment, it is assumed that an analog input signal Dm + 1 and a code a1 (1, 1) are input to the first-stage correlation accumulation quantizer (1, 1) at a time point m + 1. , At time m + 4, Dm + 1 * a1
The partial correlation value of (1, 1) is output.

Further, at time m + 5, at time m + 4
The partial correlation value output from the first-stage correlation accumulation quantizer (1, 1) is transferred to the second-stage correlation accumulation quantizer (1, 2). Assuming that analog input signal Dm + 5 and code a5 (1, 2) are output to correlation accumulation quantizer (1, 2), at time m + 9, second stage correlation accumulation quantizer (1, 2). Is (Dm + 1 * a1 (1,1)) + (D
The partial correlation value of (m + 5 * a5 (1,2)) is output to the next stage. At time m + 5, the analog input signal Dm + 2 is output from the signal delay block 2 to the first-stage correlation accumulation quantizer (1, 1), and at time m + 9,
The partial correlation value of (Dm + 2 * a2 (1,1)) is output to the next stage.

By sequentially repeating the above processing,
From the correlation accumulation quantizer (1, 4) at the last stage, the time point m +
At 16, C1 = (Dm + 1 * a1 (1,1)) + (Dm + 5 * a
5 (1,2)) + (Dm + 9 * a9 (1,3)) + (D
m + 13 * a13 (1,4)) is output. Similarly, time point m + 16
+4, m + 16 + 8, and m + 16 + 12, respectively, C2 = (Dm + 2 * a2 (1,1)) + (Dm + 6 * a
6 (1,2)) + (Dm + 10 * a10 (1,3)) + (D
m + 14 * a14 (1,4)) C3 = (Dm + 3 * a3 (1,1)) + (Dm + 7 * a
7 (1,2)) + (Dm + 11 * a11 (1,3)) + (D
m + 15 * a15 (1,4)) C4 = (Dm + 4 * a4 (1,1)) + (Dm + 8 * a
8 (1,2)) + (Dm + 12 * a12 (1,3)) + (D
A partial correlation value of (m + 16 * a16 (1,4)) is output.

FIG. 5 shows the order (timing) of the processing in each stage of the above-described correlation accumulation quantizer 6. The analog input signal Dm input to each correlation accumulation quantizer 6 is output from the sample and hold circuit 7 via the circuit selecting means 8, but in a state where each sample and hold circuit 7 holds data (that is, holds). The minimum time to do) is shown in FIG. 4 and 5, the lengths of the chip section lengths Tc are different from each other, but the lengths of one section Tc are the same.

As described above, in the correlator unit 3, 1
Only six (four sets) of analog input signal data are processed for each of the six analog input signal data, and the output is obtained by the four partial correlation values C1, C2, C3, and C4. Has become. Each of C1, C2, C3, and C4 has a digital output and an analog residual as correlation outputs. Therefore, it is necessary to obtain one final correlation value from the partial correlation values of C1, C2, C3, and C4.
This processing is performed in the output processing block 5.

In the output processing block 5, with respect to the outputs (partial correlation values) C1, C2, C3 and C4 from the correlator unit 3, the digital correlation values are input to the digital adder 21 when C1 is input. The analog residual is held in the analog adder 22. Next, when the output of C2 is completed, the digital correlation value of the partial correlation value C2 is added to the data held by the digital adder 21 and the analog residual is added to the data held by the analog adder 22. Analog / digital conversion is performed on the data held by the adder 22 by the comparing means 23. Then, the output is added to the data held in the digital adder 21. Also,
The digital / analog converter 24 performs digital / analog conversion on the analog / digital conversion output, and the output result is subtracted from the data held in the analog adder 22. Hereinafter, by repeating the same process for the partial correlation values C3 and C4, one digital correlation value and one analog residual for one basic period of analog input signal data / code are obtained.

Further, a higher-precision analog / digital conversion means is provided at the subsequent stage of the output processing block 5, and the analog residual from the output processing block 5 is further subjected to analog / digital conversion to obtain a higher-precision correlation value. It becomes possible.

As described above, in the correlator 1 of the present embodiment, the correlation accumulation quantizer 6 at each stage performs processing from data input to output for one data with a long time corresponding to four chips. It has become possible. Therefore, signal processing for high-speed data transmission, which is four times as high as that in the related art, becomes possible.

The timing relationship between the operations shown in FIGS. 4 and 5 can be adjusted so as to enable smooth signal processing as a whole. Also, by changing the order of sampling in the sample-and-hold circuit 7, the order in which the correlation accumulation quantizer 6 of each stage processes the analog input signal can be changed as shown in FIG.

[Embodiment 2] A second embodiment of the present invention is described below with reference to FIG.

FIG. 7 shows a matched filter 3 according to this embodiment.
FIG. 2 is a block diagram showing an electrical configuration of FIG. The matched filter 31 according to this embodiment includes a signal delay block 32, a filter block 33, a code generation block 34, and an output processing block 35.

The configuration of the signal delay block 32 is the same as the configuration of the signal delay block 2 in the first embodiment, and a description thereof will be omitted.

The filter block 33 has a configuration in which a plurality of correlator units 3 in the first embodiment are arranged in parallel and operated in parallel. The filter block 33 can be typically configured by arranging the correlator units 3 in parallel by the number equal to the number of chips (spreading ratio N) in one basic period of the code. The code generation block 34 and the output processing block 35 are expanded in accordance with the parallel number, and processing is performed by shifting the code by one for each of the correlator units 3, so that the combination of the signal and the code is different. A plurality of correlation value calculations can be performed in parallel, and the operation as the matched filter 31 can be realized.

In the matched filter 31 of the present embodiment, the filter block 33 has a configuration in which 16 correlators 3 of the first embodiment are arranged in parallel. It comprises an accumulator quantizer 6. The configuration of each correlation accumulation quantizer 6 is as described in the first embodiment. In FIG. 7, the connection line between adjacent correlation accumulation quantizers 6 is simplified to one. I have.

The code generation block 34 generates a basic 16-chip code and distributes and outputs these codes to the correlation accumulation quantizers 6 similarly to the code generation block 4 of the first embodiment. However, a code is output to each correlation accumulation quantizer 6 as follows. That is, codes of mutually different sections within one basic code period are input to the 16 correlation accumulation quantizers 6 at the same stage of each correlator unit 3, and the codes are changed when the analog signal input data is switched. The code generation block 34 is changed so as to change simultaneously.
Outputs a code.

The output processing block 35 has a capacity of 16 in accordance with the number of parallel correlator units 3 in the filter block 33.
The output processing units (output processing means) 36 are arranged in parallel, and the configuration of each output processing unit 36 is the same as the configuration of the output processing block 5 shown in FIG. Each output processing unit 36 includes a filter block 3
Each of the correlator units 3 constituting the correlator unit 3 is integrated into partial correlation outputs which are output in four for one code period and output as one correlation output.

Each of the sample and hold circuits 7 in the signal delay block 32 holds data as shown in FIG. 4, and the held data is sent to the corresponding correlation accumulation quantizer 6 via the circuit selecting means 8. Is output.

In the filter block 33, the same analog signal input data is input to the 16 correlation accumulation quantizers 6 in the same stage of each correlator unit 3. Further, codes of mutually different sections within one basic code period are input to the 16 correlation accumulation quantizers 6 at the same stage of each correlator unit 3, and the codes are changed when the analog signal input data is switched. The code generation block 34 is changed so as to change simultaneously.
Works.

The order (timing) of the processing in each stage of the correlation accumulation quantizer 6 is basically the same as that shown in FIG. 5, but the filter block 33 has 16 correlators. The processing shown in FIG.
It is performed in pairs and in each of the correlator units 3,
The processing shown in FIG. 5 is performed using different codes. As described above, the plurality of correlator units 3 are operated in parallel by the number of codes of one basic code period, and signal processing for one code period is performed, whereby a correlation output as the matched filter 31 is obtained. ing.

As described above, in the matched filter 31 of the present embodiment, the correlation accumulation quantizer 6 in each stage performs processing from data input to output for one data with a long time corresponding to four chips. It is possible to do. Therefore, signal processing for high-speed data transmission, which is four times as high as that in the related art, becomes possible.

As a spreading code generated by the code generating block 34, a pseudo random code called a PN code can be used. When this PN code is used, the product sum of the signal and the code when the signal and the code match becomes very large, and the product sum becomes very small if the signal and the code are slightly shifted. Therefore, good synchronization acquisition by the matched filter 31 is possible.

In addition to the PN code described above, a code generated by Hadamard sequence, that is, a code having a T-period nested structure that enables similar processing to the PN code on a small circuit scale is used as the spreading code. be able to. This is, for example, a spreading code A having a length of 256 chips, A = (a0, a1, a2, ‥, a255), ak = −1, 1 and a code having a unit (basic period / cycle number T) of 16 chips. Assuming that Y and Z are Y = (y0, y1, y2, ‥, y15), yk = −1, 1 Z = (z0, z1, z2, ‥, z15), zk = −1, 1 It is related as follows.

A = (y0 · z0, y1 · z0, y2 · z0, ‥, y15 · z0, y0 · z1, y1 · z1, y2 · z1, ‥, y15 · z1, ｙy0 · z14, y1 · Z14, y2 · z14, ‥, y15 · z14, y0 · z15, y1 · z15, y2 · z15, ‥, y15 · z15) In other words, a16i + j = yj · zi (0 ≦ i, j ≦ 15) Become. Thereby, the input signal Xk is calculated as follows: Xk = (x0 + k, x1 + k, x2 + k, ‥, x16i
+ J + k, ‥, x255 + k), the correlation Sk for this is

[0083]

(Equation 1)

Can be displayed. That is, in the case of the code having the nested structure, first, it is possible to calculate a correlation with a code having a basic period of 16 chips, and to calculate a correlation as a whole based on the correlation result. For a length of 256, processing can be performed by a matched filter for a 16-chip length code, and the circuit size of the matched filter can be significantly reduced. The matched filter according to the present invention is based on operating the multi-stage correlator units in parallel according to the number of code chips, and is therefore suitable for such a nested code.

[Embodiment 3] The following will describe a third embodiment of the present invention with reference to FIGS.

FIG. 8 shows a matched filter 4 according to this embodiment.
FIG. 2 is a block diagram showing an electrical configuration of FIG. The matched filter 41 according to the present embodiment includes a signal delay block 42, a filter block 43, a code generation block 44, and an output processing block 45.

The matched filter 41 of this embodiment corresponds to two different series of analog input signals, and accordingly, the signal delay block 42 and the output processing block 4
5 is different from the matched filter 31 of the second embodiment.

The signal delay block 42 includes sample and hold circuits 7a and 7b respectively corresponding to two signal sequences of the analog signal input A and the analog signal input B, and the circuit selecting means 8. The eleven sample hold circuits 7a and 7b are divided into four groups, and each group includes at least one or more sample hold circuits 7a and 7b. The four circuit selecting means 8
One of the sample and hold circuits 7a and 7b is selected from the corresponding groups, and the hold value is output to each of the correlation accumulation quantizers 6.

Each correlation accumulator / quantizer 6 has the configuration shown in FIG. 2 and its operation is as described above. However, the order of data processed by each correlation accumulator / quantizer 6 is The partial accumulation values corresponding to the two signal sequences are selected so as to be output alternately from the correlation accumulation quantizer 6 in the last stage of the unit 3. That is, each circuit selecting means 8 switches the signal sequence in order so that the sample and hold circuit 7a
7b is selected. Also, as shown in FIG.
Circuit selection means 8 corresponding to the first-stage correlation accumulation quantizer 6
Selects the sample and hold circuits 7a and 7b that hold the analog signal input data belonging to the signal sequence processed in the time unit in which the K-th correlation accumulation quantizer 6 performs the immediately preceding signal processing.

The output processing block 45 has 16 output processing units 46.
Has the configuration shown in FIG. That is, each output processing unit 46 includes a signal distribution unit 47, a signal holding unit 48, a holding signal selection unit 49, an addition unit (holding signal addition unit) 50, an analog / digital converter (analog / digital conversion unit) 51, and A digital adder 52 is provided.

In each output processing unit 46, a plurality of partial correlation values output from the correlation accumulation quantizer 6 in the last stage of the correlator unit 3 are distributed by the signal distribution means 47 and held by the signal holding means 48. Is done. Next, from the holding signals held by the signal holding unit 48, only the holding signal belonging to the analog signal input A or the holding signal belonging to the analog signal input B is selected and selected by the holding signal selection unit 49. The added signals are added by the adding unit 50.

Note that the partial correlation value is composed of a digital output partial correlation value and an analog residual.
From the signal distribution by the signal distribution unit 47 to the addition by the addition unit 50, the digital value and the analog residual are separately processed on the same signal processing path. In FIG.
Each path is shown as a single line for simplicity.

The analog residual added by the adding unit 50 is digitized by an analog / digital converter 51. Then, the digital value is added to the sum of the digital values of the partial correlation values by the digital adder 52, and is output as the final correlation value.

As described above, in the matched filter 41 of the present embodiment, it is possible to perform processing on two series of signals processed by one correlator unit 3 using almost the same circuit unit. Therefore, it is possible to reduce the difference in the processing result due to the circuit variation.

As shown in FIG. 8, the matched filter 41 of this embodiment has a configuration in which two different series of analog signals are input. However, the present invention is not limited to this. Thus, the present invention can be applied as a matched filter corresponding to so-called double sampling, in which one signal sequence is obtained by sampling at a basic chip interval and another signal sequence is obtained by shifting the signal sequence by a half cycle. In this case, the operation can be realized by a small circuit and a long signal processing time for two chips.

When the matched filter 41 of this embodiment is a matched filter corresponding to double sampling, FIG. 10 shows the order in which the sample-hold circuits 7a and 7b sample and hold data.
FIG. 11 shows the order in which the correlation accumulation quantizer 6 of each stage of the filter block 43 processes data. In FIG. 10, the eleven sample hold circuits 7a and 7b are represented by (v, z, u). Here, v indicates a signal sequence, and v =
It can take any value of 1 or 2. Also,
FIG. 11 shows signal sequences in which Da and Db are different from each other.

In the matched filter 41 of this embodiment, the number of the sample-and-hold circuits 7a and 7b is 11 in total. However, the present invention is not limited to this. Considering the simplification of the circuit drive signal or the circuit area. The same operation can be realized by a different number of sample and hold circuits.

[Fourth Embodiment] A fourth embodiment of the present invention will be described below with reference to FIGS.

FIG. 12 is a block diagram showing an electrical configuration of the matched filter 61 of the present embodiment. The matched filter 61 according to this embodiment includes a signal delay block 62, a filter block 63, a code generation block 64, and an output processing block 65.

The matched filter 61 of this embodiment corresponds to four different series of analog input signals, and accordingly, the signal delay block 62 and the output processing block 6
5 is the matched filter 31 of the second and third embodiments.
・ It is different from 41.

The signal delay block 62 includes sample and hold circuits 7a to 7d respectively corresponding to four signal sequences of analog signal input A, analog signal input B, analog signal input C and analog signal input D;
And 16 sample-hold circuits 7a-
7d is divided into four groups, and each group includes at least one or more sample-hold circuits 7a, 7b, 7c, and 7d. The four circuit selecting means 8
One of the sample and hold circuits 7 a to 7 d is selected from the corresponding groups, and the hold values are output to the correlation accumulation quantizers 6.

Each of the correlation accumulation quantizers 6 has the configuration shown in FIG. 2 and its operation is as described above, but the order of data processed by each correlation accumulation quantizer 6 is Are selected so that partial correlation values corresponding to the four signal sequences are sequentially output from the correlation accumulation quantizer 6 in the last stage of the modulator unit 3. That is, each circuit selecting means 8 switches the signal sequence in order so that the sample and hold circuits 7a to 7a
Select 7d. Also, as shown in FIG.
Circuit selection means 8 corresponding to the first-stage correlation accumulation quantizer 6
Selects sample and hold circuits 7a to 7d that hold analog signal input data belonging to a signal sequence processed in the time unit in which the K-th correlation accumulation quantizer 6 performs the immediately preceding signal processing.

The output processing block 65 includes 16 sequence selection means 66, and each sequence selection means 66 is connected to four output processing units 67 corresponding to four input signal sequences. . The sequence selection means 66 is arranged between the correlation accumulation quantizer 6 at the last stage of the correlator unit 3 and the output processing unit 67, and corresponds to a part corresponding to the four signal sequences output from each correlator unit 3. The correlation values are distributed by the sequence selection means 66 to the output processing units 67 corresponding to the respective signal sequences.

In the matched filter 61 of the present embodiment,
FIG. 13 shows the order in which the sample and hold circuits 7a to 7d sample and hold data. The order in which the correlation accumulation quantizer 6 of each stage of the filter block 63 processes data is shown in FIG.
As shown in FIG. In FIG. 13, the 16 sample hold circuits 7a to 7d are represented by (v, z, u). Here, v indicates a signal sequence,
It can take any value of v = 1, 2, 3, or 4. In FIG. 14, Da, Db, Dc and Dd
Indicate signal sequences different from each other.

As described above, in the matched filter 61 of the present embodiment, it is possible to perform processing on signals of four streams processed by one correlator unit 3 using almost the same circuit unit. Therefore, it is possible to reduce the difference in the processing result due to the circuit variation.
Each of the 16 correlation accumulation quantizers 6 performs processing from data input to output at time intervals of one chip.

The matched filter 61 of the present embodiment has a configuration in which four different series of analog signals are input. However, the present invention is not limited to this, and the complex filter 61 includes two signal series called “I” and “Q”. The present invention is also applicable as a matched filter that double-samples and processes each analog input signal. In this case, the operation can be realized by a small-scale circuit and a signal processing time for one chip.

The matched filters 31, 41, and 61 of the above-described second to fourth embodiments can be applied to, for example, a spread spectrum type terminal device 70 having a configuration as shown in FIG. The receiving unit of the terminal device 70 includes an antenna 71, an RF
A transmitting / receiving unit 72, a matched filter 73 for performing synchronization acquisition,
Synchronization tracking unit 74, despreading processing unit 75, audio processing unit 76,
It includes a spread spectrum processing unit 77, a speaker 78, and a microphone 79. In this matched filter 73,
The matched filters 31 41 41 of the second to fourth embodiments described above.
By applying 61, the received signal can be synchronized. That is, the timing of the code included in the received signal is detected by the matched filters 31, 41, and 61, thereby making it possible to establish synchronization for despreading / demodulating the signal. And the matched filter 31
By using 41 and 61, higher-speed / high-density data processing can be performed as compared with the related art, or by sharing most of the signal processing circuits for a plurality of series of signals, Synchronization processing with higher accuracy is realized.

[0108]

As described above, the correlator according to the present invention has the following features.
Signal delay means for outputting a plurality of analog signal input data having different signal input times with a delay with respect to the input time, respectively, and M number of cross-correlations between the analog signal input data from the signal delay means and a code; A correlator unit in which the correlator means are connected in M stages by cascade connection, code generation means for outputting a code to each of the correlator means, and Integrate the partial correlation values output at regular intervals,
Output processing means for obtaining one correlation value from the integrated value.

Further, the matched filter according to the present invention comprises:
As described above, the signal delay means for outputting a plurality of analog signal input data having different signal input times from each other with respect to the input time and outputting the analog signal input data from the signal delay means and the code. A filter block in which correlator units in which M correlation means for obtaining correlation are connected in M stages by cascade connection are arranged in an I-sequence in parallel; code generation means for outputting a code to each of the correlation means;
Output processing means for integrating partial correlation values output continuously or at regular intervals from the M-th correlation means, which is the last stage of the correlator unit, and obtaining one correlation value from the integrated value; When calculating the cross-correlation between the analog signal input data and the code in each of the correlator means, the same is applied to each of the I correlator means at the K-th stage (K = 1, 2,. Analog signal input data is input,
Further, codes corresponding to mutually different chip sections are input to each of the I-th correlating means in the K-th stage of each correlator unit.

Therefore, the whole correlator or the matched filter can perform signal processing at a higher speed than the performance of the operational amplifier used for signal processing. Further, most of the data processing can be performed by the same circuit element for a plurality of series of analog signal input data, so that a difference in processing results due to circuit variation can be reduced.

As described above, according to the correlator and the matched filter of the present invention, the signal delaying means includes a plurality of samples grouped into M groups according to the number of the M correlating means. The configuration includes a hold circuit and M signal selecting means for selecting one circuit from a plurality of sample and hold circuits in each group and outputting the selected signal.

Therefore, a desired delay operation can be realized by a relatively simple circuit configuration, and the signal delay means can be easily integrated on the same substrate on which the correlator unit is formed.

Further, as described above, the correlator and the matched filter of the present invention, when the ratio of the length of the signal processing time in each of the correlating means to the chip section is U,
Each of the signal selecting means is configured to sequentially output analog signal input data from the selected sample and hold circuit to the corresponding correlating means at a time interval U times the chip section.

Therefore, in each correlation means,
Signal processing can be performed using a calculation processing time that is U times longer than the input rate of the analog signal input data input data. In other words, the same circuit element as the conventional circuit element can be used as the correlator or the matched filter as a whole to perform data processing at a higher speed than the conventional circuit.

Further, as described above, the correlator and the matched filter according to the present invention are provided with a plurality of sample-and-hold circuits having two or more input signal sequences and being grouped into the M groups. Each group has at least one sample and hold circuit that samples and holds a signal of each signal series, and each of the signal selection means selects a sample and hold circuit by sequentially switching the signal series, and includes K + 1 stages. The signal selecting means corresponding to the eye correlating means selects a sample and hold circuit for holding analog signal input data belonging to a signal sequence processed in the time unit in which the K-th correlating means performs the immediately preceding signal processing. It is.

Therefore, a plurality of signal sequences to be processed can be processed by one correlator or one matched filter, and the circuit area and power consumption can be reduced.

As described above, in the correlator and the matched filter of the present invention, each of the M correlation means is constituted by a correlation accumulation quantizer, and each correlation accumulation quantizer is constituted by an analog signal. Multiplication means for calculating the product of the input data and the sign; analog addition means for integrating the multiplication result of the multiplication means with the analog addition value from the preceding correlation accumulation quantizer; and calculation result of the analog addition means Against
Analog subtraction means for subtracting a voltage obtained by digital / analog conversion of the digital output of the correlation accumulation quantizer at the preceding stage, and analog / digital conversion by comparing the operation result of the analog subtraction means with a predetermined reference voltage. Analog / digital conversion means, digital / analog conversion means for converting the result of the analog / digital conversion means to analog, and outputting the voltage to a correlation accumulation quantizer at the next stage;
Digital addition means for adding the digital output of the analog / digital conversion means to the digital output of the correlation accumulator up to the preceding stage,
Each of the correlation accumulation quantizers has a configuration in which the digital output and the residual of the analog amount are sequentially transmitted to the correlation accumulation quantizer at the next stage.

Therefore, the correlation means in the correlator unit can be easily connected in a pipeline system, and low power consumption and high speed operation can be realized. Further, by performing analog / digital conversion and integrating the analog residual, the problem of the dynamic range limited by the power supply voltage or the like can be greatly reduced.

Further, in the correlator and the matched filter according to the present invention, as described above, the output processing means is connected to the M-th correlating means, which is the last stage of the correlator unit. An output processing unit that performs a process of integrating an analog residual output output from the M-th stage correlation means in a cycle and a process of performing an analog / digital conversion on the integration result; The digital output thus obtained is added to the digital output from the digital addition means of the M-th correlation means.

Therefore, a plurality of partial correlation values output from the correlator unit can be integrated to obtain one final correlation value. Also, by extracting a digital value from the sum of the analog residuals of the partial correlation values, it is possible to improve the accuracy of the output correlation value.

As described above, in the correlator and the matched filter of the present invention, the output processing means includes a signal distribution means for allocating each analog residual output from the correlator unit to a subsequent stage. A signal holding unit that holds the analog residual distributed by the signal distribution unit as a holding signal; and a plurality of holding signals held by the signal holding unit, which are included in one basic cycle belonging to one signal sequence. Holding signal selecting means for selecting a holding signal to be used, holding signal adding means for adding the holding signals selected by the holding signal selecting means, and analog for performing analog / digital conversion of the added holding signal added by the holding signal adding means. / Digital conversion means.

Therefore, when processing a plurality of series of signals, most of the signal processing steps can be processed by the same circuit, and the influence of circuit variation which is a problem when using a plurality of circuits is reduced. Can be reduced.

Further, in the correlator and the matched filter according to the present invention, as described above, the output processing means includes the one analog residual signal from the last correlator and the analog residual signal immediately before the analog residual signal. An analog adding means for integrating an analog residual corresponding to the following, an analog subtracting means for subtracting a subtraction voltage obtained by digitally / analog-converting a previous digital output from an operation result of the analog adding means, Analog / digital conversion means for performing an analog / digital conversion by comparing the operation result of the subtraction means with a predetermined reference voltage; and converting the output result of the analog / digital conversion means into an analog signal, the next analog residual signal Digital / analog conversion means for outputting to the analog subtraction means as a subtraction voltage with respect to the result of the analog / digital conversion means A configuration and a digital adder for adding to the addition result of the digital adder to its previous analog residual signal.

Therefore, the output processing means can be configured substantially in the same way as the circuit configuration of the correlation accumulator in the correlator unit, and the circuit can be driven at the same drive timing (clock) as the correlator unit. Becomes possible. Furthermore, by performing analog / digital conversion while integrating the analog residual, the problem of the dynamic range limited by the power supply voltage or the like can be greatly reduced.

As described above, according to the correlator and the matched filter of the present invention, when the number of signal sequences processed by one of the correlator units is two or more, The output processing means for processing the partial correlation values of a plurality of sequences as outputs corresponds to the number of output processing units equal to the number of the signal sequences and the partial correlation values according to the signal sequence to which the partial correlation values belong. And a sequence selection means for allocating to the output processing unit.

Therefore, a single correlator unit can perform signal processing on a plurality of series of analog signal input data,
Differences in processing results due to circuit variations can be reduced.

As described above, in the matched filter of the present invention, the parallel number I of the correlator units is equal to the spreading ratio N, the code generation means generates a PN code, and the generated PN code , K of the correlator unit of the I sequence
Codes corresponding to mutually different chip sections are input to each correlating means in the stage.

Therefore, it is possible to execute a correlation operation in a different code order for one signal sequence required for operation as a matched filter in a short time corresponding to one basic code period.

In the matched filter of the present invention, as described above, when the code generation means is based on the Hadamard sequence, and the number of cycles of the code obtained by the Hadamard sequence is Q, the correlator The number of parallel units I is equal to the number of cycles Q, the code generation means generates a code by Hadamard sequence, and for each generated Hadamard code, each correlator at the K-th stage of the correlator unit of the I series has: In this configuration, codes corresponding to mutually different chip sections are input.

Therefore, it is possible to execute a correlation operation in one code sequence required for the operation as a matched filter in a different code order in a short time corresponding to one basic code period.

Further, as described above, the terminal device of the present invention has a receiving unit corresponding to a spread spectrum communication system, and uses the matched filter of the present invention in the receiving unit for synchronization processing of a received signal. It was the configuration that was.

Therefore, in the terminal device, higher speed / higher density data processing can be performed as compared with the conventional one, or by sharing most of the signal processing circuits for a plurality of series of signals. Thus, more accurate synchronization processing can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an electrical configuration of a correlator according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing an electrical configuration of a correlation accumulation quantizer provided in the correlator.

FIG. 3 is a block diagram showing an electrical configuration of an output processing block provided in the correlator.

FIG. 4 is a diagram showing operation timing of a sample and hold circuit provided in the correlator.

FIG. 5 is a diagram showing operation timings of a correlation accumulation quantizer included in the correlator.

FIG. 6 is a diagram showing another operation timing of the correlation accumulation quantizer included in the correlator.

FIG. 7 is a block diagram illustrating an electrical configuration of a matched filter according to a second embodiment of the present invention.

FIG. 8 is a block diagram illustrating an electrical configuration of a matched filter according to a third embodiment of the present invention.

FIG. 9 is a block diagram showing an electrical configuration of an output processing unit provided in the matched filter.

FIG. 10 is a diagram showing operation timings of a sample and hold circuit provided in the matched filter.

FIG. 11 is a diagram showing operation timing of a correlation accumulation quantizer included in the matched filter.

FIG. 12 is a block diagram illustrating an electrical configuration of a matched filter according to a fourth embodiment of the present invention.

FIG. 13 is a diagram showing operation timings of a sample and hold circuit provided in the matched filter.

FIG. 14 is a diagram showing operation timings of a correlation accumulation quantizer included in the matched filter.

FIG. 15 is a block diagram showing a configuration of a terminal device to which the matched filter of the present invention can be applied.

FIG. 16 is a block diagram showing an electrical configuration of a conventional matched filter.

[Explanation of symbols]

1. Correlator 2. 32. 42. 62 Signal delay block (signal delay means) 3. Correlator unit 4. 34. 44. 64 Code generation block (code generation means) 5. 35. 45. 65 Output processing block (output processing) Means 6 Correlation accumulation quantizer (Correlation means) 7.7a-7d Sample hold circuit 8 Circuit selection means (Signal selection means) 11 Multiplication means 12 Addition means (Analog addition means / Analog subtraction means) 13 Comparison means (Analog) / Digital conversion means) 14 digital adder (digital addition means) 15 digital / analog conversion means 21 digital adder 22 analog adder (analog addition means / analog subtraction means) 23 comparison means (analog / digital conversion means) 24 digital / Analog converter (digital / analog conversion means) 31.41.61 Matched filter 33.43.6 Filter block 36/46/67 Output processing unit (output processing means) 47 Signal distribution means 48 Signal holding means 49 Holding signal selection means 50 Addition unit (Holding signal addition means) 51 Analog / Digital converter (Analog / Digital conversion means) 52 digital adder 66 sequence selection means 70 terminal device

Claims (21)

[Claims] 1. A correlator for inputting one or more series of continuous analog signal input data in time series, multiplying the time series data by a code, and integrating the signals, wherein a plurality of analog signals having different signal input times are provided. A signal delay means for delaying input data with respect to an input time and outputting the same, and M correlation means for obtaining a cross-correlation between a code and the analog signal input data from the signal delay means are connected in M stages by cascade connection. Correlator unit, code generation means for outputting a code to each of the correlator means, and partial correlation values output continuously or at regular intervals from the M-th correlator means, which is the last stage of the correlator unit And an output processing means for calculating one correlation value from the integrated value. 2. The method according to claim 1, wherein the signal delay means includes a plurality of sample-hold circuits grouped into M groups according to the number of the M correlation means, and a plurality of sample-hold circuits in each group. 2. The correlator according to claim 1, further comprising: M signal selecting means for selecting one circuit and outputting the signal. 3. When the ratio of the length of the signal processing time to the chip section in each of the correlating means is U, each of the signal selecting means converts the analog signal input data from the selected sample and hold circuit into the U of the chip section. 3. The correlator according to claim 2, wherein the correlator outputs the data to the corresponding correlator sequentially at twice the time interval. 4. The method according to claim 1, wherein the number of input signal sequences is two or more,
Each group of the plurality of sample and hold circuits grouped into the M groups has at least one sample and hold circuit that samples and holds a signal of each signal sequence. The sample-and-hold circuit is selected in the order of switching, and the signal selecting means corresponding to the (K + 1) -th correlating means is a signal sequence processed by the K-th correlating means in the time unit in which the immediately preceding signal processing is performed. 4. The correlator according to claim 3, wherein a sample-and-hold circuit for holding analog signal input data belonging to the following is selected. 5. The M number of correlation means are each constituted by a correlation accumulation quantizer, each correlation accumulation quantizer comprising: multiplication means for calculating a product of analog signal input data and a sign; Analog addition means for integrating the multiplication result of the means and the analog addition value from the correlation accumulation quantizer at the preceding stage; anda digital output of the correlation accumulation quantization device at the preceding stage for the operation result of the analog addition means. Analog subtraction means for subtracting the digital / analog converted voltage; analog / digital conversion means for performing analog / digital conversion by comparing a calculation result of the analog subtraction means with a predetermined reference voltage; Digital / analog converting means for converting the result of the means into analog and outputting the voltage to the next-stage correlation accumulation quantizer; And a digital adder means for adding the digital output of the correlation accumulator quantizer to digital outputs and preceding switch means, in the M correlation accumulator quantizer in said correlator unit,
The correlator according to any one of claims 1 to 4, wherein each digital output and the residual of the analog amount are sequentially transmitted to a correlation accumulation quantizer at the next stage. 6. The output processing means is connected to the M-th correlating means, which is the last stage of the correlator unit, and outputs the analog residual output from the M-th correlating means in one basic period of the code. An output processing unit that performs a process of integrating outputs and a process of performing analog-to-digital conversion on the integration results, and a digital addition unit of the correlation unit at the M-th stage that uses the digital output obtained by the analog-to-digital conversion The correlator according to any one of claims 1 to 5, wherein the correlation is added to a digital output from the correlator. 7. The output processing means includes: a signal distribution means for outputting each analog residual output from the correlator unit to a subsequent stage; and an analog residual distributed by the signal distribution means as a holding signal. Holding signal holding means, holding signal selection means for selecting a holding signal included in one basic cycle belonging to one signal sequence from a plurality of holding signals held by the signal holding means, and holding signal selection means A holding signal adding unit that adds the holding signal selected by the following: and an analog / digital conversion unit that performs analog / digital conversion on the added holding signal added by the holding signal adding unit. 7. The correlator according to any one of 6. 8. An output processing means, comprising: an analog addition means for integrating one analog residual signal from the last-stage correlation means and an analog residual corresponding to the immediately preceding analog residual signal; Analog subtraction means for subtracting a subtraction voltage obtained by digital-to-analog conversion of the previous digital output with respect to the operation result of the analog addition means; and comparing the operation result of the analog subtraction means with a predetermined reference voltage. Analog / digital conversion means for performing analog / digital conversion; and digital / analog conversion means for performing an analog conversion on an output result of the analog / digital conversion means and outputting to the analog subtraction means as a subtraction voltage for the next analog residual signal. And adding the result of the analog / digital conversion means to the digital adder up to the previous analog residual signal. Correlator according to claim 6 or 7, characterized in that it comprises a digital adder for adding the results. 9. An output processing means for processing two or more signal sequences to be processed by one of said correlator units, and for processing partial correlation values of a plurality of sequences output from said one correlator unit. Comprises a number of output processing units equal to the number of the signal sequences, and sequence selection means for allocating the partial correlation values to the corresponding output processing units according to the signal sequence to which the partial correlation value belongs. The correlator according to claim 6. 10. A matched filter for inputting one or more series of continuous analog signal input data in time series, multiplying the time series data by a code, and integrating the same, wherein a plurality of analog signals having different signal input times are provided. A signal delay means for delaying the signal input data with respect to an input time and outputting the signal; and M correlating means for obtaining a cross-correlation between the analog signal input data from the signal delay means and a code are provided in M stages by cascade connection. A filter block in which connected correlator units are arranged in an I-sequence in parallel; a code generation means for outputting a code to each of the correlator means; Or output processing means for integrating partial correlation values output at regular intervals and obtaining a single correlation value from the integrated value. When calculating the cross-correlation between the input signal and the code, the same analog signal input data is stored in each of the I correlator means at the K-th stage (K = 1, 2,..., M) of each correlator unit. A matched filter, wherein a code corresponding to a different chip section is input to each of the I correlator means at the K-th stage of each correlator unit. 11. The signal delay means includes: a plurality of sample-hold circuits grouped into M groups according to the number of the M correlation means; and a plurality of sample-hold circuits in each group. 11. The matched filter according to claim 10, further comprising: M signal selecting means for selecting one circuit and outputting the signal. 12. When the ratio of the length of the signal processing time to the chip section in each of the correlation means is U, each of the signal selection means converts the analog signal input data from the selected sample and hold circuit into the U of the chip section. 12. The matched filter according to claim 11, wherein the output is output to the correlating means sequentially corresponding to the double time interval. 13. A sample and hold circuit, wherein the number of input signal sequences is two or more, and each group of the plurality of sample and hold circuits grouped into the M groups samples and holds a signal of each signal sequence. Each of the signal selecting means selects a sample-and-hold circuit by sequentially switching a signal sequence, and the signal selecting means corresponding to the (K + 1) -th correlating means comprises a K-th stage. 13. The matched filter according to claim 12, wherein the correlating means selects a sample and hold circuit for holding analog signal input data belonging to a signal sequence processed in a time unit in which the immediately preceding signal processing is performed. 14. The M number of correlation means are each constituted by a correlation accumulation quantizer, wherein each correlation accumulation quantizer comprises: a multiplication means for calculating a product of analog signal input data and a sign; Analog addition means for integrating the multiplication result of the means and the analog addition value from the correlation accumulation quantizer at the preceding stage; anda digital output of the correlation accumulation quantization device at the preceding stage for the operation result of the analog addition means. Analog subtraction means for subtracting the digital / analog converted voltage; analog / digital conversion means for performing analog / digital conversion by comparing a calculation result of the analog subtraction means with a predetermined reference voltage; Digital / analog converting means for converting the result of the means into analog and outputting the voltage to a correlation accumulation quantizer at the next stage; And a digital adder means for adding the digital output of the correlation accumulator quantizer to the digital output and the previous stage of the conversion means, in the M correlation accumulator quantizer in said correlator unit,
14. The matched filter according to claim 10, wherein each digital output and the residual of the analog amount are sequentially transmitted to a correlation accumulation quantizer at a next stage. 15. The output processing means is connected to the M-th correlating means, which is the last stage of the correlator unit, and the analog residual output from the M-th correlating means in one basic cycle of the code. An output processing unit that performs a process of integrating outputs and a process of performing analog-to-digital conversion on the integration results, and a digital addition unit of the correlation unit at the M-th stage that uses the digital output obtained by the analog-to-digital conversion The matched filter according to any one of claims 10 to 14, wherein the value is added to a digital output from the filter. 16. The output processing means includes: a signal distribution means for outputting each analog residual output from the correlator unit to a subsequent stage of distribution; and an analog residual distributed by the signal distribution means as a holding signal. Holding signal holding means, holding signal selection means for selecting a holding signal included in one basic cycle belonging to one signal sequence from a plurality of holding signals held by the signal holding means, and holding signal selection means 11. A holding signal adding means for adding a holding signal selected by the following, and an analog / digital conversion means for performing analog / digital conversion of the added holding signal added by the holding signal adding means. 16. The matched filter according to any one of items 15 to 15. 17. An output processing means, comprising: an analog addition means for integrating one analog residual signal from the last stage correlation means and an analog residual corresponding to the immediately preceding analog residual signal; Analog subtraction means for subtracting a subtraction voltage obtained by digital-to-analog conversion of the previous digital output with respect to the operation result of the analog addition means; and comparing the operation result of the analog subtraction means with a predetermined reference voltage. Analog / digital conversion means for performing analog / digital conversion; and digital / analog conversion means for performing an analog conversion on an output result of the analog / digital conversion means and outputting to the analog subtraction means as a subtraction voltage for the next analog residual signal. The result of the analog / digital conversion means to the digital adder up to the previous analog residual signal. Matched filter of claim 15 or 16, wherein further comprising a digital adder for adding relative calculation results. 18. An output processing means for processing two or more signal sequences in one of the correlator units and processing partial correlation values of a plurality of sequences output from the one correlator unit. Comprises a number of output processing units equal to the number of the signal sequences, and sequence selection means for allocating the partial correlation values to the corresponding output processing units according to the signal sequence to which the partial correlation value belongs. Claims 15-17
The matched filter according to any one of the above. 19. The parallel number I of the correlator units is equal to the spreading factor N, the code generation means generates a PN code, and for the generated PN code, the K-th stage of the I-series correlator unit. 2. A code corresponding to mutually different chip sections is input to each correlating means.
19. The matched filter according to any one of 0 to 18. 20. When the code generation means is based on a Hadamard sequence and the number of cycles of the code obtained by the Hadamard sequence is Q, the parallel number I of the correlator units is equal to the number of cycles Q, The code generation means generates a code by a Hadamard sequence, and for the generated Hadamard code, codes corresponding to mutually different chip sections are input to each of the K-th correlation means of the I-sequence correlator unit. The matched filter according to any one of claims 10 to 18, wherein: 21. A receiving section corresponding to a spread spectrum communication system, wherein the receiving section includes:
20. A terminal device, wherein the matched filter according to any one of 20. is used for synchronization processing of a received signal.