JP2001077311A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the power consumption of data transfer between circuit modules more easily than that of radio wave communication by using no signal wiring for parallel processing and suppressing the load to a driver to the minimum. SOLUTION: In a semiconductor device, a plurality of arithmetic units 2 is loaded in one well 1 in such a way that the units 2 are not connected to each other through wiring. The information transmitted to the units 2 are processed in parallel by propagating the information in the well 1. Since the well 1 is used as the propagating route of signals, no signal wiring is required for the parallel processing. Therefore, an increase in wiring load can be suppressed and the circuit configuration becomes simpler than that for radio wave communication. Accordingly, the power consumption of information transmission can be suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device capable of transferring data between circuit modules, and more particularly to a semiconductor device capable of transferring data between arithmetic circuits such as a neural network that requires parallel processing.

[0002]

2. Description of the Related Art Conventionally, when parallel or high-speed data transfer is performed between chips such as arithmetic circuits, a pipeline method, radio communication using radio waves, and the like are used. As an example of the former, for example, there is a parallel operation circuit disclosed in Japanese Patent Application Laid-Open No. 4-273529. In this parallel operation circuit, a plurality of operation units are provided for performing pipeline processing, and parallel operations are executed by simultaneously giving operation instructions to these operation circuits.

As an example of the latter, see, for example,
There is a wafer scale integrated circuit disclosed in Japanese Patent No. 5046. In this wafer scale integrated circuit, a plurality of microwave / millimeter wave transmitting / receiving modules with antennas and a plurality of modems are provided on a wafer. In this case, although the purpose is to reduce the signal delay, if the above-mentioned transmitting / receiving module and the like are provided in each chip, parallel data communication becomes possible.

[0004]

However, the parallel operation circuit disclosed in Japanese Patent Laid-Open No. 4-273529 has the following problems. That is, when the number of arithmetic units performing pipeline processing increases, the number of signal wires connecting the arithmetic units rapidly increases, for example, in proportion to the square of the number of arithmetic units, and the chip size and the wiring load are reduced. It causes an extreme increase.

Further, in the wafer scale integrated circuit disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 4-25046, a circuit for transmission and reception is complicated because radio waves such as microwaves and millimeter waves are used. This leads to an increase in chip size and power consumption. In addition, since radio waves propagate freely in space, problems such as EMI (Electro Magnetic Interference) and EMC (Electro Magnetic Compatibility) may occur, and countermeasures are needed. Becomes

Accordingly, an object of the present invention is to eliminate signal wiring in parallel processing, minimize the load on the driver,
An object of the present invention is to provide a semiconductor device which is simpler than radio wave communication and enables low power consumption of data transfer between circuit modules.

[0007]

In order to achieve the above object, a semiconductor device according to the present invention has a plurality of arithmetic units mounted in the same well, and input / output signals for each of the arithmetic units propagate through the well. It is characterized by sending and receiving.

According to the above configuration, input / output signals for each arithmetic unit are transmitted and received without passing through the wiring connecting the arithmetic units. Therefore, even if the number of the arithmetic units increases, the device size does not increase due to an increase in the wiring load or the number of wires, and a larger-scale parallel arithmetic device is realized. Further, since the signals transmitted and received between the arithmetic units propagate in the well, there is no radio interference as seen in general wireless communication, no complicated transmission / reception circuit is required, and power consumption is suppressed.

Further, in the semiconductor device of the present invention, it is preferable that a plurality of wells on which the plurality of arithmetic units are mounted are provided, and the plurality of wells are connected in parallel by a wiring layer.

According to the above configuration, a signal from the arithmetic unit mounted on one well is transmitted to the other well via the well and the wiring layer. Then, it propagates through the other well and is transmitted to an arithmetic unit mounted on the other well. As described above, by transmitting a signal between a plurality of wells in the wiring layer, a signal generated by propagating the other well that occurs when transmitting a signal between the plurality of wells in another well is performed. Extreme delays and attenuation are avoided. Also, the operation results of each operation unit mounted on one well are collectively transmitted to other wells, and only the operation results required from the operation results transmitted from each well through the wiring layer are transmitted. Is realized. Furthermore, if the wiring layer has bidirectionality, higher-speed operations can be performed.

Further, in the semiconductor device of the present invention, it is preferable that a plurality of wells on which the plurality of arithmetic units are mounted are provided, and the plurality of wells are hierarchically connected by a wiring layer.

According to the above configuration, the operation results from the operation units mounted on the plurality of wells located in the lower layer propagate through the wiring layer and are transmitted to the operation units mounted on the wells located on the upper layer. In this way, the operation results of the arithmetic units mounted on one well located in the lower layer are collectively transmitted to the well located in the upper layer, or transmitted from each well in the lower layer by the arithmetic unit mounted on the upper well. A system function such as selecting only necessary calculation results from the calculation results to be obtained is realized.

Further, in the semiconductor device according to the present invention, a plurality of first wells on which the plurality of arithmetic units are mounted are provided, and the first well is electrically separated from the first well and mounted with the first well. It is preferable to include a transmission / reception circuit for transmitting / receiving a signal in one direction or two directions between the first well and the second well.

According to the above arrangement, when the number of wiring layers for connecting the plurality of wells in parallel or in a hierarchical manner is large,
By eliminating the wiring layer, an increase in device size due to an increase in wiring load and an increase in the number of wires is suppressed, and a larger-scale parallel operation device is realized.

Further, the semiconductor device of the present invention has an input control circuit for inputting an external signal to at least one well,
It is desirable to include an output control circuit that outputs an internal signal from at least one well to the outside.

According to the above configuration, the present semiconductor device can transmit and receive signals by being connected to an external peripheral circuit or the like. Therefore, it is possible to perform synchronous driving with an external clock, specify an operation unit that starts an operation or an operation unit that ends an operation from the outside, and feedback an operation result to the outside.

Further, in the semiconductor device according to the present invention, the arithmetic units mounted on the wells to which the external signals are input are arranged in a matrix, and the input units are arranged in a matrix.
Preferably, one of them is arranged in parallel with one arrangement direction in the arrangement matrix of the operation units, and the other is arranged in parallel with the other arrangement direction in the arrangement matrix of the operation units.

According to the above configuration, among the plurality of arithmetic units arranged in a matrix, the conditions such as the amplitude and the arrival time of the external signal reaching the arithmetic units arranged in parallel with both input units are made uniform. Can be Thus,
A two-dimensional weighting calculation network applicable to calculations such as image processing is formed.

Further, the semiconductor device according to the present invention includes a receiving unit for receiving the signal propagated in the well and a decoder for converting the received signal into a form capable of performing arithmetic processing. An arithmetic unit for arithmetically processing the converted signal, an encoder for converting the arithmetically processed signal into a form that can be transmitted, and a transmitting unit for transmitting the signal converted by the encoder to the well. It is desirable.

According to the above configuration, the signal received by the receiving unit of the arithmetic unit is decoded, arithmetically processed by the arithmetic unit, encoded, and then transmitted again into the well by the transmitting unit. Thus, the arithmetic processing is performed in parallel by all the arithmetic units in which the receiving unit is connected to the same well, and the result is output to the well. That is, a configuration of a neural network in which all the arithmetic units are connected to each other is realized.

Further, in the semiconductor device according to the present invention, the arithmetic unit may include a receiving unit for receiving a signal propagated in the well, an arithmetic unit for arithmetically processing the received signal, and an arithmetic processing unit for arithmetically processing the received signal. It is desirable to constitute a transmission unit for transmitting the signal thus obtained into the well.

According to the above configuration, the signal received by the receiving unit of the arithmetic unit is subjected to arithmetic processing by the arithmetic unit, and is transmitted again into the well by the transmitting unit.
Thus, the configuration of the arithmetic unit when the arithmetic unit is an analog circuit or the like and conversion of a received signal is not required is simplified. Further, an analog neural network configuration in which all the arithmetic units are connected to each other is realized.

Further, in the semiconductor device of the present invention, the arithmetic unit may be configured to determine whether the received signal is a signal to be fetched, and determine whether the signal satisfies a desired rule. It is desirable to comprise an inspection circuit for inspection and an arithmetic unit for performing a predetermined operation based on information in the signal.

According to the above configuration, the determination circuit determines whether or not the received signal is a signal to be captured, and determines whether or not the check circuit satisfies the rule that the signal is the first signal captured by the arithmetic unit. The distance between other arithmetic units connected by fictitious roads by the arithmetic unit is added to the total number of distances, so that the route of the one-stroke such as the Hamilton problem or the traveling salesman problem and the shortest The solution to the problem of finding distance is obtained at high speed.

Further, in the semiconductor device of the present invention, the arithmetic unit may be configured to determine whether the received signal is a signal to be fetched, and determine whether the signal satisfies a desired rule. An inspection circuit to be inspected, a delay amount designating means for designating a delay amount when delaying the signal, and a delay circuit for delaying the signal based on the delay amount designated by the delay amount designating means. Is desirable.

According to the above configuration, the determination circuit determines whether or not the received signal is a signal to be captured, and determines whether or not the inspection circuit satisfies the rule of being the first signal captured by the arithmetic unit. Inspection is performed, and a delay amount designating unit specifies a delay amount corresponding to a distance to another arithmetic unit connected on an imaginary road, and a delay circuit determines a distance to the other arithmetic unit. By delaying the signal by a corresponding amount of delay, the signal output from the transmission unit to the well is delayed by a time corresponding to the distance to another arithmetic unit connected by an imaginary path. Output.

Therefore, when finding the solution to the problem for finding the shortest distance, such as the traveling salesman problem, it is not necessary to select the solution exhibiting the minimum value from the solutions obtained by all the arithmetic units mounted on the same well. The solution first output to the well becomes the desired solution as it is. Thus, the calculation time and the power consumption are reduced.

Also, in the semiconductor device according to the present invention, the receiving section includes a transistor, a gate of the transistor is electrically connected to the well, and one of a source and a drain of the transistor is connected to a voltage source. And the other of the source and the drain is desirably connected to the decoder or the arithmetic unit.

According to the above configuration, the voltage fluctuation of the signal propagating through the well is converted by the receiving section into a voltage fluctuation or a current fluctuation required by the decoder or the operation section circuit at the subsequent stage and transmitted. You.

Preferably, the transistor in the semiconductor device of the present invention is formed in another well that is electrically separated from the well to which the gate is connected.

According to the above configuration, the threshold value of the transistor does not change due to the voltage change of the well, and the voltage change of the well is caused by a voltage change or a current change required in the subsequent decoder or the arithmetic circuit. Converted exactly.

Further, in the semiconductor device of the present invention, the receiving section includes a transistor, one of a source and a drain of the transistor is connected to a voltage source, and the other of the source and the drain is connected to the decoder or the decoder. It is preferable that the transistor is connected to the arithmetic unit and the gate of the transistor is connected to the voltage source or another voltage source.

According to the above arrangement, the voltage fluctuation of the signal propagating through the well is regarded as a threshold fluctuation of the transistor, and is converted into a voltage fluctuation or a current fluctuation required by the decoder or the arithmetic circuit in the subsequent stage. Transmitted.

In the semiconductor device according to the present invention, the transmission section includes a capacitance-equivalent element in which one electrode is connected to the encoder or the operation section and the other electrode is connected to the well. It is desirable to do.

According to the above configuration, the calculation result from the encoder or the calculation unit is transmitted by the transmission unit by the transmission unit.
The voltage is propagated to the well as a voltage fluctuation.

Further, in the semiconductor device according to the present invention, the transmitting section includes a current drive circuit having an input terminal connected to the encoder or the arithmetic section and an output terminal connected to the well. Is desirable.

According to the above configuration, the operation result from the encoder or the operation unit is transmitted by the transmission unit by the transmission unit.
The current fluctuation is propagated to the well.

[0038]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments. FIG. 1 is a plan view of the semiconductor device of the present embodiment. In this semiconductor device, a plurality of operation units 2 are mounted in one well 1, and the operation units 2 are not connected by wiring. Then, transmission information such as input / output (excluding some basic signals for operating the arithmetic unit 2 such as a power supply) and the like propagates in the well 1.
Therefore, the signal propagated through the well 1 is received by all the operation units 2 in the same well 1, and the signal whose content has been updated according to the operation result of each operation unit 2 is It is transmitted to well 1 again. The above is the basic configuration for performing the parallel operation by the plurality of operation units 2.

FIG. 2 shows an example of the arithmetic unit 2 in FIG. The arithmetic unit 2 includes a receiving unit 5, a decoder 6, an arithmetic unit 7, an encoder 8, and a transmitting unit 9. The signal that has propagated through well 1 is received by receiving section 5. Then, the received signal is decoded by the decoder 6 and becomes a digital signal or an analog signal that can be processed by the arithmetic unit 7. The calculation result is converted again into a signal format suitable for propagation by the encoder 8 and transmitted from the transmission unit 9 to the well 1.

An arithmetic unit (eg, an arithmetic unit that does not require the decoder 6 or the encoder 8) depending on the specific circuit of the arithmetic unit 7 and the signal format of communication in the well 1
(An analog circuit) can also be configured, an example of which is shown in FIG. 11 is a receiving unit, 12 is a calculating unit, and 13 is a transmitting unit.

FIG. 4 shows an example of the receiving sections 5 and 11. The signal propagating through the well 16 provided on the substrate 15 is received by the tap 17. As the tap 17, a diffusion of the same type as the well 16 and having a different concentration is used (for example, if the well 16 is n ⁻ diffusion, the tap 17 is n ⁺ diffusion). Thus, a p-type and n-type diode configuration may be used to rectify.

The signal received by the tap 17 is input to the gate 19 of the transistor 18, and the current flowing between the source 20 and the drain 21 changes according to the voltage fluctuation. A voltage source 22 is connected to the source 20, and a decoder or operation unit 23 is connected to the drain 21, and detects a change in current or voltage to perform decoding or operation.

FIG. 5 is a block diagram of the receiving units 5 and 11 shown in FIG.
Here is a different example. The difference from the case of FIG. 4 is that the back bias of the transistor 28 for detecting voltage fluctuation is surrounded by a well 31 and is electrically separated from the well 26 for transmitting a signal. In this manner, a change in the threshold voltage of the transistor 28 can be prevented, and a change in the gate voltage can be detected more accurately. In that case, well 26
And the well 31 are usually selected between a p-type and an n-type so as to have a reverse breakdown voltage. In addition, 25 is a substrate, 27 is a tap, 29 is a voltage source, and 30 is a decoder or an operation unit.

FIG. 6 shows still another example of the receiving units 5 and 11. The signal propagating through the well 36 changes the back bias of the transistor 37,
Is varied. Gate 3 of transistor 37
8, a first voltage source 39 is connected, and a source 40 is connected to a second voltage source 39.
A voltage source 41 is connected, and a decoder or an operation unit 43 is connected to the drain 42. Then, the decoder or the arithmetic unit 43 performs decoding or arithmetic processing in response to a change in the threshold voltage of the transistor 37. still,
Reference numeral 35 denotes a substrate.

It is also possible to connect the gate 38 to the drain 42 and operate the transistor 37 in a saturation region instead of applying the voltage source 39 to the gate 38 of the transistor 37 independently. Further, even in a configuration in which the gate 38 is connected to the source 40, a change in threshold voltage can be detected.

FIG. 7 shows an example of the transmission units 9 and 13. The output of the encoder or the operation unit 45 is input to one end of the capacitor 46. The other end of the capacity 46 is connected to a well 48
It is connected to a tap 47 embedded therein. Capacity 4
The voltage fluctuation transmitted to the tap 47 via 6 is transmitted to another arithmetic unit (see FIG. 1) 2 via the well 48. The tap 47 usually uses the same type of diffusion as the well 48 but with a different concentration, but the well 48 and the tap 47 may be configured as p-type and n-type diodes to rectify. 49 is a substrate.

FIG. 8 is a block diagram of the transmitting units 9 and 13 shown in FIG.
Here is a different example. The output of the encoder or the arithmetic unit 50 is input to the current drive circuit 51 once. The output side of the current drive circuit 51 is connected to a tap 52 embedded in a well 53. Then, the current generated by the current drive circuit 51 flows from the tap 52 to the well 53, and changes the voltage of the well 53. The voltage fluctuation of the well 53 thus generated is propagated to another arithmetic unit (see FIG. 1) 2 via the well 53. Incidentally, 54 is a substrate.

By the way, at least one set of input control circuit and output control circuit is necessary for exchanging signals between the plurality of arithmetic units provided in one well and the outside as described above. Therefore, as shown in FIG. 9, a plurality of operation units 56 are arranged in a matrix at the center of one well 55 to form an operation unit array 57. Then, the input unit 58 and the output unit 59
Are arranged around the operation unit array 57 in the well 55, and the input control circuit 60 controls the input unit 58, while the output control circuit 61 controls the output unit 59.

In this case, by arranging the input unit 58 in parallel with one arrangement direction of the operation unit array 57 or the other arrangement direction, the input unit 5
The conditions such as the amplitude and the arrival time of the signal reaching the operation units 56 arranged in parallel to 8 can be made uniform, and a network configuration capable of performing two-dimensional weighting operation can be realized. The above network configuration can be applied to calculations such as image processing.

In FIG. 1, the semiconductor device is constituted by one well 1 in which a plurality of arithmetic units 2 are provided. The example shown in FIG. 10 relates to a semiconductor device in which a plurality of arithmetic units are provided in each of a plurality of wells.

In FIG. 10, a plurality of wells 65, 65 are provided.
In each of the plurality of arithmetic units 66 and at least one
A plurality of base stations 67 as transmission / reception circuits are provided, and the arithmetic units 66 and the base stations 67 are not connected to each other by wiring. Transmission information such as input / output (except for some basic signals for operating the operation unit 66 such as a power supply) of each operation unit 66 is transmitted to each well 6.
5. Therefore, the signal propagating in the well 65 is received by all the operation units 66 in the same well 65. The above is the same as the case of the semiconductor device constituted by one well 1 shown in FIG.

The difference is that the plurality of wells 65, 65
Is provided via a bus line 68. In the above configuration, the well 65
Is transmitted to the base station 67, selected, and transmitted to the bus line 68. Then, the signal transmitted to the bus line 68 is received by the base station 67 of another well 65 and selected as needed, and then, via the well 65 in which the base station 67 is mounted, the arithmetic unit 66 Is propagated to In general, by providing the bus line 68 with bidirectionality, a higher-speed operation can be performed. Note that the bus line 68 may be formed of a wiring layer formed on the same substrate as the plurality of wells 65,65.

With the above-described configuration, when a plurality of wells are mounted on one large well, it is possible to avoid signal delay and attenuation due to signal propagation in the large well. Further, the result of the operation performed in one well 65 is collectively transmitted to another well 65, or only the necessary operation result is selected from the result of the operation performed in each well 65. It is possible to realize the system functions such as performing.

FIG. 11 shows an example different from FIG. 10 in the semiconductor device having the plurality of wells. This semiconductor device includes a plurality of wells 71 provided with a plurality of arithmetic units 72 and one base station 73, and a well 74 provided with a plurality of arithmetic units 75 and two base stations 76a and 76b. Have. The one base station 76a in the well 74 and the base station 73a in the well 71a are connected by a bus line 77a, while the other base station 76b in the well 74 and the base station 73b in the well 71b are connected by a bus. They are connected by a line 77b.

In the above configuration, the plurality of wells 71a, 7
The calculation results by the calculation units 72a and 72b in the base station 1b are transmitted from the respective base stations 73a and 73b to the respective pass lines 77a and 7b.
It is transmitted to one well 74 via 7b. Thus, a parallel operation system having a hierarchical structure can be implemented. Note that the bus lines 77a and 77b may be formed of a wiring layer formed on the same substrate as the plurality of wells 71a and 71b.

FIG. 12 shows still another example of the semiconductor device having the plurality of wells. Multiple operation units 82a
The well 81a on which one base station 83a is mounted and the well 81b on which a plurality of arithmetic units 82b and one base station 83b are mounted are surrounded and disposed in another well 84. The well 84 plays the role of the bus line 68 in FIG.

In the above configuration, the base stations 83a, 83
b receives the signals from wells 81a and 81b, and
4 to the other base stations 83b and 83a.
Further, a signal transmitted through the well 84 is received, and a plurality of arithmetic units 82a and 82b are received through the wells 81a and 81b.
It is sent to.

It is desirable that the wells 81a, 81b and the well 84 be electrically separated from each other, so that each of the wells 81a, 81b, 84b is prevented from leaking current in the forward direction.
It is necessary to select the n-type and p-type and adjust the voltage value of the signal used for transmission and reception. Further, by making the base stations 83a and 83b as the transmission / reception circuits have bidirectionality, higher-speed calculations can be performed.

Next, FIG. 13 shows a configuration example for solving a Hamilton problem, a traveling salesman problem, and the like as an actual application example of the semiconductor device. In FIG. 13, a plurality of arithmetic units 86, 86,.
Corresponds to, for example, each bridge in the Hamilton problem and each city in the traveling salesman problem. The maximum number of bridges and cities is defined by the number of operation units 86. Bridges and roads connecting cities
It is not configured in hardware, and can be set arbitrarily by changing the storage contents of registers and memories described later.

An initial signal is transmitted to an input unit 88 mounted on the well 86 and connected to an input control circuit 87, and a bridge or a city to be started is designated by this signal. Then, each operation unit 86
As described in detail later, the received signal is transmitted to the well 86 again with appropriate information added thereto, and finally the output unit 8 is output.
When a desired signal (a signal giving a minimum distance solution) is obtained in step 9, the solution of the problem is output from the output control circuit 90 to the outside.

Now, each operation unit 86 in FIG.
FIG. 14 shows an example of the configuration of the arithmetic unit 86 used here in order to explain the operation of FIG. In FIG.
Whether the signal received by the receiving unit 91 and decoded by the decoder 92 is a signal to be received by the matched filter 93 or not (in the case of an actual Hamilton problem or traveling salesman problem, etc., Signal). For this purpose, a different code is assigned to each arithmetic unit 86, and the code is supplied from a code generator 94. The matched filter used here may be a circuit as disclosed in Japanese Patent Application No. 11-148445, for example. Here, if no matching is obtained by the matched filter 93, the signal is not a signal to be received, and the subsequent processing is not performed.

On the other hand, if a match is obtained by the matched filter 93, the operation proceeds to the inspection circuit 95, where the unit I
Own unit ID read from D register 96
, The same unit I is already included in the information of the received signal.
Check if D is not included (ie, has returned to the same bridge or city). Then, this unit ID is added to the received signal only when the inspection is passed, and is transmitted to the adder 97.

Here, the adder 97 and the memory 98 for storing distance information are unnecessary in the case of a general operation unit 86 for Hamilton problem, but the distance information between cities such as the traveling salesman problem is unnecessary. Use when is required. The distance information storage memory 98 stores an imaginary distance (inter-city distance in the traveling salesman problem) between the main operation unit 86 and another operation unit 86 connected by an imaginary road. . Then, the adder 97 reads the imaginary distance from the arithmetic unit 86 that has transmitted the received signal from the distance information storage memory 98, and adds the imaginary distance to the total number of distances so far to update the received signal.

Then, the updated reception signal is encoded by the encoder 99, and is transmitted as a new transmission signal to the transmitting unit 10.
From 0, it is transmitted to another arithmetic unit 86 via the well 85 (see FIG. 13). Then, when passing through all the arithmetic units 86 without duplication, it is transmitted to the output unit 89.

That is, the matched filter 93, code generator 94, check circuit 95, unit ID register 9
6, the adder 97 and the memory 98 for storing distance information constitute the arithmetic unit 7 in FIG.

In the above description, the CDMA (Code Division Multi-Dimensional Access) system is described as a communication system. However, the present embodiment does not particularly define the communication system, but uses TDMA (Code Division Multiple Access). Time-division multidimensional connection) method and F
A DMA (frequency division multidimensional connection) method may be used. When the number of the operation units 86 is limited, a simpler communication method other than the multiple access may be used.

FIG. 15 shows an example of the format of information carried on the transmission / reception signal. In FIG. 15, the contents of signals sequentially transmitted and received by the n arithmetic units 86 between time t1 and time tn are represented by binary numbers. The number to which d is added immediately above each binary number is represented by a decimal number so that the binary number can be easily understood.

Here, for example, the first 16 bits in the format of the information received at time tn,
The packet 101 stores the total number of distances. Also, the first packet 102 to the (n-1) th packet 106 every four bits after the 0th packet 101 store the number of the arithmetic unit 86 that has passed so far. Further, the last 4 bits, the n-th packet 107, include:
The number of the current arithmetic unit 86 is stored.

Then, based on the information having the above format, for example, the arithmetic unit 86 of the number “3”, which has received the signal at time t 1,
Of the first packet 102 (value 0
To indicate the end of data) to confirm that there is a connection with the arithmetic unit 86 of this number “12”. Furthermore, after confirming in the first packet 102 that there is no own number “3” in the number of the arithmetic unit 86 that has passed in the past, the own number “3” is added to the second packet 103.
Further, the number “12” is added to the total number of distances of the zeroth packet 101.
The distance (for example, 36 units) from the arithmetic unit 86 to itself is added and updated to “57 units”. The rewritten signal is as shown in the row at time t2, and is transmitted to the arithmetic unit 86 of the number "6" via the well 85.

Therefore, the output unit 89 refers to the contents of the 0th packet 101 in the format of the signal received from each arithmetic unit 86, and passes the signal exhibiting the minimum distance to the output control circuit 90 as a solution. Become.

FIGS. 16 and 17 show a configuration example different from FIGS. 13 and 14 for solving the Hamilton problem, the traveling salesman problem, and the like in the semiconductor device. 13 and 14 in that the arithmetic unit 86 is replaced by the arithmetic unit with delay 112 and the adder 97 is replaced by the delay circuit 127. This is to cause a delay corresponding to the magnitude of the distance in the transmission signal instead of adding the distance information from the distance information storage memory 128 as a value.

Therefore, in the information format in this example, the zeroth packet 101 storing the total number of distances in the format shown in FIG. 15 becomes unnecessary.
Then, the signal arriving at the output unit 115 first represents the solution of the shortest distance, and there is no need to select the solution of the minimum distance as in the case of the output unit 89 shown in FIG.

The well 111, the input control circuit 113, the input unit 114, the output control circuit 116, the receiver 121,
Decoder 122, matched filter 123, code generator 1
24, inspection circuit 125, unit ID register 126,
The encoder 129 and the transmission unit 130 correspond to the well 85, the input control circuit 87, the input unit 88, the output control circuit 90, the reception unit 91, the decoder 92, the matched filter 93, the code generator 94, and the inspection unit shown in FIGS. It has the same configuration as the circuit 95, the unit ID register 96, the encoder 99, and the transmission unit 100. The matched filter 123, the code generator 124, the check circuit 125, the unit ID register 126, the delay circuit 127, and the distance information storage memory 128 constitute the calculation unit 7 in FIG.

[0074]

As is clear from the above, the semiconductor device of the present invention has a plurality of arithmetic units mounted in the same well, and the input / output signals for each arithmetic unit are transmitted and received in the well. Therefore, it is not necessary to provide wiring for connecting the above-mentioned arithmetic units. Therefore, even if the number of the arithmetic units increases, it is possible to prevent an increase in device size due to an increase in wiring load and an increase in the number of wires, thereby realizing a larger-scale parallel arithmetic device. Further, since the signals transmitted and received between the arithmetic units propagate in the wells, radio interference as seen in general wireless communication does not occur, and a complicated transmitting and receiving circuit is unnecessary,
Power consumption can be reduced.

Further, in the semiconductor device according to the present invention, if a plurality of wells on which the plurality of arithmetic units are mounted are provided, and the plurality of wells are connected in parallel by a wiring layer, signal transmission between the plurality of wells is performed by the wiring. This can be done in layers, avoiding the extreme delay and attenuation of the signal that would otherwise occur in other wells. In addition, the operation results of each operation unit mounted on one well are collectively transmitted to other wells,
It is possible to realize a system function such as selecting only necessary operation results from the operation results transmitted from each well through the wiring layer. Furthermore, a higher-speed operation can be performed by giving the wiring layer bidirectionality.

Further, in the semiconductor device of the present invention, if a plurality of wells on which the plurality of arithmetic units are mounted are provided, and the plurality of wells are hierarchically connected by a wiring layer, the semiconductor device is mounted on one well located in the lower layer. The calculated operation results of each operation unit are transmitted together to the well located in the upper layer, and only the necessary operation results are selected from the operation results transmitted from each lower layer by the operation unit mounted on the upper layer well. And other system functions.

Further, the semiconductor device of the present invention is provided with a plurality of first wells on which the plurality of arithmetic units are mounted, and is electrically separated from the first well and the first well.
And a transmission / reception circuit for transmitting and receiving signals unidirectionally or bidirectionally between the first well and the second well, the plurality of wells may be connected in parallel or When there are many wiring layers to connect hierarchically,
The wiring layer can be eliminated. Therefore, it is possible to suppress an increase in device size due to an increase in wiring load and an increase in the number of wires, and it is possible to realize a larger-scale parallel processing device.

Also, the semiconductor device of the present invention has an input control circuit for inputting an external signal to at least one well,
If an output control circuit for outputting an internal signal from at least one well to the outside is provided, a signal can be transmitted / received to / from an external peripheral circuit or the like. Therefore, it is possible to perform synchronous driving with an external clock, externally specify an arithmetic unit that starts arithmetic or an arithmetic unit that completes arithmetic, and feedback an arithmetic result to the outside.

In the semiconductor device according to the present invention, the arithmetic units mounted on the wells to which the external signals are input are arranged in a matrix, and one of the two input units is arranged in the array matrix. If one is arranged in parallel with the arrangement direction and the other is arranged in parallel with the other arrangement direction, the amplitude, arrival time, etc. of the external signal reaching the operation units arranged in parallel with both input units Conditions can be aligned. That is, it is possible to configure a two-dimensional weighting calculation network applicable to calculations such as image processing.

Further, in the semiconductor device of the present invention, if the arithmetic unit is constituted by a receiving unit, a decoder, an arithmetic unit, an encoder and a transmitting unit, all the arithmetic units in which the receiving unit is connected to the same well are provided. After the calculation processing is performed in parallel, the calculation result can be output to the well again. Thus, it is possible to realize a neural network configuration in which all the arithmetic units are connected to each other.

Further, in the semiconductor device according to the present invention, if the arithmetic unit is constituted by a receiving unit, an arithmetic unit and a transmitting unit, the arithmetic unit is an analog circuit or the like and the conversion of a received signal is unnecessary. The configuration of the arithmetic unit can be simplified.
In this way, it is possible to realize an analog neural network configuration in which all the arithmetic units are connected to each other.

Further, in the semiconductor device according to the present invention, the arithmetic unit may be configured to determine whether the received signal should be fetched or not, and to determine whether the signal satisfies a desired rule. A circuit and an arithmetic unit for performing an arithmetic operation based on information in the signal, the inspection circuit inspects whether or not the signal satisfies the rule that the signal is the first signal taken into the arithmetic unit, and performs the arithmetic operation. Solves the problem of finding the one-stroke path and the shortest distance such as the Hamilton problem and traveling salesman problem by adding the distance to other arithmetic units connected on an imaginary road by a container to the total number of distances. Can be obtained at high speed.

Further, in the semiconductor device according to the present invention, the arithmetic unit may be configured to determine whether the received signal should be fetched or not, and to check whether the signal satisfies a desired rule. A circuit, a delay amount designating means for designating a delay amount of the signal, and a delay circuit for delaying the signal based on the designated delay amount. It is checked whether or not the signal rule is satisfied, and the delay amount designating means designates a delay amount corresponding to a distance to another arithmetic unit connected on an imaginary road, thereby transmitting the signal. The signal output from the unit to the well can be delayed by a time corresponding to the distance from the other arithmetic unit. Therefore, when finding the solution to the problem of finding the shortest distance such as the traveling salesman problem, it is not necessary to select the minimum value from the solutions of all the arithmetic units mounted on the same well, and the solution is first output to the well. The desired solution can be used as it is. That is, the calculation time and power consumption can be reduced.

Further, in the semiconductor device of the present invention, the receiving section includes a transistor, a gate of the transistor is electrically connected to the well, and one of a source and a drain of the transistor is connected to a voltage source. If the other is connected to the decoder or the operation unit, the voltage fluctuation of the signal propagated through the well is converted into a voltage fluctuation or a current fluctuation required by the subsequent decoder or the operation unit circuit. Can communicate.

Further, in the semiconductor device according to the present invention, if the transistor is formed in another well that is electrically separated from the well to which the gate is connected, the transistor may be changed due to a voltage change in the well. , And the voltage fluctuation of the well can be accurately converted by a voltage fluctuation or a current fluctuation required in the subsequent decoder or arithmetic circuit.

Further, in the semiconductor device of the present invention, the receiving section includes a transistor, one of a source and a drain of the transistor is connected to a voltage source, and the other of the source and the drain is connected to the decoder or the decoder. If the transistor is connected to the arithmetic unit and the gate of the transistor is connected to the voltage source or another voltage source, the voltage fluctuation of the signal propagating through the well can be regarded as the threshold fluctuation of the transistor, The above-mentioned decoder or arithmetic unit circuit can convert and transmit the required voltage fluctuation or current fluctuation.

Further, in the semiconductor device according to the present invention, the transmission section includes a capacitance-equivalent element having one electrode connected to the encoder or the operation section and the other electrode connected to the well. Then, the calculation result from the encoder or the calculation unit can be propagated to the well as voltage fluctuation.

Further, in the semiconductor device according to the present invention, the transmitting section may include a current drive circuit having an input terminal connected to the encoder or the arithmetic section and an output terminal connected to the well. The calculation result from the encoder or the calculation unit can be propagated to the well as a current fluctuation.

[Brief description of the drawings]

FIG. 1 is a plan view showing an example of a semiconductor device of the present invention.

FIG. 2 is a block diagram of an arithmetic unit in FIG.

FIG. 3 is a block diagram of an arithmetic unit different from FIG. 2;

FIG. 4 is a cross-sectional view of a receiving unit in FIG. 2 or FIG.

FIG. 5 is a sectional view of a receiving unit different from FIG. 4;

FIG. 6 is a cross-sectional view of a receiving unit different from FIGS. 4 and 5;

FIG. 7 is a cross-sectional view of a transmission unit in FIG. 2 or FIG.

FIG. 8 is a cross-sectional view of a transmission unit different from FIG. 7;

FIG. 9 is a plan view of a semiconductor device capable of transmitting and receiving signals to and from the outside;

FIG. 10 is a plan view of a semiconductor device having a plurality of wells.

11 is a plan view of a semiconductor device having a plurality of wells different from FIG.

FIG. 12 is a plan view of a semiconductor device having a plurality of wells different from FIGS. 10 and 11;

FIG. 13 is a plan view of a semiconductor device for solving a Hamilton problem, a traveling salesman problem, and the like.

FIG. 14 is a block diagram of an arithmetic unit in FIG.

FIG. 15 is a diagram illustrating an example of a format of information processed in FIG. 14;

16 is a plan view of a semiconductor device for solving a Hamilton problem, a traveling salesman problem, and the like different from FIG.

17 is a block diagram of an arithmetic unit in FIG.

[Explanation of symbols]

1,16,26,31,36,48,53,55,65,71,7
4,81,84,85,111 ... well, 2,56,66,7
2,75,82,86 ... arithmetic unit, 5,11,91,12
1 ... Receiving unit, 6,92,122 ... Decoder, 7,1
2, arithmetic operation unit, 8,99,129 encoder, 9,13,100,130 transmission unit, 15,
25, 35, 49, 54 ... substrate, 17, 27, 47, 52 ... tap, 18, 28, 37 ... transistor, 22, 2
9, 39, 41 ... voltage source, 23, 30, 43 ... decoder or operation unit, 45, 50 ... encoder or operation unit,
46: capacity, 51: current drive circuit, 57: arithmetic unit array, 58, 8
8, 114 ... input unit, 59, 89, 115 ... output unit, 60, 87, 113 ... input control circuit, 61,
90, 116 ... output control circuit, 67, 73, 76, 83
... Base stations, 68,77 ... Bus lines, 9
3, 123: matched filter, 94, 124: code generator, 95, 125: check circuit, 96, 126
... Unit ID register, 97 ... Adder,
98,128 ... Distance information storage memory, 1
12: arithmetic unit with delay 127: delay circuit

Claims (15)

[Claims] 1. A semiconductor device having a plurality of operation units mounted in the same well and transmitting and receiving input / output signals to and from each of the operation units in the well. 2. The semiconductor device according to claim 1, wherein there are a plurality of wells on which the plurality of arithmetic units are mounted, and the plurality of wells are connected in parallel by a wiring layer. 3. The semiconductor device according to claim 1, wherein there are a plurality of wells on which the plurality of arithmetic units are mounted, and the plurality of wells are hierarchically connected by a wiring layer. 4. The semiconductor device according to claim 1, wherein there are a plurality of first wells on which the plurality of operation units are mounted, and the first well is electrically separated from the first well and the first well is electrically connected to the first well. A semiconductor device comprising: a second well on which a well is mounted; and a transmission / reception circuit for transmitting / receiving a signal in one or two directions between the first well and the second well. 5. The semiconductor device according to claim 1, wherein: an input control circuit for inputting an external signal to at least one well; and an internal signal from at least one well to the outside. A semiconductor device comprising an output control circuit for outputting. 6. The semiconductor device according to claim 5, wherein the operation units mounted on the well to which the external signal is input are arranged in a matrix, and the number of the input units is two. One is arranged in parallel with one arrangement direction in the arrangement matrix of the operation units, and the other is arranged in parallel with the other arrangement direction in the arrangement matrix of the operation units. apparatus. 7. The semiconductor device according to claim 1, wherein the arithmetic unit is configured to receive a signal transmitted in the well, and convert the received signal into a form capable of arithmetic processing. A decoder that performs an arithmetic operation on the signal converted by the decoder, an encoder that converts the arithmetically processed signal into a transmittable form, and transmits the signal converted by the encoder into the well. A semiconductor device comprising a transmission unit. 8. The semiconductor device according to claim 1, wherein the arithmetic unit includes: a receiving unit that receives a signal propagated in the well; an arithmetic unit that performs arithmetic processing on the received signal; A semiconductor device comprising a transmission unit for transmitting the signal subjected to the arithmetic processing into the well. 9. The semiconductor device according to claim 7, wherein the arithmetic unit determines whether the received signal is a signal to be captured, and a determination circuit that determines whether the signal is a desired rule. A test circuit for checking whether or not the above condition is satisfied; and an arithmetic unit for performing an arithmetic operation based on information in the signal. 10. The semiconductor device according to claim 7, wherein the operation unit determines whether or not the received signal is a signal to be captured, and wherein the signal has a desired rule. An inspection circuit for inspecting whether or not the above condition is satisfied; a delay amount designating unit for designating a delay amount when delaying the signal; and a delay unit for delaying the signal based on the delay amount designated by the delay amount designating unit. A semiconductor device comprising a delay circuit for causing the semiconductor device to operate. 11. The semiconductor device according to claim 7, wherein the receiving unit includes a transistor, a gate of the transistor is electrically connected to the well, and One of a source and a drain is connected to a voltage source, and the other of the source and the drain is connected to the decoder or the operation unit. 12. The semiconductor device according to claim 11, wherein said transistor is formed in another well electrically separated from said well to which said gate is connected. Semiconductor device. 13. The semiconductor device according to claim 7, wherein the receiving unit includes a transistor, and one of a source and a drain of the transistor is connected to a voltage source. The semiconductor device, wherein the other of the source and the drain is connected to the decoder or the operation unit, and a gate of the transistor is connected to the voltage source or another voltage source. 14. The semiconductor device according to claim 7, wherein the transmitting unit has one electrode connected to the encoder or the arithmetic unit, and the other electrode connected to the well. A semiconductor device including a capacitor-equivalent element. 15. The current driving device according to claim 7, wherein the transmitting unit has an input terminal connected to the encoder or the arithmetic unit and an output terminal connected to the well. A semiconductor device comprising a circuit.