JP2001075814A - Device and method for compilation - Google Patents

Abstract

PROBLEM TO BE SOLVED: To effectively optimize an object code in the range satisfying limitation caused by the number of physical registers of a processor. SOLUTION: This compiler device performs code generation from a program represented by a DAG(directed acyclic graph) while evaluating the number of used registers and the number of execution cycles and optimizes a code to be generated. That is, the compiler calculates the number of cycles with which each operation can be executed on the DAG and the number of the currently available registers, performs code generation while preceding an operator on an execution path that takes the most time in the DAG in a part where the number of registers is sufficient, and performs code generation while preceding such an operator as to reduce the number of used registers when the number of registers is not sufficient.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compiling apparatus and method for compiling source code and generating optimized object code.

[0002]

2. Description of the Related Art For example, "Compilers -Principles, Te"
chniques and Tools-AV Aho, R. Sethi and JD Ull
man "," Principles of Compiler Design AV Aho and
JD Ullman "," Advanced Compiler Design Implementa
Conventionally, a compiler that compiles source code described in a high-level programming language and generates object code executable by a processor, as disclosed in literatures such as "Action, SS Muchnick", has been generally used. In addition, various optimizations of the object code generation processing have been conventionally performed on the compiler so that an object code that can be executed at a higher speed can be obtained.

In a compiler, when trying to optimize an object code generation process, a trade-off is often made between the scope of the optimization and the number of physical registers available for executing the object code. It must be made.

For example, in order to perform optimization by code scheduling, an interval between instructions having data dependency is increased to increase a filling rate of a pipeline of a processor,
The delay of the arithmetic unit in the processor must be hidden. In such a case, a temporary register is needed to store the plurality of values to be pipelined. Also, for example, a common subexpression (Common Subexpressi
In the case of omitting ons) and performing optimization to reduce the number of operations, a register for storing the calculated value of the common subexpression is required.

In the conventional optimization by a compiler, the optimization processing for elimination of common subexpressions, the register allocation processing for optimizing register allocation, and the code scheduling processing for optimizing code scheduling are implemented as separate paths. Was. Each of these optimization processing paths receives a processing result of another preceding optimization processing path as an input. As described above, the method of optimizing the processing results of all stages has a problem that, for example, the process of the previous stage may work in a direction that hinders the optimization process of the next stage. is there. For example, in the case where the number of registers used has increased as a result of the common subexpression deletion processing, when register allocation processing is performed next,
Register spill codes for saving and restoring register values may be generated unnecessarily.

There is also a possibility that the processing in the next stage is limited to the result of the processing in the previous stage. For example, even if the number of available registers is sufficient, if code scheduling processing is performed after register allocation processing, in the code scheduling processing, optimization is performed such that registers are renamed to conceal delays of arithmetic units. Gets harder.

[0007]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art, and provides code scheduling and common sub-expression elimination within a range that satisfies a constraint caused by the number of physical registers of a processor. Accordingly, it is an object of the present invention to provide a compiling device and a compiling method capable of effectively optimizing an object code. Further, the present invention provides a DAG (directed acyclic
From the source program expressed in (graph) format, object code is generated while evaluating the number of registers used and the number of hardware execution cycles, the scope of optimization by code scheduling and the elimination of common subexpressions, and the number of physical registers It is an object of the present invention to provide a compiling device and a compiling method that can optimally trade off with the constraints of the above.

[0008]

To achieve the above object, a compiling apparatus according to the present invention comprises a converting means for converting a source code of a program into a DAG format, and a converting means for converting the source code into a DAG format. Parameter calculating means for calculating a processor parameter for executing an object code corresponding to each of the included instructions by using a predetermined number of registers; and scanning the converted source code, based on the calculated processor parameter. A compiling unit for compiling the source code to generate an object code, wherein the parameter calculating unit calculates a timing at which the object code corresponding to each of the instructions is executed by the processor. Timing calculation means for performing Serial and a register decrease calculation means for calculating a numerical value indicating the register number of increase or decrease of the processor occupied when the object code corresponding to the instruction, respectively, are performed.

Preferably, the compiling means sequentially compiles each of the instructions according to the order of execution of the instructions in the converted source code and in accordance with the priority given to the instructions, and Object code generation means for generating an object code, and the number of registers of the processor occupied when each of the instructions which may be compiled next is executed based on a numerical value indicating increase or decrease of the number of registers Occupied register number calculation means for calculating the number of occupied registers indicating the number of open registers, and the instruction that may be compiled next based on the calculated number of open registers and the timing at which the object code of the instruction is executed And a priority assigning means for assigning a priority.

[0010] Preferably, the priority assigning means compares the calculated number of occupied registers with a predetermined threshold value, and when the calculated occupied register number is larger than a predetermined threshold value, Instructions that increase or decrease the number of occupied registers are given higher priority, and otherwise, instructions on the critical path are given higher priority.

Preferably, the compiling means is configured to generate an object code after deleting a common subexpression in the instruction, and the calculated occupied register number is smaller than the predetermined threshold value. In a case where the number of the common sub-expressions is large, an inverse transform unit for performing an inverse transform for restoring the deleted common subexpression is further provided.

Preferably, the apparatus further comprises data allocating means for allocating the register based on a predetermined constraint condition which restricts a use of a register of the processor.

[Operation of Compiler] The compiler according to the present invention provides an operator / instruction dependent DAG (directe
d acyclic graph), the code is generated while evaluating the number of registers used and the number of hardware execution cycles, and the application range of code scheduling optimization and common subexpression elimination and the restriction on the number of physical registers It is configured to optimize the trade-off between.

[0014] The compiler device according to the present invention comprises a DAG
The number of executable cycles of each operation is calculated above, and the number of registers that can be currently used when code is generated from the DAG is calculated. In areas where there is room for registers, DAG
, The code generation is performed with priority given to the operator on the execution path which takes the longest time, and the code generation is performed such that the pipeline filling rate of hardware is increased by increasing the number of registers used. In a part where the number of registers that can be used is small, code generation is performed with priority given to an operator that reduces the number of registers used, so that unnecessary spill code is not generated.
In addition, by performing the inverse conversion of the common subexpression deletion on the DAG during the code generation, it is possible to avoid the generation of useless spill codes due to the optimization.

[Compile method] The compile method according to the present invention provides a compile method in which a program
A conversion step of converting to a format, an object code corresponding to each of the instructions included in the converted source code, a parameter calculation step of calculating a parameter of a processor that executes using a predetermined number of registers,
Scanning the converted source code and, based on the calculated parameters of the processor, compiling the source code to generate an object code. Calculate the timing at which the object code corresponding to each of the instructions is executed by the processor, and calculate a numerical value indicating an increase or decrease in the number of registers of the processor occupied when the object code corresponding to each of the instructions is executed. I do.

[Medium] Further, a medium according to the present invention includes a conversion step of converting a source code of a program into a DAG format, and converting a predetermined number of object codes corresponding to instructions included in the converted source code into a predetermined number. A parameter calculating step of calculating a parameter of a processor to be executed using a register; scanning the converted source code; and compiling the source code based on the calculated parameter of the processor to generate an object code. A program for causing a computer to execute a compiling step, wherein in the parameter calculating step, an object code corresponding to each of the instructions calculates a timing to be executed by the processor; and an object code corresponding to each of the instructions. Mediating program for executing a process of calculating a numerical value indicating the register number of increase or decrease of the processor in the computer occupied when the Tokodo is executed.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] A first embodiment of the present invention will be described below.

[Summary of Compiler Shown as First Embodiment] A compiler according to the present invention first uses a DAG (direc
Calculates the number of execution cycles of the processor required to execute each operation included in the ted acyclic graph), generates object code from each operation included in the DAG, and uses it for each operation. Calculate the number of registers to perform.

[Code Generation] Further, when the number of registers required for executing the object code obtained as described above is small and the number of registers has a margin, the compiler according to the present invention requires the operation. The longer the execution time, the higher the priority of the order in which the processing is performed
An object code corresponding to the operation in G is generated, the number of registers used by the processor executing the object code is increased, and optimization is performed to increase the pipeline filling rate of the processor.

Conversely, if the number of registers is not large enough, the compiler according to the present invention increases the priority of the order in which the processing is performed as the number of registers required for the operation is smaller, and sets the priority in the DAG. Generates object code corresponding to the operation of (1), reduces the amount of code (spill code) that saves register contents in memory, and deletes common sub-expressions already generated at the time of object code generation. By canceling the optimization of and generating code, useless spill code is not generated.

For such optimization of the object code, the compiler according to the present invention evaluates the number of registers used by the operator and the number of cycles at which execution can be started when generating the object code from the DAG. When generating the object code, the code generation policy is changed based on the number of registers that change every time the code is generated. Dynamically changing from a policy of increasing the ratio to a policy of minimizing spill code by reducing the number of registers used and optimizing the elimination of common sub-expressions, restricting hardware and increasing the efficiency of object code And trade off.

As described above, the compiler according to the present invention determines the range of optimizing the object code as the number of physical registers of the processor, that is, the number of physical registers of the processor, among the operations included in the DAG. Limited to operations that are not subject to any restrictions. Further, when the processing of the compiler method according to the present invention is prepended to the register allocation processing and the code scheduling processing,
In order to optimize the object code, it is possible to alleviate the restriction on the part where these two processes must cooperate, so that the register allocation process and the code scheduling process are implemented as separate processing paths. Even so, the object code can be optimized.

[Method of Implementing Compiler Shown as First Embodiment] The compiler according to the present invention includes the following three steps for optimizing the object code described above.

[First Step] In the first step, the compiler according to the present invention expresses the source code in a DAG format representing the dependence of the operator on the data and the dependence on the side effect.

[Second Step] In the second step, the compiler according to the present invention uses hardware used for code generation, such as increasing or decreasing the number of cycles or the number of registers used, for each vertex of the DAG representing the source code. Calculate wear parameters.

[Third Step] In the third step, the compiler according to the present invention executes the above-described "code generation".
As shown in, the DAG is scanned to find the number of registers used,
A code is generated in consideration of an execution cycle to obtain an optimized object code sequence. In the third step, the compiler according to the present invention generates an object code while calculating the number of used registers during code generation, and determines the number of used registers at that time by a predetermined value (for example, an experiment or experience). When the number of registers used becomes smaller than the threshold, the number of used registers is reduced to minimize the spill code by changing the object code generation policy thereafter, that is, by increasing the number of registers used and increasing the pipeline priority ratio. Make changes to the policy and undo common subexpression elimination as needed.

As will be described later, the compiler according to the present invention calculates the number of registers that are not actually used, that is, the number of registers that are not occupied for executing the object code. The number and the number of unoccupied registers are equivalent and are merely differences in representation.

[Details of First to Third Steps] Hereinafter, the processing contents of the first to third steps of the compiler according to the present invention will be described in detail.

[Details of First Step] FIG.
FIG. As exemplified in Table 1 below, a source program including a loop is supplied with the dependency DAG shown in FIG.
(DAG is defined as the set of vertices and arrows in FIG. 1).

[0030]

[Table 1]

First, as described above, the compiler according to the present invention converts a source code (program: Table 1) into a DA code to be subjected to object code generation processing as follows.
Expressed in the form of G (FIG. 1). The compiler according to the present invention defines the operators (+, *, LOAD) in the program as vertices v∈V (each of the white circles in FIG. 1), and also depends on the definition and use of data between the operators. The dependencies to ensure that the relations and operations carry over (e.g., exceptions and writes to main memory) are triggered as described in the program, and the directed edge e = (V, w) ∈E (each arrow in FIG. 1)
And ignore the loop dependency,
A directed graph (DAG) without a cycle is represented by G = (V, E). The direction of the directed side e indicates the data dependency of each vertex (instruction or operator), and also indicates the execution order of the object code generated from each vertex included in the DAG.

Further, the compiler according to the present invention provides a virtual vertex top that precedes all vertices that do not have a vertex (preceding vertex) that is a source of a directed edge indicating a certain vertex, and a vertex that indicates a certain vertex. A virtual vertex bottom ┴ to be added to all vertices that do not have vertices (succeeding vertices) preceding the opposite side is added to the directed graph (DAG) G = (V, E).
Note that a directed edge (solid arrow in FIG. 1) indicating data dependence indicates that the operator uses the processor register when referring to the operation result of the preceding vertex. Are assigned the number of machine cycles cy (v) required to execute the above, and the compiler according to the present invention uses these pieces of information to generate a code in consideration of the execution cycle.

[Details of Second Step] Next, the compiler according to the present invention calculates, for each vertex of the DAG shown in FIG. 1, parameters used in code generation. Parameters that can be quantified from the graph structure. Information for optimization by code scheduling includes depth from the top, depth from the bottom, and slackness (slacknes).
s). Information on the number of used registers is reflected in the number of reference vertices. The depth lt from the top of a vertex v
(V), depth lb (v) from bottom, slackness s
l (v) and number of references (increase in number of references Δref (v))
Has the following meanings.

[Depth from Top] In the directed graph (DAG) G = (V, E) shown in FIG. 1, the depth from the top of a vertex v is determined by tracing the directed edge from the top ┬. It is defined as the maximum value of the cumulative addition value of the machine cycle of each vertex that passes before reaching the vertex v. In other words, the depth from the top refers to the maximum of the target architecture after the processor (target architecture) that executes the object code generated from the program represented by the DAG starts executing the top object code. The number of machine cycles after which the object code corresponding to the operator at the vertex v is executed.

When the DAG (FIG. 1) is scanned from the top ┬ by the depth-first search (reverse post-order), before scanning a certain vertex v, all the preceding vertices v must be read. Vertices are scanned. Therefore, a vertex v
Can be calculated in order from the vertex v close to the top に よ り by the following procedures 1-1 and 1-2.

Procedure 1-1: If a certain vertex v has no preceding vertex, the depth lt from the top of the vertex v
(V) = 0. Procedure 1-2: If a vertex v has a preceding vertex, the depth lt (v) from the top of the vertex v is represented by lt (v) = matrix with the vertex preceding the vertex v as the vertex p. x
(Lt (p) + cy (p)).

[Depth from the Bottom] The depth lb (v) from the bottom of a certain vertex v is defined as the direction from the bottom ┴ to the directed side of the DAG (FIG. 1) in the opposite direction. It is defined as the maximum sum of the machine cycles of the vertices to be reached before reaching. That is, the depth lb (v) from the bottom is
When executing object code generated from a program represented by DAG on a target architecture,
It indicates how many cycles before the execution of the object code corresponding to the operator of the vertex v has been started from the end of execution of all the object codes.

The depth lb (v) of the vertex v from the bottom is
Similar to the depth lt (v) from the top, a DAG with the directed side reversed is depth-first search from the bottom (reverse post
-order). The depth lb (v) from the bottom is, in order from the vertex v near the bottom ┴,
It can be calculated by the following procedures 2-1 and 2-2.

Procedure 2-1: If a vertex v has no successor vertex, lb (v) = 0. Procedure 2-2: If a vertex v has a successor vertex s, the depth lb (v) from the bottom = max (lb (s)) + sy (s).

[Slackness] The depth from the top to the bottom of the DAG (FIG. 1) is called the critical path length of the DAG. In other words, the critical path length indicates the minimum number of cycles it takes to execute the entire program represented by DAG. Critical path length is cp
(G), the slackness sl (v) of each vertex v
Is sl (v) = cp (G) -lt (v) -lb (v)
Is defined as That is, the slackness sl (v) represents a margin when the object code is generated.
The vertex v with slackness sl (v) = 0 is on the path (critical path) passing through the most directional edges from the top ┬ to the bottom through the vertex v.

Vertex v having large slackness sl (v)
Depends on the vertex v because slackness sl (v ') is lower in priority than vertex v' smaller than sl (v), and object code generation is postponed. It is unlikely that the generation of object codes for other vertices will be delayed.

[Increase in the number of references] Increase in the number of references Δref
(V) indicates the number of registers that have been used when the execution of the object code corresponding to the vertex v is started and can be released for new use, and the number of registers newly required. Is used to estimate The increase in the reference number of the vertex v Δref (v) is obtained by subtracting the number of the directed sides preceding the vertex v from the number of the directed sides succeeding the vertex v. Increase in reference number of vertex v Δref
The fact that the value of (v) is negative indicates that the use state of the register used for executing the object code corresponding to the preceding vertex is likely to end. Conversely, a positive value of the increase in the reference number Δref (v) of the vertex v means that the register that has not been used for executing the object code corresponding to the preceding vertex may be further used. Is higher.

[Details of Third Step] In the third step, the compiler according to the present invention uses the parameters (lt (v), l) calculated in the above-described second step.
b (v), sl (v), Δref (v)) to obtain D
Each vertex is scanned in order from the top # of the AG (FIG. 1) to generate an object code.

[Data Structure] During the generation of the object code, the compiler according to the present invention calculates the actual number of registers used and switches the object code generation policy. Note that the compiler according to the present invention executes the following data / lists a (G), r for executing the third step.
(G), u (G), reg, ap (v), au (v) are used, and these data / lists (data structures) are used for the (current) object code generation at each point in the object code generation process. Indicates the status.

A (G): a sequence of vertices for which an object code has already been generated, r (G): a sequence of vertices for which an object code can be generated next, u (G): an object code has yet to be generated Set of missing vertices, reg: number of physical registers of the target architecture currently available.

In the initial state before the generation of the object code is started, a (G) is an empty list, and r (G) is an empty list.
(G) becomes a list containing only the top ┬, and u (G)
Is a set containing all vertices except top ┬, and re
g is DA of the registers of the target architecture.
This is the number of registers that can be used to execute the object code generated from G (FIG. 1).

The following data structure indicates the state of each vertex for which the generation of the object code has not been completed.

Ap (v): the number of vertices preceding the vertex v in the DAG, for which the generation of the object code has been completed, and au (v): the vertex succeeding the vertex v via a directed edge. And the number of vertices for which object code generation has been completed.

The initial value of ap (v) is as follows in DAG:
This is the number of directed sides preceding vertex v, and the initial value of au (v) is the number of vertices succeeding vertex v via directed sides.

[Object Code Generation Algorithm]
The compiler according to the present invention performs the following procedures 3-1 to 3-8.
The object code is generated by the algorithm indicated by.

Procedure 3-1: The top vertex v of r (G) is extracted and added to the end of a (G). Procedure 3-2: For the directed side corresponding to each vertex s∈u (G) succeeding vertex v, change the value of ap (s) to ap (s):
= Ap (s) -1. Procedure 3-3: In procedure 3-2, if there is a vertex w that gives ap (w) = 0, it is added to r (G). Procedure 3-4: 4) Each vertex p @ a (G) preceding vertex v
, The value of au (p) is given by au (p): = au (p)
Update to -1. Procedure 3-5: Change reg value to reg: = reg + Δre
Update to g (v). Procedure 3-6: For each vertex v of r (G), calculate an increase Δreg (v) in the number of available registers. Procedure 3-7: If r (G) is not empty, rearrange the vertices of r (G) according to the priority and return to procedure 3-1. In other words, if r (G) is not empty and the number of currently available registers is larger than the threshold, according to the priority given by the following "when the number of available registers reg is larger than the threshold thr", The vertices of r (G) are rearranged, and when the number of registers currently available is smaller than the threshold, r (G) is given according to the priority given as shown in the following “when the number of available registers reg is less than or equal to the threshold thr” Are rearranged, and the procedure returns to the procedure 3-1. Procedure 3-8: If r (G) is empty, end the process.

It should be noted that the value Δreg (v) used in the above procedures 3-5 and 3-6 is obtained when the target architecture executes the object code corresponding to the vertex v of the DAG (FIG. 1). At the moment (current)
Indicates the number of registers of the target architecture that can be used. In other words, the value Δreg (v) is
Shows the number of available registers which increases when the object code of the above is executed.

The value Δreg (v) is given by Δreg (v) =
(The number of registers released by the execution of the object code of the vertex v) − (the number of registers reserved for the execution of the object code of the vertex v) and is released by the execution of the object code of the vertex v The number of registers is au of each vertex p preceding vertex v.
(P) = 1 is defined as the number of vertices giving 1, and the number of registers (registers required to store the value generated by the operator of vertex v) reserved for execution of the object code of vertex v is , 1 if vertex v produces a value in the register, 0 otherwise.

In the above procedure 3-7, the policy for aligning the vertices included in r (G) is changed depending on whether or not the currently available register number reg is larger than a predetermined threshold thr. Thereby, the policy of object code generation can be dynamically switched according to the restriction on the number of physical registers of the target architecture.

[The number of available registers reg is equal to the threshold thr
In the case of more than one) In order to generate object codes in order from the highest priority, a priority is given to each vertex included in the DAG (FIG. 1). When the number of available registers is larger than the threshold value (reg> thr), the compiler according to the present invention determines the priority according to the following rules a and b according to the compensation relation between the number of currently available registers and the threshold value. Give according to.

Rule a: Increase the priority of the vertex with the smaller slackness. Rule b: When the slackness is the same, the priority of the vertex having the smaller depth from the top is set higher.

In other words, the fact that the number of available registers is larger than the threshold value (reg> thr) means that there are sufficient available registers and there is room in the number, so that a vertex on the critical path in the DAG has a higher priority. An object code is generated by assigning a rank and optimizing by code scheduling by using many registers to conceal a delay of a computing unit.

[The number of available registers reg is equal to the threshold th
When the number of available registers is equal to or less than the threshold (reg ≦ thr), the compiler according to the present invention assigns priorities according to the following rules c to e.

Rule c: The priority of a vertex having a large Δreg (v) is set higher. Rule d: For vertices having the same Δreg (v), Δref
The priority of a vertex with a small (v) is increased. Rule e: If the priority is not determined by rules c and d, the priority is determined using slackness and depth from the top, as in the case where the number of registers is larger than the threshold.

The number of available registers is equal to or smaller than the threshold (reg)
≤ thr) indicates that the number of available registers is small and that there is no room, the registers are released as much as possible, the priority of vertices that are not newly secured is increased, and the object code is Generate. That is, the object code is generated by increasing the priority of a vertex that increases the number of available registers reg or a vertex whose value is not referred to by many vertices.

In order to assign such priorities, it is preferable to pre-read only one increase / decrease in the number of registers due to the next vertex to be generated from r (G). Although look-ahead may be extended for a plurality of vertex columns, it is necessary to trade off compile time and optimization effect because the number of combinations to be considered is increased. That is, the compiler according to the present invention determines the priority by calculating the increase or decrease in the number of registers when the next vertex to be generated is selected from r (G). Extending the algorithm to calculate the increase or decrease in the number of registers when a sequence of vertices is selected in sequence may provide a more desirable solution, but it is necessary to consider the trade-off between compile time and optimization There is.

When determining the priority order according to rule e,
The number of available registers is even smaller. In such a case, when the inverse transformation of common subexpression elimination is performed, the number of available registers reg can be increased. Since vertices for which object code has not been generated are represented by DAG, the compiler according to the present invention transforms DAG and performs inverse transformation.

[Inverse Conversion of Common Subexpression Deletion] The compiler according to the present invention performs the inverse conversion of common subexpression deletion according to the following procedures 4-1 to 4-3.

Procedure 4-1: From vertex p to r in a (G)
(G) and directed edge eεE stretched to vertex v in u (G). Procedure 4-2: directed side e = found in procedure 4-1
Among the vertices p preceding (p, v), a search is made for a vertex that can be calculated using only the value stored in the register at that time. Procedure 4-3: Duplicate the preceding vertex p to create a vertex p ′ (generate a vertex p ′ having the same operator, the same leading point, and the same successor as the preceding vertex p), and u (G) With this addition, the vertex preceding the directed side e = (p, v) is changed to e = (p, v). Note that common subexpression elimination is DA
On G, a plurality of vertices that generate the same value are represented by one vertex, and the succeeding vertex is dependent on the vertex. In procedures 4-1 and 4-3, one common vertex is deleted as a result. The inverse transformation of common subexpression elimination is performed by creating a vertex that generates the same value once again by generating a vertex that generates the same value at a plurality of vertices.

The value of au (p) is expressed as au (p): = au
When the value is updated to (p) −1 and the value of au (p) becomes 0, the number of available registers reg can be increased by one.
The reason that reg can be increased by one is that all vertices using the value of the preceding vertex have been code generated,
The preceding vertex value is no longer used. Therefore,
This is because one register can be released. That is, when the common subexpression is deleted on the DAG, a new data-dependent edge is introduced. When the common subexpression is deleted on the DAG, the value of the preceding vertex is shared by a plurality of succeeding vertices. Since the fact that a value is referred to is represented by an edge of the DAG, the compiler transforms the DAG to introduce a data-dependent edge. When the number of available registers is insufficient, an edge introduced by common subexpression elimination is selected, and inverse conversion is performed according to the above procedures 4-1 to 4-3. The optimization of the common subexpression elimination is canceled, and the optimization can be applied only to a portion where the number of available registers has room.

[Specific Example of Optimization by Compiler According to the Present Invention] As a specific example, the compiler according to the present invention is repeatedly executed from a source program (Table 1 above) in a loop body (in a program). A DAG (FIG. 1) is generated from the DAG, and a processor manufactured by Intel and others (x86 architecture) and a processor manufactured by Motorola (Pow) are generated from the DAG.
(erPC architecture) as a target architecture, a description will be given of the result of code generation with respect to the optimization result when these processors generate executable object code.

In the source program (Table 1), i and n indicate integer variables, and t1 to t8, x1 to x
Reference numeral 4 denotes a floating-point variable, and a [i] represents an array access and corresponds to a load instruction of the target architecture. For the sake of simplicity, the operation of the compiler according to the present invention will be described below focusing only on the code generation of instructions using a floating-point number register and an arithmetic unit.

As described above, the source program exemplified in Table 1 can be represented by DAG shown in FIG. In this DAG, the directed side of the solid line connecting the vertices represents the dependence of the data during the operation, and the directed side of the dotted line represents the dependence in the order of the side effects. Here, if the order of the side effects of the memory access must be maintained from the programming language model, the variables x1 to x4 refer to values from outside the loop, and the values are changed in the next execution of the iteration. Keep the value between iterations of the loop because it is referenced. Therefore, each of these variables x1 to x4 occupies one floating-point number register. Therefore, when the generation of the object code of the loop body of the source program starts, four registers are used.

[X86 Architecture] Hereinafter, the x86 architecture in which code generation is performed under the condition that the number of registers is smaller than the threshold will be described. In the x86 architecture, when a register is used as an operand, the cycle number of a load instruction of a floating-point number, a multiplication instruction, and an addition instruction is one. Depth lt from top of each vertex
(V), depth lb (v) from bottom, slackness s
The compiler according to the present invention calculates l (v) and the increase Δref (v) of the number of references as shown in Table 2 below.

[0070]

[Table 2]

The x86 architecture has eight floating point registers. Since it is known that four registers are occupied in the entire loop, the number of registers available in the initial state is four (= 8−4). Now, if the threshold thr for switching the code generation policy is set to, for example, 2, the initial state is expressed as shown in Table 3 below.

[0072]

[Table 3]

In the above-described data structure, the compiler according to the present invention is capable of generating a code in the next sequence of vertices r (G)
When the top オ ブ ジ ェ ク ト is extracted and the object code of the top ┬ is generated, the vertex 3 is added to r (G), and ap (3) = 0 according to the procedure 3-2.
Is generated, the vertex 2 is added to r (G) because ap (2) = 0 according to the procedure 3-2). When the compiler according to the present invention generates an object code from vertex 2, vertices 1 and 7
(G).

Up to this point, since there is only one vertex for which object code can be generated, either one of the above-mentioned policies (when the number of available registers reg is larger than the threshold thr) and when the number of available registers is reg Is the threshold th
The same order is applied in the case of “if r or less”. When the object code is generated from the vertex 2, the number of registers currently available becomes reg = 2. Therefore, a code generation policy that minimizes the number of registers is selected.

That is, Δreg (1) = + 1, Δreg
(7) = + 1, and the register occupied by one increases even if any of the vertices 1 and 7 is selected.
From (1) = + 2, Δref (7) = − 1, the priority of vertex 7 is set higher according to rule d, and the data structure is as shown in Table 4 below (rules c, d, e).

[0076]

[Table 4]

When the compiler according to the present invention generates the object code from the vertex 7, the vertex 11 is added to r (G), and Δreg (11) = − 1, Δreg (1) =
The priority of the vertex 11 is set higher than +1 and the data structure is as shown in Table 5 below (rule c).

[0078]

[Table 5]

When the compiler according to the present invention generates an object code from vertex 11, reg = 2, and only vertex 1 remains in r (G) (procedure 3-2). When the compiler according to the present invention performs the same optimization in the following, the data structure is finally as shown in Table 6 below.

[0080]

[Table 6]

[PowerPC Architecture] Next,
A PowerPC architecture in which vertices on the critical path are preferentially code-generated will be described. Po
The number of cycles for loading, multiplying, and adding a floating-point number in the warPC architecture is 1, 2, 1, respectively. Accordingly, the compiler according to the present invention provides a depth lt (v) from the top of each vertex v, a depth lb (v) from the bottom, slackness sl (v), and an increase in the number of references Δref.
(V) is calculated as shown in Table 7 below.

[0082]

[Table 7]

Here, similar to the x86 architecture,
Threshold thr for switching object code generation policy
Is set to 2. Since the PowerPC architecture has 32 floating point number registers, the value of reg of the data structure is 28 (= 32−4) in the initial state. As in the case of x86, the compiler according to the present invention generates object codes from vertices 3 and 2 from the initial state (procedures 3-1 to 3-8).

When the object code is generated from the vertex 2, the value of reg becomes 30. Therefore, the compiler according to the present invention uses the slackness sl (v) and the depth l from the top.
An object code generation policy that prioritizes t (v) is selected (see processing from when the number of available registers reg is larger than the threshold thr to rules c to e). Slackness sl (1) = 0, sl (7) = 3 for each of vertices 1 and 7
Thus, vertex 1 is given a higher priority, and the data structure is
The results are as shown in Table 8 below (refer to the above-described process of “calculating the actual number of used registers and switching the object code generation policy”).

[0085]

[Table 8]

The compiler according to the present invention similarly operates
Generate object code for one load instruction. With the object code of the load instruction of vertex 0 generated, the object codes of vertices 4, 5, 6, and 7 can be generated next. Here, the slackness of each of the vertices 4, 5, 6, and 7 is sl (4) = 0, sl (5) = 0,
Since sl (6) = 1 and sl (7) = 3, vertices 4 and 5 are assigned high priority, and object codes are generated from vertices 4 and 5 before vertices 6 and 7, and the data structure is And Table 9 below (procedures 3-1 to 3-8).

[0087]

[Table 9]

Similarly, the slackness values of the vertices 8, 9, 10, and 11 are sl (8) = 0 and sl (9) =
Since 0, sl (10) = 1 and sl (11) = 3, the data structure finally becomes as shown in Table 10 below.

[0089]

[Table 10]

[Delay concealment of operator with long delay time]
As described above, when the PowerPC architecture is the target architecture, the multiplication delay time is two machine cycles. Here, if there is an operator on the critical path that greatly increases the delay time of the arithmetic unit of the target architecture, giving priority to a vertex with small slackness wastes the waiting time for executing an instruction on the critical path. Sometimes.

In order to improve such a state, the compiler according to the present invention performs
Calculates the execution start time of each vertex, and if there is a vertex with a large slackness with respect to the waiting time of the instruction on the critical path, if there is a vertex with an earlier execution start time, the priority is increased and the object is set. It may be configured to perform code generation.

The processing of the compiler according to the present invention in such a configuration will be described below. The time ct at which the latest code was issued when the object code was generated
(Maximum value of code generation time until now)
Further, during the object code generation, a vertex v is generated for the vertex v for which the object code has not yet been generated (the vertex v belonging to r (G) during the code generation from the DAG). Rt (v) is calculated. However, in this case, the initial values at the time of starting the object code creation at time ct and rt (v) are set to 0.

When the object code of the vertex w is generated, the value of the time ct is changed to ct:
= Rt (w). In procedure 3-3, time r
The value of t (w) is set as rt (w): = ct + cv (v). In order to perform the delay concealment of the operator, the slackness sl (v) and the depth l from the top are determined according to the rules a and b.
In the code generation policy in which t (v) is prioritized, rt (v) may be generated prior to slackness. When rt (v) is the same, priority is given to slackness and depth from the top.

[Effect] In the case where an object code is generated from a source program represented by a tree without a common subexpression, see Sethi, R. and JD Ullman, "T
he generation of optimal code for arithmetic expre
ssions ", J. ACM 17: 4, 715-728. Algorithms have been developed to minimize the number of registers used for intermediate variables.
C. Johnson, "Optimal code generation for expressio
In order to cope with an architecture having a complicated instruction set, an algorithm using dynamic programming has been developed as disclosed in J. ACM 23: 3, 488-501. Each of these algorithms is devised so as to minimize only the number of used registers.

However, as described above, there is a trade-off between minimizing the number of registers used and optimizing the object code for hiding the operation delay time and reducing common sub-expressions. Exists. The compiler according to the present invention can calculate this trade-off at the time of generating the object code from the DAG and dynamically change the optimization policy, so that the optimization can be performed without hindering other code optimization. It is superior to the algorithm developed by Seti et al. In that the applicable range can be limited to a portion permitted by the restriction on the number of registers that can be used.

[Second Embodiment] A method of optimizing an object code by devising register allocation will be described below as a second embodiment of the present invention. Register allocation is one of the most important ways to improve the performance of the object code chosen as a result of compilation, but many treat all registers symmetrically. However, the handling types of all registers are not equivalent, and there is actually an asymmetry in register usage based on machine specifications and object code generation practices. If register allocation is performed without considering this restriction, instructions for moving registers between registers will be generated in vain when object code is generated, and the performance of the object code selected as a result of compilation may be greatly reduced. is there.

In the optimization processing shown as the second embodiment of the present invention, information on a specific use of a register is propagated from back to front of the intermediate code by solving a data flow equation, and will appear in the future. The usage constraint of a specific register is satisfied in advance, and when a register is assigned to a variable constituting a Web (a definition / use chain of a certain variable and a linked set by use / definition chain), the Web, that is, the connection is established. This register is propagated to the members of the set, and the future use of the specific register is determined in advance. Thereby, register movement for satisfying the register constraint is reduced, and high-quality object code without waste can be generated.

The compiler according to the present invention shown as the second embodiment prepares a field (hereinafter referred to as a constraint description field) that can describe a desired register in an element that requires register allocation of each instruction in the intermediate code used for the compiling process. Then, a constraint description field is described in accordance with the properties of the target machine. The constraint description field is prepared with two types, one that describes a strong constraint and one that describes a weak constraint.

Next, weak constraints are described for each instruction of the intermediate code based on the specifications of the machine. The constraint includes a dedicated register used for a specific operation, a function argument passed through the register, and the like. In particular, the present invention considers that variables that survive a function call should be placed in nonvolatile registers, and refers to variables as many as the number of nonvolatile registers that are referred to earliest after a function call. The constraint corresponding to the non-volatile register is described in the instruction.

After describing the weak constraints in each instruction, these constraints are propagated backward from the use of data to the definition. Here, the term “propagation” specifically refers to copying information (here, a weak constraint) in an object code in which data is used to an object code in which data is defined. As a result, it becomes clear what kind of register constraint the variable definition in a certain instruction will be referred to in the future. At the same time, a constraint that is a complement of the constraint is described in a variable whose live range overlaps with a variable having a constraint, and propagation is similarly performed.

Thus, it is possible to avoid a situation in which a register having a constraint is already allocated to another variable at the time of obtaining the register with the constraint. After preparing a function for performing the above propagation in the basic block, the data flow equation is solved. By the above operation, the weak constraint is propagated throughout the intermediate code beyond the basic block.

Thereafter, the intermediate code is scanned from front to back, and registers are allocated based on the described constraints. At this time, the register assigned to the variable being defined is propagated as a strong constraint to the entire Web to which the definition of the variable belongs while following the definition / use chain and the use / definition chain of the variable. Here, the Web is
It refers to a connected set by the DU-UD-chain for the same variable.

As a result, there is a high possibility that the same register is allocated to a variable belonging to each Web. Particularly, when the definition of the variable is merged at the junction of the basic blocks, the transfer instruction between the registers is guaranteed. Can be avoided. This operation is performed only once for each Web.
When a register is assigned to a variable on b, no propagation is performed.

Further, when determining the initial value (initial cache set) of the register mapping, the weak register constraint solved by the data flow equation is reflected, and the variables which have already been in the registers from the beginning are referred to by those variables. At times, useless inter-register transfer instructions are prevented from being generated.

In the interference graph coloring algorithm generally adopted by a static compiler,
Methods have been developed to reflect register constraints. However, this method has the following problems. In this method, a node representing a physical register is added to the interference graph,
It is possible to express the register constraint passively by causing the register and the variable to interfere with each other. For example, to assign a variable a to the register r1, a node representing r1 and a
Interference may be given to nodes representing variables other than. However, since this method can only describe passively, the description of the constraint becomes weak when a plurality of variables are assigned to one register.

Further, since the temporal context is compressed in each node, when a certain variable has a different context and a different constraint, the constraint cannot be described. Further, there is a problem that the number of interferences required to represent the register constraint becomes enormous.

[Compiler Shown as Second Embodiment]
The compiler (Java) shown as the second embodiment of the present invention
a Just-in-Time compiler) will be described.

The compiler according to the present invention performs processing using the intermediate code at the register transfer level. That is, each instruction is a destination, a source (plural)
(Virtual register) and an operation code. Each variable in the instruction is assigned a register by the register allocator. Compiler according to the present invention, for these variables, prepare a bit field to represent a physical register available in the target machine as ancillary information, the bit of the register is preferably obtained by the method described below Stand up.

This field prepares two types, one in which a strong constraint is described and one in which a weak constraint is described. The register allocator follows the basic blocks in depth-first order, and allocates registers while scanning instructions in each basic from the front to the back. At the time of register assignment, if a bit indicating a strong constraint is set in a variable to which a register is to be assigned, the register is preferentially assigned. If the register has already been used, allocate the register based on weak constraints. If the register is used, another register is allocated.

In this method, a register cache set is determined for each loop, and registers are replaced at the entrance of the loop. Here, the variables that should be in the registers in advance are the variables of the physical registers that are first referred to from the entrance of the loop. Registers are initially allocated to these variables. At this time, the register constraints propagated at the entry of the loop are reflected.

[Description of Constraints] First, constraints on function calls will be described.

[Restriction on Argument of Function] In the compiler according to the present invention, a part of the argument is placed in a register at the time of calling the function, so that the processing is speeded up. Which argument rides on which register is predetermined by calling convention, which is a constraint when allocating registers to variables. In this example, among the source variables of the instruction for performing the function call, a bit corresponding to the register defined by the calling convention is set in a field of a value to be passed on a register.

[Restriction on Return Value of Function] In the compiler according to the present invention, the return value is placed in a register when returning from the function, so as to speed up the processing. Since the register to which the return value is put is determined by custom, there is a restriction when assigning a register to a variable to be a return value. In this example, a bit corresponding to a register determined by custom at the time of return is set in the field of the source variable of the instruction to perform the return.

[Restriction on Variable Surviving Beyond Function] In the compiler according to the present invention, the register alive at the time of calling the function is saved as needed on the called side (Callee). Therefore, there is a kind of restriction that it is better to put a variable that survives beyond a function on a nonvolatile register. In this example, a bit corresponding to the nonvolatile register is set in the source field of the instruction that uses the variable of the nonvolatile register that is referred to the earliest after the function call occurs. The variable that is referred to earliest after a function call can be determined using data flow analysis.

[Restriction on Specific Operation] There is a restriction that a specific register must be used in multiplication, division, shift instruction and the like. In this embodiment, a bit corresponding to a register defined in the machine specifications is set in a field of a source variable of an instruction that requires the use of a specific register.

[Propagation of Constraints] Propagation of constraints in the compiler according to the present invention will be described below.

[Static Constraint Propagation (Propagation of Weak Constraints)] For each basic block, an array representing the register constraints of each variable is prepared at the entrance and exit. In each basic block, the initial register constraint of each variable is set to the array of the exit of the basic block, the instruction is scanned from bottom to top, and the described constraint is propagated from the use of the variable to the definition, and the weak constraint description field of the variable is set. I will describe it.
In addition, a constraint that is a complement of the constraint is described in a variable whose live range overlaps with the variable having the constraint, and propagation is performed similarly. Stores the propagated result in the array of basic block entrances, and calculates the logical product of the array of exits of a basic block = the array of entrances of all basic blocks arriving from the basic block based on the connection state of the basic blocks The constraint array is scanned using the exit array as a new initial value. The above is repeated until the change in the outlet arrangement is saturated.

[Propagation of Constraints During Register Allocation (Propagation of Strong Constraints)] During register allocation, a Web having two or more definitions
When the register acquisition is performed for the variable that configures the instruction, the link following the instruction is linked to another Web.
Is detected as a constituent variable. The obtained register is written in the strong constraint description field of this variable. If there is no restriction on the register acquisition target, operate the Web to detect the restriction attached to other definitions, and try to acquire the register based on this restriction. This operation is performed only once for each Web, and when a register is assigned to a variable on the Web that has already been processed, propagation is not performed.

[Third Embodiment] Hereinafter, as a third embodiment of the present invention, a method of implementing the compiler for optimizing the object code shown in the first embodiment and the second embodiment will be described.

[Computer System] FIG. 2 is a diagram showing a configuration of a computer system for realizing the compiler according to the present invention shown in the first embodiment and the second embodiment. As shown in FIG. 2, the computer system includes a Java development environment 1 including a Java compiler, a medium 5 such as a network or a recording medium, and a client device 6.

The client device 6 includes a microprocessor including a predetermined number of registers, arithmetic circuits, and a pipeline mechanism, a memory such as a RAM and a ROM, peripheral circuits, and a storage device such as a hard disk device and a removable disk device. (Not shown). This hardware 13
Is a JavaVM (Java Virtual Machine) 7 and
Windows (trade name of Microsoft Corporation), OS2
An operating system (OS) 12 such as (IBM product name) and MacOS (Apple product name) is loaded from a recording medium to a memory and executed. JavaVM7
Includes a Java bytecode verification unit 8, a Java interpreter 9, and a JavaJIT compiler 10.

[Java Development Environment 1] In the Java development environment 1, the Java compiler 3 compiles the Java source code 2 created in advance, and
Generate a byte code 4. The generated Java bytecode 5 is recorded on a network or in a recording medium and sent to the client device 6 via the medium 5. The Java bytecode 4 is an expression format of a Java program that can be executed regardless of computer hardware and an execution environment.

[Client Device 6] The client device 6 converts the Java bytecode 4 supplied from the Java development environment 1 via the medium 5 into a WWW browser, WWW
It is executed by the Java VM 7 such as a server.

[Java Bytecode Verification Unit 8] In the client device 6, the Java bytecode verification unit 8
Verifies the bytecode of the Java bytecode 4 sent from the Java development environment 1 to the client device 6 via the medium 5, determines whether the specification of the Java bytecode is satisfied, and satisfies the specification. in case of,
Output to the Java interpreter 9 and the JIT compiler 10.

[Java interpreter 9] The Java interpreter 9 executes the Java bytecode input from the Java bytecode verification unit 8 by an interpreter method.

[JIT Compiler 10] The JIT compiler 10 converts the machine code (object code) 11 that can be executed by the hardware 13 to execute the Java bytecode input from the Java bytecode verification unit 8 at high speed. Let it run.

[Operation of Computer System] The operation of the computer system shown in FIG. 2 will be described below with reference to FIGS. FIG. 3 is a flowchart showing the operation of the JIT compiler 10 shown in FIG. FIG.
5 is a first flowchart showing the intermediate code optimization processing (S17) shown in FIG. FIG. 5 is a flowchart showing the intermediate code creation processing (S26) shown in FIG. FIG. 6 is a flowchart showing the process of creating the intermediate code from the DAG shown in FIG. 5 (S30). FIG.
7 is a flowchart showing a vertex string alignment process (S37) shown in FIG. FIG. 8 is a second flowchart showing the intermediate code optimizing process (S17) shown in FIG. 3, and shows a process subsequent to the process shown in FIG. FIG. 9 shows FIG.
9 is a flowchart showing a code generation / register allocation process (S18) shown in FIG.

In the Java development environment 1, the Java compiler 3 generates a Java bytecode 4 from the Java source code 2 and sends it to the client device 6 via the medium 5. In the client device 6, Java
The Java bytecode verification unit 8 of the aVM 7
Bytecode 4 is received, Java bytecode is verified, and Java bytecode 4 that meets the specifications is
Output to the compiler 10.

As shown in FIG. 3, step 14 (S1
In 4), the JIT compiler 10 (FIG. 2)
From the Java bytecode verification unit 8 to the Java bytecode 4
Receive. In step 15 (S15), JIT
The compiler 10 converts the Java bytecode 4 into an intermediate code format and generates an intermediate code (S16). This intermediate code (S16) is in an expression format that is easily analyzed and deformed by the JavaJIT compiler, that is, a format in which instructions for reading a variable value, performing an operation, and writing a result to a variable are arranged in order. Has become.

In step 17 (S17), the JIT
The compiler 10 performs an optimization process (FIG. 4 to FIG. 4) on the intermediate code (S16) generated in the process of S15.
Perform 8).

As shown in FIG. 4, in step 23 (S23) of S17 (FIG. 3), the JIT compiler 10
(FIG. 2) converts the intermediate code into a DAG (FIG. 1) format to generate an intermediate code DAG (S24). As described above, the intermediate code DAG (S25) is expressed as a directed graph in which the intermediate code has an operator as a vertex and a dependency of data used for the operation as an edge.
The T compiler 10 performs optimization processing such as deletion of the common subexpression on the intermediate code DAG (S25).

In step 26 (S26), the JIT
The compiler 10 generates the intermediate code again by arranging the operators of the intermediate code in order so as to satisfy the constraint expressed by the intermediate code DAG (S25). Note that the constraint expressed by the intermediate code DAG means that the directed side of the DAG represents the order constraint of the original intermediate code.

As shown in FIG. 5, in step 29 (S29) of S26 (FIG. 4), the JIT compiler 10
FIG. 2 shows parameters (lt, l) used for object code generation for each vertex of the DAG (S26).
b, sl, △ ref) (see “Details of the second step” above).

In step 30 (S30), the JIT
The compiler 10 calculates the number of used registers of the generated intermediate code, and generates the object code while dynamically changing the policy for generating the intermediate code (procedure 3-1 to procedure 3-1).
3-8).

As shown in FIG. 6, in step 33 (S33) of S30 (FIG. 5), the JIT compiler 10
(FIG. 2) shows a column r of vertices from which object code can be generated.
(G) is initialized (procedures 3-1 to 3-8 described above). That is, the JIT compiler 10 adds the top ┬ to the row of vertices for which the object code can be generated.

In step 34 (S34), the JIT
The compiler 10 extracts the top vertex of the vertex sequence r (G) in which the object code can be generated and adds it to the end of the vertex sequence a (G) in which the object code is generated (procedure 3-1 and 3-2). .

In step 35 (S35), the JIT
The compiler 10 adds the vertex for which the object code can be newly generated to the column of the vertex for which the object code can be generated by the process of S34 (procedure 3-
3).

In step 36 (S36), the JIT
Compiler 10 terminates the process when the column of vertices for which object code can be generated becomes empty, and otherwise proceeds to the process of S37 (procedure 3-8).

In step 37 (S37), the rows of vertices for which object codes can be generated are arranged in accordance with the (current) object code generation policy at that time.
The process returns to S34 (procedure 3-7).

As shown in FIG. 7, in step 40 (S40) of S37 (FIG. 6), the JIT compiler 10
(FIG. 2) calculates the number of registers changed by the generation of the object code in the process of S34 (procedure 3-).
5).

In step 41 (S41), if the number of available registers is 0, the process proceeds to S42, otherwise, the process proceeds to S43. That is, S41
In, the condition for determining the inverse transformation of the common sub-expression is determined.

In step 42 (S42), the JIT
The compiler 10 is a vertex of the DAG for which no object code has been generated.
If there is a vertex at which the number of available registers of the hardware 13 increases, inverse transformation is performed on the vertex (procedure 4-1 to procedure 4-1).
4-3).

In step 43 (S43), the JIT
The compiler 10 determines whether or not the number of registers of the hardware 13 that can be used at that time is larger than a predetermined threshold. If the number is larger, the process proceeds to S44. Proceed (procedure 3-7).

In step 44 (S44), the JIT
The compiler 10 determines that the available registers are sufficient in number, and generates the object code by giving priority to the vertices on the critical path of the DAG so that the parallelism of the object code is high.

In step 45 (S45), the JIT
The compiler 10 determines that the number of available registers is low, and calculates a parameter (△ reg) such as an increase or decrease in the number of available registers for each vertex included in the column of vertex where the object code can be generated, Priority is given to vertices that increase the number of available registers.

Following the processing shown in FIG. 7, as a continuation of the processing in S17 shown in FIG. 3, the JIT compiler 10 transmits the weak register constraint shown in FIG. 8 and the Web having two or more definitions as shown in FIG. To detect. As shown in FIG. 8, in step 48 (S48), the JIT compiler 10
(FIG. 2) describes the weak constraints to be propagated in step 49 for each instruction in the intermediate code (S16 in FIG. 3). That is, the JIT compiler 10 describes weak constraints on each instruction of the intermediate code based on the specifications of the machine and the like.

In step 49 (S49), the JIT
The compiler 10 propagates the weak constraint described in the processing of S48 from the use of data to the definition. That is, the JIT compiler 10 propagates the constraint backward from use of data to definition.

In step 50 (S50), the JIT
The compiler 10 detects a linked set of definitions and uses for a certain variable (Web) while using information on data definitions and usage chains. Particularly, in this step, a Web having two or more definitions is detected. That is, the JIT compiler 10 scans the intermediate code from the front to the back and allocates registers based on the described constraints.

Referring again to FIG. Step 18 (S
In 18), the JIT compiler 10 performs register allocation and object code generation for each instruction in the intermediate code.

As shown in FIG. 9, in step 53 (S53) of S18 (FIG. 3), the JIT compiler 10
(FIG. 2) determines whether or not register allocation and object code creation are completed for each element of the intermediate code (each instruction in the intermediate code), and when these are completed, the object code (S20; Figure 3) is generated and S2
Then, the process proceeds to S54. Otherwise, the process proceeds to S54. That is, the end condition is that code generation and register allocation are repeated from the first instruction to the last instruction in the intermediate code.

In step 54 (S54), the JIT
The compiler 10 performs register allocation and object code generation for each element of the intermediate code.

In step 55 (S55), the JIT
The compiler 10 propagates the register allocated in the processing of S54 to the Web having two or more definitions as a strong constraint. In other words, JIT compiler 10
Traces the register allocated to the variable used in a certain instruction to the Web in which the variable is included. Since the Web is a set of definitions and uses, there is a strong restriction on all the definitions and uses of the instructions that make up the element. Describe.

In step 56 (S56), the JIT
The compiler 10 extracts the next element (instruction) of the intermediate code to be processed. S19 is obtained in S57.

Reference is now made to FIG. Step 21 (S
21; in FIG. 3), the JIT compiler 10 (FIG. 2)
Performs a code schedule process to generate an object code (machine code 11; FIG. 2) that can operate at high speed.

[0155]

As described above, according to the compiling apparatus and method of the present invention, object scheduling is performed by code scheduling and common sub-expression elimination within a range that satisfies the constraint caused by the number of physical registers of the processor. It can be optimized effectively.

According to the compiling apparatus and the compiling method of the present invention, a DAG (directed acyclic graph) is provided.
Generates object code from the source program expressed in the format while evaluating the number of registers used and the number of hardware execution cycles, the scope of optimization by code scheduling and the elimination of common subexpressions, and the restrictions on the number of physical registers Can be optimally traded off.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a DAG.

FIG. 2 is a diagram illustrating a configuration of a computer system that implements a compiler according to the present invention illustrated in the first embodiment and the second embodiment.

FIG. 3 is a flowchart showing an operation of the JIT compiler shown in FIG. 2;

FIG. 4 is an intermediate code optimizing process shown in FIG. 3 (S17);
6 is a first flowchart illustrating the process of FIG.

FIG. 5 is a flowchart showing an intermediate code creation process (S26) shown in FIG. 4;

FIG. 6 is a flowchart showing a process of creating an intermediate code from a DAG shown in FIG. 5 (S30).

FIG. 7 is a flowchart showing a vertex string alignment process (S37) shown in FIG. 6;

FIG. 8 is an intermediate code optimizing process shown in FIG. 3 (S17);
5 is a second flowchart showing processing subsequent to the processing shown in FIG.

FIG. 9 is a flowchart showing a code generation / register allocation process (S18) shown in FIG. 3;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Java development environment 2 ... Java source code 3 ... Java compiler 4 ... Java bytecode 5 ... Medium 6 ... Client device 7 ... JavaVM 8 ... Java bytecode Verification unit 9 Java interpreter 10 JIT compiler 11 Machine code 12 OS 13 Hardware

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Satoshi Furuseki 1623-14 Shimotsuruma, Yamato-shi, Kanagawa Prefecture Inside the Tokyo Research Laboratory, IBM Japan, Ltd. (72) Inventor Tatsu Inagaki, Yamato-shi, Kanagawa Prefecture 1623-14 Tsuruma, Tokyo Japan Basic Research Laboratories, IBM Japan, Ltd. (72) Inventor Toshiaki Yasue 1623-14 Shimotsuruma, Yamato-shi, Kanagawa Prefecture, Japan Tokyo Research Laboratories, IBM Japan, Ltd. (72 Inventor Hideaki Komatsu 1623-14 Shimotsuruma, Yamato City, Kanagawa Prefecture Inside the Tokyo Research Laboratory, IBM Japan, Ltd. (72) Mikio Takeuchi 1623-14 Shimotsuruma, Yamato City, Kanagawa Prefecture, Japan F-term in M Basic Research Laboratory Tokyo (reference) 5B081 CC25 CC41

Claims (7)

[Claims] 1. A conversion means for converting a source code of a program into a DAG format, and a parameter of a processor for executing an object code corresponding to each instruction included in the converted source code by using a predetermined number of registers. A compiling device comprising: parameter calculating means for calculating; and compiling means for scanning the converted source code and compiling the source code based on the calculated parameters of the processor to generate object code. Wherein the parameter calculating means comprises: timing calculating means for calculating a timing at which the object code corresponding to each of the instructions is executed by the processor; and wherein the object code is occupied when the object code corresponding to each of the instructions is executed. Processor Compiling device having a register decrease calculation means for calculating a numerical value indicating the increase or decrease of register number. 2. The method according to claim 1, wherein the compiling means executes the instructions in the converted source code in accordance with an execution order of the instructions and a priority given to the instructions.
Object code generation means for sequentially compiling each of the instructions to generate an object code for each of the instructions; and executing each of the instructions which may be next compiled based on a numerical value indicating an increase or decrease in the number of registers. Occupied register number calculating means for calculating the number of occupied registers indicating the number of registers of the processor which are occupied when the instruction is executed, based on the calculated number of open registers and the timing at which the object code of the instruction is executed. ,
2. The compiling device according to claim 1, further comprising: a priority assigning unit that assigns a priority to the instruction that is likely to be compiled next. 3. The priority assigning means compares the calculated number of occupied registers with a predetermined threshold. If the calculated number of occupied registers is larger than a predetermined threshold, the priority assigning means calculates the occupied register. 3. The compiling apparatus according to claim 2, wherein an instruction for increasing or decreasing the number of registers is assigned a high priority, and otherwise, an instruction on a critical path is assigned a high priority. 4. The compile means is configured to generate an object code after deleting a common subexpression in the instruction, and when the calculated occupied register number is larger than the predetermined threshold value. 4. The compiling device according to claim 3, further comprising an inverse transform unit for performing an inverse transform for restoring the deleted common subexpression. 5. The compiling device according to claim 1, further comprising data allocating means for allocating said register based on a predetermined constraint condition for restricting a use of a register of said processor. 6. A conversion step of converting a source code of a program into a DAG format, and a parameter of a processor for executing an object code corresponding to each instruction included in the converted source code by using a predetermined number of registers. A compiling method comprising: a parameter calculating step of calculating; and a compiling step of scanning the converted source code and compiling the source code based on the calculated parameters of the processor to generate an object code. In the parameter calculation step, the timing at which the object code corresponding to each of the instructions is executed by the processor is calculated, and the processor occupied when the object code corresponding to each of the instructions is executed. Compiling method for calculating a numerical value indicating the increase or decrease of static number. 7. A conversion step of converting a source code of a program into a DAG format, and a parameter of a processor for executing an object code corresponding to each instruction included in the converted source code by using a predetermined number of registers. A program for causing a computer to execute a parameter calculating step of calculating, and a compiling step of scanning the converted source code and compiling the source code based on the calculated parameters of the processor to generate an object code. Wherein in the parameter calculation step, a process of calculating a timing at which the object code corresponding to each of the instructions is executed by the processor; and an occupation when the object code corresponding to each of the instructions is executed. Medium mediating program for executing a process of calculating a numerical value indicating the register number of increase or decrease of the processor computers.