JP2001068649A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a storage device which can significantly reduce the capacitor area of each memory unit thereby contributing to the increase of the degree of integration of memories and realizing a G bit-class DRAM. SOLUTION: A needle-like body of silicon crystal 11 is formed for each memory unit of a DRAM. A capacitor 10 is formed on the side face of the crystal by using the body 11 as one electrode. Namely, an electrode 13 is provided outside an insulating film 12. Therefore, a capacitor having a large capacitance can be formed with a small occupying area. Preferably, the degree of integration of the DRAM is increased by also forming a switching transistor at part of the needle-like crystal 11. The transistor may be provided at the foot or the tip of the crystal 11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device such as a DRAM which stores electric charges in a capacitor, and more particularly to a high integration of a memory device.

[0002]

2. Description of the Related Art FIG. 1 shows a basic circuit configuration of a DRAM (Dynamic Random Access Memory: a storage device requiring a memory holding operation), in which a capacitor and a switching transistor are connected. The capacitor is grounded, and the switching transistor is connected to a bit line and a word line.

[0003] Conventionally, DRAMs have been required to be highly integrated, and for high integration, it is required to minimize the element occupied area of capacitors and transistors.

[0004] Among them, it is required that the occupied area of the capacitor be reduced while securing necessary capacity. Normal,
The capacitor needs to have a capacitance one digit or more larger than the wiring capacitance. If the capacitance of the capacitor is as small as the wiring capacitance, the electric charge cannot be held and the memory operation becomes impossible. 64MbitD currently mass-produced
The capacitor capacity of the RAM is about 30 fF.

As capacitors having a small area and a large capacitance, a stack capacitor and a trench capacitor have been put into practical use, and the capacitance of these capacitors is increased by three-dimensional arrangement instead of two-dimensional arrangement. Further, there has been proposed a structure in which unevenness is formed on the opposing surface of the capacitor electrode in order to increase the effective area of the capacitor (for example, Japanese Patent Application Laid-Open No. H11-54727). In the current 64 Mbit DRAM, the occupied area of the memory cell has reached about 2 μm ² .

[0006]

As described above, although the area occupied by the capacitor has been conventionally reduced, there is a limit to high integration as long as the conventional technology is used. For example, when realizing a Gbit class DRAM, it is required to reduce the area of the memory cell to about 0.3 μm ² . If this is to be realized by the prior art, the capacitance of the capacitor is equal to the wiring capacitance (several fF).
I will be buried in.

The present invention has been made under the above-mentioned background art, and an object of the present invention is to provide a storage device capable of greatly reducing the capacitor area of each memory unit, thereby achieving high integration of memories. Contributes to Gbit class DRAM
Is also realizable. The present invention achieves the above object by effectively utilizing an appropriate three-dimensional structure.

[0008]

In order to achieve the above object, the present invention relates to a semiconductor memory device for storing information by storing electric charge in a capacitor constituting each memory unit. And a capacitor is formed using the side surface of the needle-shaped body as one electrode.

According to the present invention, since the capacitor is formed on the side surface of the silicon crystal needle, the area of the capacitor electrode is large although the area when viewed from above the needle is small. Therefore, even if the occupied area is reduced, the capacitance of the capacitor can be secured, and the electric signal can be sufficiently secured. By utilizing this structure, integration of the memory can be achieved.

The suitable size of the silicon crystal needle is, for example, a tip diameter of about several nanometers and a height of about 5 to 10 micrometers. The needle functions as one electrode of a capacitor. The other capacitor electrode (outer electrode) is formed around the needle-like body via a film such as an oxide film. The other electrode is formed of, for example, conductive polysilicon (polycrystalline silicon). With such a configuration, a sufficiently large capacitor capacity, for example, about 18 fF, is ensured as compared with the wiring capacity.

The above-mentioned needle-like body of silicon crystal is preferably obtained by anisotropically etching the silicon substrate or the silicon layer with a high selectivity using the impurity deposition region formed in the silicon substrate or the silicon layer as a micromask. Thus, a weight-shaped structure formed with the micromask as a vertex. As a result, an appropriate silicon needle-shaped body that achieves the required capacitor capacity can be obtained.

In a preferred aspect of the present invention, a switching transistor for supplying a charge to the capacitor is formed in a part of the needle-shaped body of the silicon crystal. The switching transistor may be formed at a base (base, base end, or root) of the needle-shaped body of the silicon crystal. The switching transistor may be formed at a tip of a needle-like body of the silicon crystal. According to this aspect, further integration of the memory becomes possible.

Further, in the configuration in which the switching transistor is arranged at the tip of the needle-shaped body of silicon crystal, a single-electron transistor function in which the tip of the needle is a quantum dot can be obtained, and power consumption can be reduced.

Another embodiment of the present invention is a method for manufacturing a semiconductor memory device. The method includes the steps of forming a needle of silicon crystal and forming a capacitor on a side of the needle of silicon crystal. The method further includes forming a switching transistor for supplying electric charge to the capacitor on or near the needle of the silicon crystal.

As described above, according to the present invention,
By forming a capacitor on the side surface of the silicon crystal needle, a large capacitor capacity can be secured with a small area. By forming the switching transistor in a needle shape, further integration becomes possible. A silicon needle having a suitable shape is obtained by the above-described anisotropic etching. In this way, the size of the memory cell can be reduced, and the memory can be highly integrated.
It can also contribute to the realization of a t-class DRAM.

Here, the DRAM has been mainly described, but the present invention is naturally applicable to any type of storage device using a capacitor other than the DRAM.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention (hereinafter, referred to as embodiments) will be described below with reference to the drawings.

<Embodiment 1>> FIG. 2 shows the D of the present embodiment.
1 schematically shows memory cells (memory units) constituting a RAM. Here, one memory cell is shown, but by arranging many similar memory cells, DR
AM is configured. The overall configuration and principle of the DRAM may be the same as those of a conventional DRAM, and a detailed description thereof will be omitted.

FIG. 2A is a front sectional view of the memory cell, and FIG. 2B is a sectional view taken along the line AA of FIG. 2A. As shown, the memory cell has a capacitor 10 and a switching MOS transistor 20, which are arranged next to each other and connected to each other.

First, the capacitor 10 will be described.
As a feature of the present invention, a capacitor 10 is formed on the side surface of a silicon crystal needle-like projection 11 (corresponding to the needle-like body of the present invention). The needle-like projections 11 are conical, and the silicon substrate 1
Projecting from. The needle-like projection 11 functions as one electrode of the capacitor, that is, a ground-side capacitor electrode. The needle-like projections 11 are covered with an insulating film 12 made of a thermal oxide film. A switch-side capacitor electrode 13 (outer electrode), which is another electrode of the capacitor, is formed so as to surround the needle-like protrusion 11 via the insulating film 12. The capacitor electrode 13 is preferably formed of conductive polysilicon (polycrystalline silicon). Capacitor electrode 13
Starts from the base of the needle-shaped protrusion 11 and reaches a predetermined height slightly below the protrusion apex. The outside of the capacitor electrode 13 is covered with an insulating film 14.

On the other hand, the switching MOS transistor 2
Reference numeral 0 denotes an n-channel MOSFET, which is formed on the same plane as the bottom surface of the needle-like projection 11 and next to the needle-like projection 11. As shown, the flat portion of the silicon substrate 1 is covered with an insulating film 12 like the needle-like projections 11. Below the insulating film 12, a source impurity concentration layer 21 and a drain impurity concentration layer 22 are provided at intervals. A word line 23 as a gate electrode is provided above these layers 21 and 22 via an insulating film 12. Word line 2
Numeral 3 extends in a direction perpendicular to the plane of the drawing, and the lower region is a channel of the transistor. The word line 23 is preferably formed of polysilicon, and is more preferably formed simultaneously with the capacitor electrode 13. The word line 23 is also covered with the insulating film 14.

Further, the source impurity concentration layer 21 is connected to the switch-side capacitor electrode 13. That is,
A part of the capacitor electrode 13 is separated from the needle-shaped protrusion 11
It extends to the source impurity concentration layer 21. On the other hand, the drain impurity concentration layer 22 is connected to a bit line 24 arranged on the insulating film 14. Bit line 24 is preferably formed of aluminum.

The configuration of the memory cell has been described above. The operation of the memory cell is basically the same as that of a known memory,
When a signal is applied to the word line 23, a channel below the word line 23 is turned on, and electrons flow from the bit line 24 to the switch-side capacitor electrode 13.

Next, the preferred size of the needle-like projection 11 of silicon crystal constituting the capacitor 10 will be described. The diameter of the tip is 10 nm or less, preferably several nm, and the height of the projection is 5 to 10 μm. It is. For example, when the crystal height is 5 μm, the capacitance value of the capacitor part is about 18 fF,
This value is sufficiently larger than the wiring capacitance, and therefore can withstand charge retention as a memory cell. At this time, the size of the root of the needle-like projection 11 is about 0.2 μm. The element occupation area in the case of the configuration of FIG.

As described above, according to the present embodiment, since the capacitor is formed on the side surface of the silicon needle crystal, the area of the capacitor electrode can be increased despite the small area when viewed from above the needle. Thus, a necessary capacitor capacity can be secured.

Next, a method of manufacturing the DRAM of this embodiment will be described. In the present invention, the microneedle projection is an important component for the memory cell. An important point is how to make a structure having the needle-like projections. Therefore, first, a method of forming needle-like projections on a silicon substrate devised by the present inventors will be described.

The needle-shaped body of the present embodiment is of a weight type and is formed so as to protrude from the substrate. This silicon needle-shaped cone is formed by using an impurity deposition region formed in a single-crystal silicon substrate or a single-crystal silicon layer as a micromask, and performing anisotropic etching of the silicon substrate or the silicon layer with a high selectivity to form a micromask. It can be formed as a vertex.

FIG. 3 shows the principle of forming a silicon needle cone. On a silicon substrate (or a silicon layer)
For example, oxygen is introduced as an impurity. When heat treatment is performed on the silicon substrate into which oxygen has been introduced, an oxygen precipitation region (oxygen precipitation defect SiO ₂ in which agglomerated oxygen and Si are combined) is formed as an impurity precipitation region in the region into which oxygen has been introduced (FIG. 3 (a) → (b)).

After the heat treatment, the silicon substrate is
_{2 When} anisotropic etching is performed under the condition of large selectivity,
An oxygen precipitate having an etching rate different from that of the i crystal (which is harder to etch than the Si crystal in this case) serves as a micromask, and a silicon cone is formed on the exposed surface with the mask serving as a vertex (FIG. 7D). . In the anisotropic etching, for example, when an oxygen deposition region in a silicon substrate or a silicon film is used as a micromask, a halogen-based (B
It can be performed by dry etching (for example, reactive ion etching) using a gas containing (r, Cl, F) gas. By etching under such conditions, FIG.
A cone having the apex of the oxygen precipitation region as described above, here a cone, is obtained.

As described above, in the present invention, the impurity deposition region is used as a micromask. The deposition area is preferably obtained by ion implantation and heat treatment. A mask that is sufficiently smaller than the mask that can be formed by photolithography is obtained, resulting in a very steep and sharp silicon needle-shaped cone. This needle-shaped weight can also function as a quantum dot as described later.

Explaining the specific size, a very elongated needle cone having a radius of curvature near the tip of the needle of several nm to several tens of nm and an aspect ratio of about 10 can be obtained. Further, the base angle of the cone is extremely large, for example, about 80 ° or more, and the height of the cone can be about several μm. The aspect ratio of the needle-shaped cone is controlled to 1 by controlling the mixing ratio of a mixed gas used for anisotropic etching.
It can be greater than or equal to 0 (it can be less than 10 if necessary).

In the above process, a plurality of silicon needle-shaped weights having the same shape and size are formed by setting the plane position and the depth position of the impurity deposition region to predetermined positions.

The density of the silicon needle-shaped weight varies depending on the amount of oxygen injected (dose) when forming the micromask. Therefore, in the present embodiment, as shown in FIG. 4, photolithography is performed so as to open a region where the needle-shaped weight is to be formed, and approximately one needle-shaped weight is formed in the opened region under a suitable oxygen dose condition. Can be formed. Thereby, a silicon needle-shaped weight body is formed in a grid shape.

Next, an example of a method of forming the memory cell of FIG. 2 using a needle crystal will be described with reference to FIGS. First, as shown in FIG. 5A, a silicon needle crystal is formed on a p-type silicon substrate by the above method, and then oxidized to form a thermal oxide film. The thermal oxide film covers the entire silicon substrate and the needle crystals. In FIG. 5B, the thermal oxide film is partially removed by lithography and dry etching. The removal region is a region where the source electrode concentration region of the switching transistor is brought into contact with the capacitor electrode. In FIG. 5C, polysilicon is deposited on the entire surface by a low pressure CVD method. Thereafter, phosphorus is diffused into the polysilicon to have a high concentration of about 10 ²¹ cm ^-3 . As a result, the polysilicon has sufficient conductivity.
The polysilicon will later become capacitor electrodes and word lines.

Referring to FIG. 6A, a resist is applied, and a part of the resist is exposed and removed by photolithography. The removal region is a region where the source and drain impurity concentration layers of the switching transistor are to be formed. The resist is not originally applied to the tip of the needle-shaped crystal due to the viscosity of the resist. FIG. 6 (b)
Dry-etch polysilicon. The polysilicon is divided into a capacitor electrode portion and a word line portion. In FIG. 6C, As + ions are implanted to form source and drain impurity concentration layers of the switching transistor.

Referring to FIG. 7A, an oxide film doped with boron and phosphorus is deposited by plasma CVD. The oxide film covers the entire region including the needle crystal and the impurity concentration layer, and functions as an insulating film. In FIG. 7B,
A contact hole for extracting a symbol of each electrode is formed by etching. Then, aluminum is sputtered, and turning is performed by photolithography and dry etching. As a result, as shown in the figure,
A bit line is formed of aluminum.

As described above, the memory cell of FIG. 2, that is, the capacitor formed in the silicon needle crystal,
A memory cell having a transistor connected next to the capacitor is formed. This embodiment also has the advantage that the process is relatively simple.

<Embodiment 2. Next, a second embodiment of the present invention will be described with reference to FIG. The feature of the present embodiment is that, in addition to the formation of the capacitor 10 on the side surface of the silicon crystal needle, a switching transistor is formed on a part of the needle. That is, both the capacitor and the switching transistor are formed in the silicon needle crystal, thereby further integrating the memory.

FIG. 8A is a front sectional view of the memory cell, FIG. 8B is a sectional view taken along line B1-B1 of FIG. 8A, and FIG. 8C is a sectional view of FIG. 3 is a B2-B2 cross section of FIG. As shown, the capacitor 30 is formed on the side surface of the needle-shaped body 31 made of silicon crystal. The switching transistor 40 is provided at the base of the needle-shaped body 31 (the base, the base,
(At the base end or the end on the substrate side) adjacent to the capacitor. The capacitor 30 and the transistor 40 are separated by an insulating film 34.

First, the configuration of the capacitor 30 will be described. As in FIG. 2, a conical needle-like projection 31 protrudes from the silicon substrate 1. However, unlike the needle-like projections shown in FIG. 2 which functioned as the ground-side capacitor electrodes, the needle-like projections 31 of the present embodiment function as switch-side capacitor electrodes. The needle-like projections 31 are covered with an insulating film 32 made of a thermal oxide film.
The flat part is also covered. Then, the ground-side capacitor electrode 33 (outer electrode) which is another electrode of the capacitor
Surrounds the needle-like projection 11 via the electrode insulating film 32. The ground-side capacitor electrode 33 is connected to a ground terminal. Preferably, capacitor electrode 33 is made of conductive polysilicon. The outside of the capacitor electrode 33 is covered with an insulating film 34.

Unlike FIG. 2, the lower end of the capacitor electrode 33 is located at an appropriate height in the middle of the needle 31. That is, the capacitor 30 is formed on the side surface above the middle, except for the base (base) of the needle-like body 31.

On the other hand, in the switching transistor 40, the gate electrode portion 43a surrounds the periphery of the root of the needle-like projection 31. The insulating film 32 is interposed between the gate electrode portion 43a and the needle-like protrusion 31. A word line 43 extends in the horizontal direction from the gate electrode portion 43a, and the word line 43 is formed on the insulating film 32 on the flat portion of the substrate.
The gate electrode portion 43a and the word line 43 are preferably integrally formed conductive polysilicon layers.
The bit line 44 of the transistor 40 is formed below the needle-like projection 31. The bit line 44 is connected to the silicon substrate 1
An n-type impurity concentration layer formed therein, and extends laterally along the substrate surface.

As described above, in the present embodiment, the transistor 40 is a MOSFET in which the polysilicon layer formed around the base (base) of the silicon needle crystal 31 is used as a gate electrode. The channel is formed at the interface with the thermal oxide film around the base of the needle crystal. When a signal is applied to the word line, the channel is turned on, and electrons flow from the bit line toward the needle crystal.

Also in the present embodiment, a necessary capacitor capacity is secured by using a needle-shaped crystal having an appropriate shape similar to that of the embodiment of FIG. In the present embodiment, the number of manufacturing steps is greater than in the embodiment of FIG. However, since the capacitor and the switching transistor are formed in the silicon needle crystal portion, the occupied area of the memory cell can be reduced, and the DRAM can be highly integrated. The area occupied by the silicon needle crystal substantially corresponds to the area occupied by the memory cell. Therefore, a memory cell having a small size of about 0.3 μm × 0.3 μm can be produced, and thus a Gbit class DRAM can be realized.

This embodiment can of course be arbitrarily modified within the scope of the present invention. That is, another configuration may be adopted as long as the base transistor of the needle-shaped crystal is formed and the capacitor is formed on the tip side thereof.

Next, an example of a method of manufacturing the DRAM of this embodiment will be described with reference to FIGS. First, FIG.
As shown in (a), conical silicon needle-like crystals projecting from the p-type silicon substrate are formed. This needle-like crystal is formed by the characteristic method of the present invention described with reference to FIG. Further, an n-type impurity concentration layer is formed by ion-implanting phosphorus into the depth of the needle-like crystal bottom. The n-type impurity concentration layer starts from the lower part of the silicon needle crystal and extends laterally along the surface of the silicon substrate. This part functions as a bit line later. Further, a thermal oxide film is formed so as to cover the entire silicon substrate flat portion and the silicon needle crystal.

In FIG. 9B, polysilicon is deposited on the thermal oxide film by a low pressure CVD method. After that, phosphorus is diffused into the polysilicon to have a high concentration of about 10 ²¹ cm ^-3 to provide sufficient conductivity. In FIG. 9C, a resist is applied, and the resist is removed by photolithography. The region where the resist remains is only the region corresponding to the gate electrode portion (near the foot of the needle-like crystal portion) and the word line extending therefrom.

Referring to FIG. 10A, the polysilicon layer is removed by dry etching. Thus, the gate electrode of the switching transistor and the word line are patterned. In FIG. 10B, a thermal oxide film is formed by the thermal oxidation process. The thermal oxide film is formed on the patterned polysilicon, and from the center of the needle-shaped crystal to the upper part (portion where the polysilicon is not formed).
Also formed over. Next, as shown in FIG. 10C, polysilicon is deposited by a low pressure CVD method.
After that, phosphorus is diffused into the polysilicon to make 10 ²¹
Sufficient electrical conductivity is provided at a high concentration of about cm ^-3 .

Next, dry etching is performed in the state shown in FIG. In this case, the vertical thickness a at the top of the crystal is sufficiently smaller than the vertical thickness b on the side wall of the needle crystal. The vertical thickness of the polysilicon layer around the needle-shaped crystal (the flat portion of the substrate) is also sufficiently small. Therefore, by utilizing this difference in film thickness and setting appropriate dry etching processing conditions, it is possible to leave polysilicon only on the side walls of the needle-like crystals and remove all the polysilicon in other portions.
The result of this etching process is shown in FIG. 11A, and the remaining polysilicon becomes the ground-side capacitor electrode.

Referring to FIG. 11B, an oxide film is deposited on the entire surface by the CVD method. Further, in FIG. 11C, a contact portion is formed by performing a dry etching process on the oxide film formed by the CVD method. The contact portion is formed to a depth reaching the lower end portion of the polysilicon for the capacitor electrode. An aluminum wiring is formed so as to be connected to polysilicon via the contact portion, and the aluminum wiring is grounded. As a result, a wiring for grounding the outer electrode of the capacitor is formed. In addition, 10 (c)
8 and FIG. 8, the arrangement of the aluminum wiring for grounding is different.
This wiring can be changed appropriately.

As described above, the memory cell of FIG. 8, that is, the memory cell having the switching transistor formed at the base of the silicon needle crystal and the capacitor formed at the tip thereof is formed.

<Embodiment 3>> Next, referring to FIG.
A third embodiment of the present invention will be described. As in the above-described embodiment, in this embodiment, both the capacitor 50 and the switching transistor 60 are formed on the silicon crystal needle 51. However, as a feature of the present embodiment, the switching transistor 60 is formed at the tip of the needle-like crystal 51, and the capacitor 50 is formed at other portions.

FIG. 12A is a front sectional view of the memory cell, FIG. 12B is a sectional view taken along line C1-C1 of FIG. 12A, and FIG. 12C is a sectional view of FIG. 5 is a C2-C2 cross section of FIG.

First, the configuration of the capacitor 50 will be described. A buried oxide film 55 is formed in the silicon substrate 1,
Needle-like bodies 51 of silicon crystal project above oxide film 55. The needle-shaped body 51 functions as a switch-side capacitor electrode.

The needle-like body 51 is an insulating film 52 made of a thermal oxide film.
Covered by Then, the needle-like body 51 is made of the insulating film 5.
2, the capacitor is surrounded by a ground-side capacitor electrode 53 (outer electrode), which is another electrode of the capacitor. The lower end of the ground-side capacitor electrode 53 extends in the horizontal direction and is connected to a ground terminal. Preferably, capacitor electrode 53 is polysilicon having conductivity. Capacitor electrode 53
Is further covered with an insulating film 54.

In the present embodiment, the capacitor 50 is formed in a region other than the tip of the needle 51, that is, on the side surface below the middle. Accordingly, the upper end of the installation range of the ground-side capacitor electrode 53 is set to an appropriate height slightly lower than the upper end of the needle-shaped body 51, and the lower end of the electrode is set to the needle-shaped body 51.
It is set equal to the lower end of.

Next, the configuration of the switching transistor 60 will be described. The vicinity of the tip of the needle 51 is locally surrounded by the gate electrode 63a. Gate electrode section 63
An insulating film 52 is interposed between a and the needle 51. The gate electrode portion 63a and the lower capacitor electrode 53 are separated by an insulating film 54, and the gate electrode portion 63a reaches only a little below the tip of the needle. Gate electrode section 63
A word line 63 extends laterally from a. The gate electrode portion 63a and the word line 63 are preferably integrally formed conductive polysilicon layers.

The bit line 64 of the transistor 60 is formed above the tip of the needle 51. Since the bit line 64 is formed on the insulating film 54, the insulating film 52 and the insulating film 54 are interposed between the bit line 64 and the tip of the needle 51. However, as shown, the insulating film 54 in this portion is provided thin.

As described above, in the present embodiment, the gate electrode is formed around the vicinity of the tip of the needle-shaped crystal, and the bit line is formed above the needle-shaped crystal. Thus, the function of the switching transistor 60 is obtained. The channel of the transistor is formed near the vertex of the needle crystal at the interface with the thermal oxide film. When a signal is applied to the word line, the channel is turned on, and electrons flow from the bit line to the needle crystal.

At this time, the tip of the needle-shaped crystal is very thin,
Because of the nano-order size, a high electric field is generated at the tip,
This high electric field causes destruction of the thermal oxide film. By this oxide film destruction, contact between the aluminum of the bit line and the needle-shaped crystal is secured.

The memory cell according to the present embodiment has been described above. In this embodiment, as in the above-described embodiment, both the capacitor and the transistor are formed in the silicon needle crystal, so that the DRAM can be highly integrated. The area occupied by the memory cell substantially corresponds to the area occupied by the needle crystal. Assuming that the size of the tip of the needle-shaped crystal is several nanometers, the occupied area of the memory cell is 0.3 μm × 0.3 μm
Gbit class DRAM can be realized.

Further, according to the present embodiment, the tip of the needle-like crystal is used for the switching transistor, and the tip is a nano-level fine region. Therefore,
By reducing the supply bias, it is possible to function as a single-electron transistor in which the tip of the crystal is a so-called quantum dot. With the provision of the single-electron transistor, power consumption can be reduced.

This embodiment can of course be arbitrarily modified within the scope of the present invention. That is, another configuration may be adopted as long as a transistor is formed at the tip of the needle crystal and a capacitor is formed below the transistor. For example, instead of the buried oxide film 55 in FIG. 12, a pn junction isolation using a silicon substrate doped with a p-type impurity (the needle-like crystal part is an n-type impurity concentration layer) may be adopted.

Next, a method of manufacturing the DRAM of this embodiment will be described with reference to FIGS. First, FIG.
As shown in (a), SOI (Silicon On)
An insulator is prepared, and a silicon needle crystal is formed in the single crystal layer on the buried layer of the SOI substrate. The needle-like crystal is formed by the characteristic method of the present invention described with reference to FIG. Thereafter, the silicon needle crystals are oxidized by thermal oxidation.

In FIG. 13B, polysilicon is deposited by a low pressure CVD method, and then phosphorus is diffused in the polysilicon to a high concentration of about 10 ²¹ cm ^-3 to give conductivity. In FIG. 13C, application of a resist and photolithography are performed. The region where the resist is left is only the region excluding the tip of the silicon needle crystal and the region corresponding to the ground line in the flat portion.

Dry etching is performed from the state shown in FIG. Then, as shown in FIG. 14A, the conductive polysilicon remains in a range from the lower end of the needle-like crystal to an appropriate height (a range excluding the tip portion) and a connecting portion extending in the lateral direction. That is, patterning of one electrode region of the capacitor is performed. In FIG. 14B, a thermal oxidation process is performed after removing the resist. A thermal oxide film is formed on the patterned polysilicon. Then, decompression CV
Polysilicon is deposited again by the method D, and phosphorus is diffused into the polysilicon to increase the concentration to about 10 ²¹ cm ^-3 to provide conductivity.

Next, from FIG. 14 (c) to FIG. 15 (a), the gate electrode portion of the switching transistor and the word line are processed. In FIG. 14C, application of a resist and photolithography are performed. The resist is left on the gate electrode around the tip of the needle crystal and on the word line extending therefrom. Then, FIG.
As shown in (a), dry etching is performed to remove polysilicon other than the gate electrode portion and the word line.

In FIG. 15B, after removing the resist, the CV
An oxide film is deposited by the D method. The oxide film is formed entirely and functions as an insulating film. In FIG. 15C, an aluminum wiring is formed at the tip of the silicon needle crystal. This aluminum wiring functions as a bit line as described above.

As described above, the memory cell shown in FIG.
That is, a memory cell having a switching transistor formed at the tip of the silicon needle crystal and a capacitor formed below the switching transistor is formed.

The manufacturing processes described in the first to third embodiments are merely examples, and it goes without saying that other processes may be used. Further, the manufacturing process is appropriately changed according to the deformation of the memory cell within the scope of the present invention.

[0071]

As described above, according to the present invention, a needle-like body of silicon crystal is provided in a memory cell, and a capacitor is formed on the side surface of the needle-like body, so that a large capacitor capacity can be secured with a small area. Furthermore, by providing a switching transistor on the needle-like body, the area occupied by the memory cell can be significantly reduced. Needles having an appropriate shape and structure are preferably obtained by an anisotropic etching method using a micromask devised by the present inventors. As described above, high integration of the semiconductor memory device becomes possible, and Gb
It becomes possible to realize an it class DRAM.

Although the DRAM has been mainly described here, it goes without saying that the present invention can be similarly applied to a semiconductor memory device using a capacitor other than the DRAM, as described above.

[Brief description of the drawings]

FIG. 1 is a diagram showing a basic configuration of a memory cell of a DRAM.

FIG. 2 is a diagram illustrating a configuration of a memory cell of the DRAM according to the first embodiment of the present invention.

FIG. 3 is a diagram illustrating a method of generating a silicon needle-shaped body of the memory cell of FIG. 2;

FIG. 4 is a view showing a method of forming needle-shaped weights in an appropriate arrangement by the processing of FIG. 3;

FIG. 5 is a first diagram illustrating a step of forming the memory cell of FIG. 2;
FIG.

FIG. 6 is a second diagram illustrating a step of forming the memory cell of FIG. 2;
FIG.

FIG. 7 is a third view showing a step of forming the memory cell of FIG. 2;
FIG.

FIG. 8 is a diagram showing a configuration of a memory cell according to a second embodiment of the present invention.

FIG. 9 is a first diagram illustrating a step of forming the memory cell of FIG. 8;
FIG.

FIG. 10 is a second diagram showing a step of forming the memory cell of FIG. 8;

FIG. 11 is a third diagram showing a step of forming the memory cell of FIG. 8;

FIG. 12 is a diagram showing a configuration of a memory cell according to a third embodiment of the present invention.

FIG. 13 is a first diagram showing a step of forming the memory cell of FIG. 12;

FIG. 14 is a second diagram showing a step of forming the memory cell of FIG. 12;

FIG. 15 is a third diagram showing a step of forming the memory cell of FIG. 12;

[Explanation of symbols]

REFERENCE SIGNS LIST 1 silicon substrate, 10 capacitor, 11 silicon needle, 12 insulating film, 13 capacitor electrode on switch side, 14 insulating film, 20 switching transistor,
21 source impurity concentration layer, 22 drain impurity concentration layer, 23 word lines, 24 bit lines.

 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Koichi Mitsushima 41-1, Oku-cho, Yokomichi, Nagakute-cho, Aichi-gun, Aichi Prefecture F-term in Toyota Central R & D Laboratories, Inc. 5F083 AD21 AD54 GA09 JA02 KA05 PR03 PR21 PR36

Claims (4)

[Claims] 1. A semiconductor memory device for storing information by storing electric charge in a capacitor constituting each memory unit, wherein a needle of a silicon crystal is formed in each memory unit, and a side surface of the needle is connected to one side. A semiconductor memory device, wherein a capacitor is formed as an electrode. 2. The semiconductor memory device according to claim 1, wherein a switching transistor for supplying a charge to said capacitor is formed at a part of said needle-shaped body of said silicon crystal. Semiconductor storage device. 3. The semiconductor memory device according to claim 2, wherein the switching transistor is formed at a foot of a needle-shaped body of the silicon crystal, and the capacitor is formed at a tip side thereof. Semiconductor storage device. 4. The semiconductor memory device according to claim 2, wherein the switching transistor is formed at a tip of a needle-like body of the silicon crystal, and the capacitor is formed below the needle. Semiconductor storage device.