JP2001060970A - Address retrieving device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an address retrieving device capable of obtaining desired through put even when short packets consecutively arrives by reducing an IP address longest coincidence retrieving processing time. SOLUTION: Retrieving processing parts 11, 12, 13 for executing the longest coincidence retrieval of an address based on a routing table are plurally provided, packets are assigned to the prescribed parts 11 to 13 in the order of retrieval and the respective parts 11 to 13 execute the longest coincidence retrieval by parallel processing. It is preferably provided with retrieving processing parts whose number is larger by one than the integral number part of a quotient obtained by dividing the longest necessary time for retrieving an address by one retrieving processing part by the arriving necessary time of the shortest packet length. Further, it is preferred that the parts 11 to 13 output an operating state signal showing operating states including that of retrieving processing operation and waiting and start retrieving processing when a control signal instructing the start of retrieving processing is inputted during the waiting.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an address search device capable of speeding up address search in a high-speed IP packet transfer processing device.

[0002]

2. Description of the Related Art In order to determine a transfer destination port number of an IP packet, a longest match search process of an IP address is required. A conventional IP address longest match search apparatus stores routing information relating to an IP address as a table as a DR.
When the IP packet arrives at the AM and accesses the DRAM while referring to the transfer destination IP address value, the longest match search is performed to determine the transfer destination.

In this case, since the random access time of the DRAM is generally about 50 ns, it is difficult to determine the transfer destination in a time shorter than the access time to the DRAM even if the DRAM access is pipelined. It is. That is, in a situation where the shortest packets arrive continuously, the search processing cannot be performed in time.

For example, a synchronous optical network "SONE"
T ", at a transfer rate of 9.95 Gb / s specified as OC-192, if packets of 48 bytes in length corresponding to the shortest packet continuously arrive, they will arrive at an interval of approximately 38 ns. , 38 ns or less, it is necessary to perform the longest match search processing of one packet.

Although a method of holding routing information in an SRAM which can be accessed at a high speed instead of a DRAM has been proposed, since the SRAM has only one-tenth the degree of integration as compared with the DRAM, an enormous amount of SRAM is required. In order to hold the routing information, a large number of chips are required, which increases the cost.

Further, in IP version 6, since the IP address is converted into 128 bits, the load of the IP address longest match search processing is expected to be further increased, and the search processing time is expected to be longer. As described above, the address search requires a lot of processing time, and has been a bottleneck in performing high-speed packet transfer.

[0007]

SUMMARY OF THE INVENTION In view of the above situation, an object of the present invention is to reduce the longest match search processing time of an IP address and obtain a desired throughput even when short packets continuously arrive. An address search device is provided.

[0008]

In order to achieve the above object, an address search apparatus according to the present invention includes a plurality of search processing units for performing a longest match search of an address based on a routing table, and receives a packet when it arrives. The search processing units are sequentially assigned to predetermined search processing units, and each search processing unit performs a longest match search by parallel processing.

In the present invention, the number of search processing units which is larger by one than the integer part of the quotient obtained by dividing the maximum required time required for an address search by one search processing unit by the required arrival time of the shortest packet length is provided. It is desirable to have. Further, the search processing unit may output an operation state signal indicating an operation state including the search processing operation and the standby state, and start the search processing when a control signal instructing the start of the search processing is input during the standby state. Is desirable. Also, an address holding register for holding a search address value, a transfer destination port number holding register for holding a transfer destination port number, and a control unit are provided. Under the control of the control unit, the address values are waiting from the address holding register in the order of packet arrival. It is desirable to have a configuration for transferring the data to the search processing unit, starting the search operation, and transferring the transfer destination port number obtained from the search to the transfer destination port number holding register.

According to such an address search apparatus of the present invention, a plurality of IP address longest match search processing units are provided,
When a packet arrival interval is shorter than the processing time of each search processing unit, a desired throughput can be realized by performing search processing in parallel using a plurality of search processing units.

Now, let the shortest packet length be Rmin bytes,
Assuming that the data transfer rate is CGb / s, and as shown in the time chart of FIG. 1, that the arrival time interval when the shortest packet length continuously arrives is Tint, Tint =
8Rmin / C (ns). On the other hand, the time required for the longest match search processing generally varies, but if the maximum value of the time required for the search processing is Tmax (ns), one search processing unit converts (Tmax / Tint) +1 packets into (Tmax / Tint) +1 packets. The search process can be performed once. Therefore, the parallelism npara of the search processing unit is set to npara = [Tmax / Tint] +1 (FIG. 1 shows an example of npara = 3), and if these are sequentially operated in parallel, the search processing is continued without interruption. Can be done.

[0012]

Next, embodiments of the present invention will be described.
FIG. 2 is a diagram showing the configuration of an embodiment of the address search device of the present invention. In this embodiment, the address search device 1
Denotes three search processing units 11, 12, and 13, an address holding register 14 for holding an IP address value, a destination port number holding register 15 for holding a destination port number, and a control unit.
With 16 Search processing units 11, 12, and 13 are output terminals for operation state signals 31, 32, and 33 indicating search operation states, and search processing start signals 21, 22, and 23 for instructing start of search operation.
Signal input terminals for each. Operating status signal
For example, 31, 32, and 33 continuously output the H level during the search processing, and continuously output the L level during the standby state. Further, when the signal input terminals for the search processing start signals 21, 22, and 23 are triggered when the operation state signals 31, 32, and 33 are at the L level, the search operation is started.

Assuming now that the shortest packet length Rmin = 48 bytes and the data transfer rate C = 9.95 Gb / s, the shortest packet length packet arrival time interval Tint at this time is Tint = 38.5
9 ns. On the other hand, assuming that the maximum value of the time required for one longest match search process in the search processing unit is Tmax = 100 ns, the degree of parallelism npara = [100 / 38.59] +
1 = 3. Therefore, in this embodiment, three search processing units 11, 12, and 13 are provided. The control unit 16 generates each of the search processing start signals 21, 22, and 23 based on the IP address update signal 41 from the address holding register 14 and the operation state signals 31, 32, and 33 of each of the search processing units 11, 12, and 13. create.

Next, the operation of the address search device 1 of FIG. 2 will be described with reference to the timing chart of FIG. First, when an IP address is newly loaded into the address holding register 14, the IP address update signal 41 is triggered.
When the control unit 16 receives the IP address update signal 41, the operation state signals 31, 32, and 33 from the search processing units 11, 12, and 13 are received.
, The search processing unit 11 not performing the search processing,
A search processing start signal 21, 22, or 23 is issued for 12 or 13. In this case, when there is a plurality of search processing units that are not performing the search operation, the search processing unit 11, 12, or 13 that performs the search processing according to a predetermined rule is selected, and the search processing start signals 21, 22, or Issue 23.

In the example shown in FIG. 3, a search processing start signal 21 is first issued to the search processing unit 11. The search processing unit 11 receives the search processing start signal 21 and starts the search processing. Search processing section
11 holds the operation state signal 31 at the H level during the search process. Next, when the packet having the shortest packet length arrives again, the IP address update signal 41 is triggered, and the control unit 16 receives the packet and sends the search processing start signal 22 to the search processing unit 12 which has not performed the search processing. Emit.
The search processing unit 12 receives the search processing start signal 22 and starts the search processing. The search processing unit 12 holds the operation state signal 32 at the H level during the search processing. Subsequently, when the packet having the shortest packet length arrives, similarly, the IP address update signal 41 is triggered, and the control unit 16 receives the packet and sends the search processing start signal 23 to the search processing unit 13 which has not performed the search processing. Emits. The search processing unit 13 receives the search processing start signal 23 and starts the search processing. Search processing unit 13
Holds the operation state signal 33 at the H level during the search process.

Subsequently, when a packet having the shortest packet length arrives, the IP address update signal 41 is triggered. At this point, since the search by the search processing unit 11 has been completed, the operation state signal 31 is at the L level. Therefore,
The control unit 16 sends a search processing start signal 21 to the search processing unit 11.
Emits.

In the transfer destination port number holding register 15, the detection processing is completed by detecting that the operation state signals 31, 32, and 33 have transitioned from the H level to the L level from the search processing unit 11, 12, or 13. The detection processing unit is selected, and the transfer destination port number value is loaded into the transfer destination port number holding register 15.

Similarly, even when the shortest packet arrives continuously, one of the detection units is always waiting for the detection operation. Therefore, the search is performed by the parallel processing by sequentially replacing the search processing units. Address search can be speeded up.

[0019]

As described above, according to the present invention,
By providing a plurality of conventional IP address search devices and performing parallel search processing by appropriately controlling these devices according to the arrival intervals of IP packets, address search can be speeded up. Transfer processing can be speeded up.

[Brief description of the drawings]

FIG. 1 is a time chart for explaining a case where shortest packets continuously arrive.

FIG. 2 is a diagram showing a configuration of an embodiment of an address search device of the present invention.

FIG. 3 is a timing chart for explaining a case where a shortest packet continuously arrives at the address search device of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Address search device 11, 12, 13 Search processing part 14 Address holding register 15 Transfer destination port number holding register 16 Control part 21, 22, 23 Search processing start signal 31, 32, 33 Operating state signal 41 IP address update signal

Continuation of the front page (72) Inventor Naoaki Yamanaka 2-3-1 Otemachi, Chiyoda-ku, Tokyo F-term in Nippon Telegraph and Telephone Corporation (reference) 5K030 GA01 HA08 HC14 KA05 LB05 5K033 CB08 CC01 EC04 9A001 BB03 BB06 CC02

Claims (4)

[Claims] 1. A search processing unit for performing a longest match search of an address based on a routing table, allocating packets to predetermined search processing units in the order of arrival, and each search processing unit performing a longest match search by parallel processing. Address search device characterized by comprising: 2. The method according to claim 1, wherein one search processing unit has a maximum required time required for searching for an address divided by an arrival time required for the shortest packet length, and the number of search processing units is greater by one than an integer part of a quotient. The address search device according to claim 1, wherein 3. The search processing unit outputs an operation state signal indicating an operation state including a search processing operation and a standby state, and performs a search processing when a control signal instructing start of the search processing is input during the standby state. 3. The address search device according to claim 1, wherein the address search is started. 4. An address holding register for holding a search address value, a transfer destination port number holding register for holding a transfer destination port number, and a control unit, and the control unit controls the address values from the address holding register in the order of packet arrival. 4. The apparatus according to claim 1, further comprising a configuration in which the data is transferred to a standby search processing unit, a search operation is started, and a transfer destination port number obtained from the search is transferred to a transfer destination port number holding register. The address search device according to claim 1.