JP2001060181A - Bus competition avoiding method for processor system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid bus competition without providing a special function means in a bus arbitrating circuit even when a standard local bus is used for a processor system where the local bus of an interlock bus is connected with the system bus of a split bus through a bridge device. SOLUTION: When the request of data transfer from the split bus 1-52 to the interlock bus 1-51 is received during data transfer from the interlock bus 1-51 to the split bus 1-52, a bridge device 1-3 performs a retry request response to the interlock bus, holds address information under transfer from the interlock bus in a buffer and when the address information sent from the interlock bus again is coincident with the contents of the buffer after the data transfer from the split bus is completed, by applying the bus right to access from the interlock bus, the reception waiting state of answer transfer is provided without newly performing order transfer to the split bus.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a bus contention avoiding method in a processor system, and more particularly to a bus contention avoiding method in a processor system in which an interlock bus and a split bus are connected by a bridge device.

[0002]

2. Description of the Related Art As a technique for avoiding bus contention in a conventional processor system, there is known a technique for avoiding bus contention disclosed as a "deadlock avoidance circuit in a multiprocessor system" in Japanese Patent Application Laid-Open No. 3-189557. FIG. 18 shows a basic configuration of this conventional bus contention avoidance.

In a processor system shown in FIG. 18, a local bus of an interlock bus is connected to a system bus of a split bus via a bridge device 18-3, and the processor 18-1 and the local memory 1 are connected to the local bus.
8-2 and the like, and the processor 18-1 and the local memory 18-2 mutually transfer data with other processors and IO devices via a local bus and a system bus.
This is a system suitably applied as a multiprocessor system for improving the processing capacity of the entire system.

In such a system, a processor, a memory or an I / O is connected via a local bus and a system bus.
When data is transferred between the O-devices and the like, a bus use request is generated among a plurality of devices at the same time, and contention for a bus use right (hereinafter, referred to as a bus right) occurs.

In order to arbitrate and avoid such bus contention, a conventional bus contention avoiding means is a bridge device 1.
8-3, a local bus request guarantee circuit 18-31 and a re-registration inhibiting circuit 18-32 are provided. A bus arbitration circuit (bus arbiter) 18-4 includes a bus right return guarantee circuit 18-4.
1 was provided.

The local bus request guarantee circuit 18-31
After receiving a use request of the system bus from the processor 18-1 via the local bus and performing order transfer to the system bus of the split bus, before receiving an answer transfer for the order transfer from the system bus, Upon receiving the request to use the local bus, the processor 1 issues a local bus release request to the processor 18-1, and interrupts the transfer operation and subsequently re-executes it.
8-1.

[0007] The re-registration inhibiting circuit 18-32 responds to the command issued by the processor 18-1 by re-executing the transfer after the use of the local bus is completed by the use request from the system bus. It has a function of preventing the command from being re-registered so that the order transfer sent to the system bus and the order transfer by re-execution do not overlap.

[0008] The bus right return guarantee circuit 18-41 responds to the bus right request by the transfer operation re-executed from the processor 18-1 after the use of the local bus by the use request from the system bus ends. On the other hand, it has a function to return the bus right.

[0009]

In the conventional bus contention arbitration / avoidance means, the bus right return guarantee circuit 18-41 in the bus arbitration circuit 18-4 first makes a bus request for bus right return. Remembers the bus master that has been used and, upon a local bus use request from the system bus side, temporarily removes the bus right from the bus master in the answer transfer waiting state, and grants the bus right to the local bus use request from the system bus side to transfer data. In the bus arbitration circuit 18-4, it is necessary to provide a function of giving a bus right to the bus master in the answer transfer waiting state which has issued the bus request after the completion of the data transfer.

However, in a standard local bus such as a PCI bus, the function of a bus arbitration circuit is defined as a standard specification. A function to remember the bus master cannot be provided, and a bus arbitration circuit of a standardized specification cannot be used to arbitrate and avoid bus contention as in the prior art.

When a standard local bus is used, a retry request response to a burst write transfer composed of a plurality of micro accesses may not be made. For example, if a retransmission request response is sent in the fourth word in burst write transfer (this is called a disconnect request response), the bus master may be designed to retransmit from the fourth word. Since the access information transmitted when making a bus request is different from the access information transmitted at the time of retransmission, it is necessary to specify the bus master when re-assigning the bus right to the bus master having previously made the bus request. become unable.

According to the present invention, in a processor system in which a local bus of an interlock bus and a system bus of a split bus are connected by a bridge device, even when a standard local bus such as a PCI bus is used as a local bus, a bus arbitration circuit is provided. Without special function means,
An object of the present invention is to perform a bus right contention avoidance process similar to the conventional one.

[0013] Also, for an access for performing a burst write transfer, the bus arbiter is not provided with any special function means, and the bus master that has made the access is determined and the bus right is returned. The purpose of the present invention is to perform a right conflict avoidance process.

[0014]

According to the present invention, there is provided a bus contention avoiding method in a processor system, wherein (1) an interlock bus and a split bus are connected, and information including an access address received from the interlock bus is stored in a buffer. In a processor system having a bridge device for holding, when the bridge device receives a data transfer request from the split bus to the interlock bus during data transfer from the interlock bus to the split bus,
A retry request response is sent to the interlock bus,
In the buffer, the step of holding information including an address during data transfer from the interlock bus to the split bus, and after transferring data by accessing the interlock bus received from the split bus, again from the interlock bus Comparing information including the address of the received access with the content held in the buffer;
Receiving a data from the interlock bus when the match is detected by the comparison, and waiting for answer transfer reception without newly performing order transfer to the split bus.

(2) When the comparison detects a mismatch between the information including the address of the access received from the interlock bus and the content held in the buffer, a retry request response to the access is detected. And rejecting data reception from the interlock bus.

(3) When the comparison detects that the information including the access address received from the interlock bus matches the contents held in the buffer, the contents of the buffer are erased. And a step of invalidating the comparison step.

(4) When a data transfer request from the split bus to the interlock bus is received during a burst write transfer from the interlock bus to the split bus, which consists of a plurality of microaccesses with consecutive addresses. Sending a retransmission request response to the interlock bus, and holding, in the buffer, information including an address related to the access that made the retransmission request response; and data obtained by accessing the interlock bus received from the split bus. And then comparing the information including the address of the access received from the interlock bus again with the contents held in the buffer, and receiving the data from the interlock bus when a match is detected by the comparison. And an answer without new order transfer to the split bus. It is intended to include the steps of a reception waiting state of the transmission.

(5) If the comparison in (4) detects a mismatch between the information including the address of the access received from the interlock bus and the content held in the buffer, It includes a process of responding to a retry request and rejecting data reception from the interlock bus.

(6) If the comparison in (4) detects a match between the information including the access address received from the interlock bus and the content held in the buffer, the content of the buffer is determined. Erasing and invalidating the comparison process.

(7) Data transfer from the split bus to the interlock bus during the burst write transfer of a specific access composed of a plurality of macro accesses whose addresses are not consecutive from the interlock bus to the split bus. When receiving the request, responding to the interlock bus with a retransmission request response, and holding, in the buffer, information including an address in the first word of the burst data that has responded to the retransmission request, and receiving the request from the split bus. After transferring the data obtained by accessing the interlock bus, comparing the information including the address of the access received from the interlock bus again with the content held in the buffer, and when a match is detected by the comparison. In addition to receiving data from the interlock bus, To those newly including the steps of a reception waiting state of the answer transfer without order transfer.

(8) Notifying the bridge device of the arbitration result of the bus contention by the arbitration circuit in the interlock bus, and the bridge device identifies the bus master based on the arbitration result, and Judging the access to be received as the specific access.

(9) The bridge device identifies a bus master notified by an individual line from a device capable of performing burst write transfer in which addresses are continuous and burst write transfer in which addresses are not continuous, and receives from a specific bus master. Determining the access to be performed is the specific access.

(10) The bridge device determines an address space of transfer data on the basis of address information of a head micro-access transferred on the interlock bus, and determines the identification based on the determination of the address space. This includes the process of determining access.

(11) In response to a retransmission request for burst write transfer of a specific access composed of micro-accesses whose addresses are not continuous from the interlock bus to the split bus, the bus master receiving the retransmission request response This includes a process of returning retransmission data of only one word data.

[0025]

FIG. 1 shows an example of the basic configuration of a processor system according to the present invention. In the figure, 1-1 is a processor, 1-2 is a memory, 1-3 is a bridge device, 1-4
₁ The first IO device 1-4 ₂ second IO device, 1-
5 ₁ interlock bus (local bus) that connects the processor and memory, and the bridge device 1-5 ₂ split bus (system bus) for connecting the bridge device and the IO device, 1-6 ₁ interface A first bus arbitration circuit that performs bus arbitration of the lock bus, and a second bus arbitration circuit that performs bus arbitration of the split bus 1-6 ₂ .

FIGS. 2 and 3 are time charts of an example of data transfer on the interlock bus. A typical example of the interlock bus is a PCI bus. 2 and 3 show an example of one-word write transfer.

The interlock bus is capable of responding to the Frame line indicating the head data position of the bus transfer, the Irdy line indicating the initiator side (bus master side) ready to use the bus, and the response side (bus slave side). A Devsel line to indicate that there is, a Trdy line to indicate that the responding side has completed the final data reception, a Stop line to indicate a retry request response from the responding side, an Ad line to which addresses and data are multiplexed and transferred, A C / BE line to which a command and a byte enable signal are transferred;

In the interlock bus, if either the Frame line or the Irdy line is asserted, it is a transfer cycle. In the first cycle of the transfer cycle, Ad
The transfer address (32 bits) is displayed on the line, and C / BE
The line displays the command.

The bus master asserts the Frame signal and waits for the return of the Devsel signal. The bus slave decodes the transfer address, and when responding to the transfer address, asserts the Devsel signal and notifies the completion of writing by asserting the Trdy signal (normal com).
pletion). When the bus slave responds to the retry request, as shown in FIG.
Notification is made by asserting the p signal.

FIG. 4 shows a time chart of an example of split bus data transfer. In the split bus, data is transferred separately in order transfer and answer transfer. During the period between the order transfer and the answer transfer, another bus master can transfer data using the split bus.

In FIG. 4, for example, when the bridge device sends a split bus use request Req0, the bus arbitration circuit notifies the bridge device of a grant signal Gnt0 indicating permission of bus use in response to the request, and grant signal Gn
The bridge device notified of t0 asserts the system bus start signal Sbs and the system bus block signal Sbk, and transfers the SCAD signal including the command (C), the address (A), and the data (D) in order.

Next, when the order transfer is received, for example, the first
Sends a split bus use request Req1, and upon receiving a grant signal Gnt1 indicating bus use permission from the bus arbitration circuit in response to the request, the first IO
The device similarly asserts the system bus start signal Sbs and the system bus block signal Sbk to perform an answer transfer of the SCAD signal including the command (C) and the address (A).

FIG. 5 shows a first operation example of the bus right contention avoidance in the present invention. The processor 5-1 is a bridge device 5.
-3, the write transfer to the _first IO device 5-41 is performed. The second IO device 5-4 _2, memory 5-2
Shall be performed.

The bridge device 5-3 receives a write transfer request from the processor 5-1 via the interlock bus ().
Then, the Devsel signal is asserted, and split bus order transfer () is performed.

The split bus is connected to the first IO device 5-4.
Before receiving the answer transfer from ₁ , the second IO device 5-
Receiving a data transfer request to the memory 5-2 4 ₂ ()
May be.

In this case, the bridge device 5-3 sends a retry request response () to the processor 5-1 that has completed the order transfer and is in the answer transfer waiting state, and also requests the release of the interlock bus.

At this time, the bridge device 5-3 holds access information including the address being received from the processor 5-1 in a buffer in the bridge device. The processor 5-1 that has received () the retry request response once releases the occupation of the interlock bus, and then requests the use of the bus again.

[0038] After the bridge device 5-3 to obtain the right to use the interlock buses, memory from the second IO device 5-4 ₂ 5
-2, and the interlock bus is released after completion of the write transfer ().

After releasing the interlock bus, the processor 5-1 requests the use of the bus and obtains the bus right.
Rerun () a write transfer to the IO device 5-4 _1. The bridge device 5-3 compares the address information in the write transfer due to the re-execution with the address information held in the buffer in the previous write transfer, and confirms that the address information matches the address information.
asserting el signal, but without a new order transfer to avoid duplication of already went order transfer for the split bus, the answer transfer waiting state from the first IO device 5-4 ₁ I do.

Thereafter, upon receiving the answer transfer from the split bus (), the bridge device 5-3 returns a Trdy signal (normal completion) to the interlock bus (), and terminates the data transfer requested by the processor 5-1. I do.

As described above, in the bridge device for connecting the interlock bus and the split bus, the bridge device has the buffer for holding the information including the address of the access received from the interlock bus, and switches from the interlock bus to the split bus. When a data transfer request from the split bus to the interlock bus is received during data transfer to the interlock bus, a retry request response is sent to the interlock bus, and the buffer transfers the address transferred from the interlock bus to the split bus. After holding the access information including the access information and transferring the access to the interlock bus received from the split bus, the access information received from the interlock bus is again compared with the content held in the buffer. , Accepts access from the interlock bus, and And waits answer transferred without new orders transferred to Ttobasu.

By providing such a function in the bridge device, the bridge device knows that the access received from the interlock bus is a retry access by the original bus master, and avoids processing inconsistency due to bus contention. be able to.

Therefore, in a processor system using a standardized bus arbitration circuit, conflict of bus rights can be avoided as in the prior art, without providing special function means in the bus arbitration circuit. FIG. 6 shows a second operation example of the bus right contention avoidance in the present invention. In the operation example shown in FIG. 5, when the first processor (P1) and the second processor (P2) are connected to the interlock bus, the first processor (P1) releases the bus right. Then, before the bridge device acquires the bus right, there may be a case where the second processor (P2) acquires the bus right and performs access via the bridge device. FIG. 6 shows such a case.

In such a case, the bridge device 6-3
In response to the access () from the _second processor (P ₂ ) 6-12, the Devsel signal is once asserted. However, since the address information of the access is different from the address information held in the buffer, the retry request response ( ).

The second processor (P2) 6-1 ₂ that has received the retry response request () from the bridge device 6-3.
Since the bus right is once released, the bus right is passed to the bridge device 6-3 requesting the bus right. Therefore, even in such a case, the contention of the bus right can be avoided without providing any special function means in the bus arbitration circuit.

That is, in the prior art, the bus arbitration circuit operates the bus right by the bus right return guarantee circuit, transfers the bus from the split bus to the interlock bus, and then gives the bus right to the original bus master. The other bus master did not transfer to the bridge device.

On the other hand, the present invention, as a method for avoiding such a contention, employs a retry when the access information received from the interlock bus does not match the address information held in the buffer in the bridge device. By performing a request response, access is not received from the interlock bus.

Retry is repeated for subsequent access information mismatches, and the bus right is passed to the access () from the original bus master whose access information matches, and the retry access by the original bus master is executed. .

In response to the data transfer of the _first processor (P1) 6-11, the bridge device 6-3, which has received the answer transfer () from the split bus, sets the T to the interlock bus.
At the same time, the rdy signal is returned (), and the contents held in the buffer are erased to invalidate the operation of the access information comparison processing. As a result, the second processor (P2) 6-
12 _{acquires the} bus right and can access () via the bridge device 6-3.

Thus, the first processor (P1) 6
-1 ₁ when data transfer split bus f is finished by, returns a response by Trdy signal to interlock bus, by disabling the comparison of buffer contents and access information of the bridge device 6-3 described above in this case After the data transfer from the interlock bus to the split bus by the original bus master is completed, other bus masters connected to the interlock bus can use the bus.

That is, contention for the split bus by a plurality of bus masters connected to the interlock bus is avoided in the same manner as in the prior art without adding any special function to the arbitration circuit, and each bus master is connected to the split bus. Data can be transferred to

Next, conflict avoidance in the case of burst transfer according to the present invention will be described. FIGS. 7 and 8 are time charts of an example of burst transfer in the interlock bus. FIG. 7 shows an example of 4-word write transfer, and FIG. 8 shows a case where a disconnect request response is made in the transfer.

The Frame line is negated (invalidated) with the final data. In the first cycle of the transfer cycle, the transfer address (32 bits) is displayed on the Ad line. Also C /
Commands are displayed on the BE line.

Since the bridge device performs the order transfer to the split bus, it is necessary to receive all the write data from the interlock bus. Therefore, as shown in FIG. 7, in the case of four-word write transfer, Trdy for three words is used.
Signal, and the fourth word Trdy signal is returned after receiving the answer transfer from the split bus (norm
al completion). On the other hand, when the disconnect request response is performed, as shown in FIG. 8, the notification is made by the Stop signal instead of the Trdy signal.

FIG. 9 shows a third example of operation for avoiding bus contention according to the present invention. The processor 9-1 performs a write transfer to the _first IO device 9-41 via the bridge device 9-3. The second IO device 9-4 ₂ memory 9-2
Shall be performed.

The bridge device 9-3 includes a processor 9-1.
Receives a 4-word write transfer () from Devsel
Assert the signal and perform split bus order transfer. Before receiving the answer transfer from the split bus for the order transfer, the bridge device 9-3 performs the second I
Sometimes from O device 9-4 ₂ receives the transfer request of the memory 9-2 f.

In this case, the bridge device 9-3 sends di to the processor 9-1 connected to the interlock bus.
A connection request response () is performed, and a bus right of the interlock bus is requested.

At this time, the bridge device 9-3 sets the address information (a) being received from the processor 9-1 to the address (`12`) of three words (one word is assumed to be four bytes). The added value (a + '12 ') is held in the buffer.

Then, the disc is sent from the bridge device 9-3.
The processor 9-1 receiving the connect request response,
The bus right is released once, and then the bus right is requested again.
By releasing the bus right of the processor 9-1, the bridge device 9 is released.
-3, after obtaining the bus right, performs a write transfer () from the _second IO device 9-42, and releases the bus right after the transfer.

After the processor 9-1 obtains the bus right again,
The write transfer () to the _first IO device 9-41 is performed.
The write transfer address at this time is disconnect.
Address (a + '1) for the data that received the request response
2 ').

When the bridge device 9-3 confirms that the address information matches the address information held in the buffer,
Assert the evsel signal, but do not perform a new order transfer to the split bus.

Then, when receiving the answer transfer () from the split bus, the bridge device 9-3 returns a Trdy signal (normal completion) to the interlock bus (), and ends the data transfer.

When the transfer from the interlock bus to the split bus is a burst write transfer, or when the transfer from the split bus to the interlock bus is received during the transfer from the interlock bus to the split bus, for example, four words When a normal response is returned for the first to third words of the write transfer, even if a retry request response is returned for the fourth word, it may be retransmitted from the fourth word. This is based on the standardized specification of the interlock bus.

For such a burst write transfer,
Even if the received address or the like is stored in the buffer, it does not match the address at the time of retry access. Therefore, in the case of the burst write transfer, the disc is connected to the interlock bus.
A connect request response is performed, and address information and the like for the last word are held.

With this function, the bridge device can correctly recognize the retry access, and it is possible to avoid the same contention of the bus right as in the related art without providing any special function means in the bus arbitration circuit.

In the case of the burst transfer described above, when the first processor (P1) and the second processor (P2) are connected to the interlock bus, the first processor (P1) releases the bus. It is possible that the second processor (P2) obtains the bus right and performs access via the bridge device from the time until the bridge device obtains the bus right. The fourth operation example shown in FIG. 10 is an operation example in such a case.

In such a case, the bridge device 10-3
Asserts the Devsel signal once for the access () from the _second processor (P2) 10-12, but since the address information of the access is different from the address information already held in the buffer, the retry request Returns a response ().

The second processor (P2) 10-1 having received the retry request response () from the bridge device 10-3
₂ is a bridge device 10- for temporarily releasing the bus right.
3 bus rights will be passed. Therefore, even in such a case, the contention of the bus right can be avoided as in the related art without providing any special function means in the bus arbitration circuit.

In other words, even in such a case, if the access information received from the interlock bus and the address information in the buffer do not match, a retry request response is made, and no access is accepted from the interlock bus. By doing so, retry is repeated for a subsequent access by bus arbitration for an address information mismatch, and a bus right is passed to an access () from the original bus master whose address information matches, and Retry access is performed.

In the operation example shown in FIG. 10 described above, the bridge device 10-3 which has received the answer transfer () from the split bus in response to the data transfer of the _first processor (P1) 10-11 is interlocked. A Trdy signal is returned to the bus (), and the above-described comparison of the held contents of the buffer and the address information is invalidated. As a result, second processor (P2) 10-1 ₂ is to give a bus right, access via bridge device 10-3 () it is possible to perform.

As described above, after the transfer to the split bus is completed, when the response is returned to the interlock bus, the contents of the buffer and the like are invalidated. Can transfer data to the split bus using the interlock bus.

FIG. 11 shows a fifth operation example of the bus right contention avoidance in the present invention. This operation example illustrates an operation example in which the second processor (P2) performs burst write transfer in which addresses and data are not paired.

After the data transfer of the _first processor (P1) 11-11 is completed, the second processor (P2) 11
-1 ₂ performs the first IO device 11-4 ₁ f burst write transfer via the bridge device 11-3. Also, the second
The IO device 11-4 ₂ will be made a write transfer to the memory 11-2.

[0074] Bridge device 11-3 receives the second processor (P2) 11-1 ₂ from 4-word write transfer (), asserts Devsel signal, performs an order Transfer () to the split bus. Then, before receiving the answer transfer from the split bus, the second IO device 11-4
₂ to the memory 11-2.

In such a case, the bridge device 11-3
It is for the second processor (P2) 11-1 _2, di
A connection request response () is performed, and a bus right of the interlock bus is requested. Then, the time the second processor (P2) the address information in the received from 11-1 ₂ (a) holds the buffer.

A disconnect request response has been received.
Second processor (P2) 11-1 _Two Once got the bus right
Release and then request the bus right again. Bridge device
After the 11-3 has obtained the bus right, the second IO device 11-4_Two 
Write transfer () from the
Release the bus right of the lock bus.

[0077] The second processor (P2) 11-1 ₂ is,
After obtaining the bus right again, burst write transfer () to the first IO device 11-4 is performed. However, it is assumed that the burst write transfer address at this time is the address (a) for the head data of the data transfer that has received the disconnect request response.

When the bridge device 11-3 confirms that the address information matches the address information held in the buffer,
Assert the sel signal, and wait for answer transfer without performing new order transfer to the split bus.

When the transfer data and the address in the burst write transfer are not paired, the bus master that has received the disconnect request response other than the first word cannot calculate the retransmission address. For example,
This is a case in which data in a register corresponding to a plurality of scattered addresses is transferred in one burst write transfer.

Normally, the bus master performing such burst write transfer cannot receive the disconnect request response, so that it is impossible to avoid the conflict as in the prior art. Therefore, for a specific access composed of a plurality of micro accesses in which such addresses are not continuous, d is a value other than the first word of the burst write transfer.
The bus master receiving the disconnect request response,
The retry is performed based on the start address, and the bridge device side can hold the information including the address of the start word in the buffer, thereby making it possible to avoid the same conflict.

Therefore, even in such a case, a specific access composed of a plurality of micro accesses having non-consecutive addresses is identified, and the information including the address of the first word is stored in the buffer of the bridge device in response to the specific access. Is provided, the bus arbitration circuit can be provided with no special function means, and thus, it is possible to avoid the conflict of the bus rights.

In the above-described system configuration, the bus master connected to the general-purpose local bus normally conforms to the local bus specification. Therefore, it is determined whether or not the specific access in which the address and the data are not continuous as described above is performed. , Can be identified by the attributes of the bus master connected to the local bus.

Therefore, by identifying an access received from a specific bus master as a specific access,
It is possible to avoid bus contention in a system in which a bus master in which addresses and data are continuous and a bus master in which addresses and data are not continuous are mixed.

As a first method of identifying the bus master, the bridge device can notify the bridge device of the arbitration result in the arbitration circuit, thereby identifying the bus master and determining the specific access from the result.

FIG. 12 is a block diagram of the bus master notification of the present invention by the arbitration control line of the interlock bus. FIG. 13 shows a time chart of the arbitration operation in the interlock bus. When the first processor (P1) 12-1 ₁ requests the bus right, to the arbitrating circuit 12-2, a bus right request signal including the identification information of the processor req_P1
Assert The second processor (P2) 12
When -1 ₂ requests the bus right, likewise asserts the bus request signal req_P2 including the identification information of the processor.

The arbitration circuit 12-2 has one processor, for example, a first processor (P
1) to 12-1 _1, it asserts the grant signal gnt_P1 a bus grant signal including the identification information of the processor, the first processor for example given the bus (P1) is the grant signal gnt_P1 After receiving, the Frame signal and the Irdy signal are asserted to transfer the data, and the Devsel signal and the Trd signal from the responding side are transmitted.
The data transfer is completed by the assertion of the y signal. In addition,
When giving the bus right for the second processor (P2) 12-1 _2, grant signal gnt_P2 including identification information of the processor is asserted.

The bridge device 12-3 includes an arbitration circuit 12-
2, the bus master can be specified by taking in these grant signals gnt_P1 and gnt_P2 sent out from the second and analyzing the identification information of the processor and the like included in the signals.

When a plurality of bus masters are mounted on one local bus interface, the specific access described above may not be able to be identified simply by identifying the bus master.
For example, there is a case where a bus master having continuous addresses and data and a bus master having non-continuous addresses coexist under the lower bridge device.

FIG. 14 shows a first configuration example in which a plurality of processors are connected to an interlock bus via a lower bridge device. First processor (P1) 14-1
The _first and second processor (P2) 14-1 ₂ and a local bus 14-5 _3, is connected to the lower bridge device 14-3 _1, the lower bridge device 14-3 ₁ and the memory 14
2 and is connected to the upper bridge devices 14-3 ₀ by a local bus (interlock bus) 14-5 _1, the upper bridge device 14-3 ₀ is further connected to other devices via a system bus 14-5 ₂ Shall be.

[0090] lower bridge device 14-3 _1, the arbitration circuit 14-6 ₁ provided to the local bus 14-5 ₃
From the arbitration result, the bus master can be specified. However, a local bus (interlock bus) 14-5 ₁ side via the lower position the bridging device 14-3 _1, the bus request signal req_B1 and grant signal gnt_B1 including identification information of the lower level bridge device 14-3 ₁ since summarized upper bridge device 14-3 _0, first
Since the processor (P1) 14-1 ₁ and the second processor (P2) 14-1 can not be determined whether the access from any _2, it is impossible to identify a particular access described above.

[0091] Therefore, the lower bridge device 14-3 _1,
Grant signals gnt_P1 and gnt_P2 for the first and second processors in the same manner as the method described with reference to FIG.
Retraction, to identify the bus master by the grant signal line, by relaying via the individual line 14-7 results identified to the host bridge device 14-3 _0, the upper bridge device 14-3 _0, identifies the master Can be
It is possible to identify whether the transfer on the interlock bus is the specific access described above.

In this case, the lower bridge device 14-3 ₁
Indicates the individual line 1 when transferring as a local bus master.
4-7 to display information indicating whether the access or not the address and data are continuous, the upper bridge device 14-3 _0, and identifies configure whether specific access by the display of the individual line 14-7 be able to.

FIG. 15 shows a second configuration example in which a plurality of processors are connected to an interlock bus via a lower bridge device. The method of identifying specific access described above is:
The upper bridge device 14-3 ₀ and the lower bridge device 14-
Between 3 ₁ and, in addition to a separate individual lines of the interlock bus 1
4-7, but the above individual line may not be added due to local bus regulations.
When you use a generic bridge LSI or the like in the lower bridge device 14-3 _1, it is impossible to separately provide a dedicated line.

In such a case, in the above-described configuration, the lower bridge device cannot notify the upper bridge device of the specific access. Therefore, usually, when a space where addresses and data are continuous is defined as a memory space, and a non-contiguous space is defined as a control space, the address assignment does not overlap. Can be determined.

That is, as shown in FIG. 15, the interlock bus is drawn into the address decoder 15-7, which decodes the address information transmitted on the interlock bus, and stores the address in the memory space. to determine what things or control space of the upper bridge device 15-3 ₀ based on該判specific information can be transferred in the interlock bus to determine whether or not a particular access described above. In FIG. 15, the same components as those shown in FIG. 14 are denoted by the same reference numerals, and duplicate description will be omitted.

FIG. 16 shows an example of address space mapping. Address '0000 0000 _H ' to '7FFF FFFF _H '
The address space (2 GB) is a memory space in which addresses and data are paired, and the burst write transfer of the address space is a memory space (access to the memory).

Further, addresses' 8000 0000 _H 'to' 100
The address space (2 GB) of 0 000 _H ′ is a control space in which addresses and data are not paired, and the burst write transfer of the address space is a control space (access to a register or the like).

As shown in FIG. 16, normally, the memory space and the control space are completely separated from each other and do not overlap. Therefore, the upper bridge device 15-3 _0, by analysis of the address by the address decoder 15-7,
Interlock bus 14-5 on _one transfer, to identify whether those things or control space of the memory space, it is possible to determine whether a particular access described above. When the address space can be identified by a command like a PCI bus, it can be similarly determined whether or not a specific access is made by analyzing the command.

Returning to the fifth operation example of the bus right contention avoidance in the present invention shown in FIG. 11, the bus master (the second processor 11-) receiving the disconnect request response () from the interlock bus. 1 ₂ )
After the bus is released, all the same data as already transmitted () are retransmitted () to the bridge device 11-3.

However, since the bridge device 11-3 has already received the write data of the corresponding access and completed the order transfer () of the data to the split bus, the retransmission data is unnecessary. Therefore, by not resending such unnecessary data,
The waiting time can be reduced and the bus use efficiency can be improved.

FIG. 17 shows a sixth example of operation for avoiding bus contention according to the present invention which prevents such unnecessary data retransmission. In FIG. 17, the operation of is the same as the operation of FIG. 11 shown in FIG. In the sixth operation example, di
sconnect request response () master (second processor 11-1 ₂₎ which received as retransmission data, retransmits only arbitrary one word data such as null data ( ') and that the waste on interlock bus It is not necessary to perform a complicated data cycle, and the time can be reduced and the processing efficiency can be improved.

[0102]

As described above, according to the present invention,
In a processor system in which a local bus of an interlock bus and a system bus of a split bus are connected by a bridge device, the bridge device includes a buffer for holding information including an address of an access received from the interlock bus. After responding to the retry request, the information including the address of the access received from the interlock bus is compared again with the content held in the buffer, and the bus arbitration circuit is specially given by granting the bus right to the matching access. The bus right contention avoidance processing can be performed without providing any functional means.

Also, for a burst write transfer including a specific access composed of a plurality of micro-accesses whose addresses are not consecutive, the bus arbitration circuit is specially designated by identifying a bus master or an address space in the bridge device. It is possible to correctly determine the bus master that has performed the burst transfer for the retransmission request, return the bus right, and perform the bus right contention avoidance processing without providing any functional means.

[Brief description of the drawings]

FIG. 1 is a diagram showing a basic configuration example of a processor system of the present invention.

FIG. 2 is a time chart of an example of data transfer on an interlock bus.

FIG. 3 is a time chart of an example of a data transfer (retry request response) of an interlock bus.

FIG. 4 is a time chart of an example of split bus data transfer.

FIG. 5 is a diagram illustrating a first operation example of avoiding bus contention according to the present invention;

FIG. 6 is a diagram showing a second operation example of avoiding bus contention in the present invention.

FIG. 7 is a time chart of an example of a burst transfer in an interlock bus.

FIG. 8 shows an example of a burst transfer in an interlock bus (d)
6 is a time chart of an disconnect request response).

FIG. 9 is a diagram showing a third operation example of avoiding bus contention in the present invention.

FIG. 10 is a diagram showing a fourth operation example of avoiding bus contention according to the present invention.

FIG. 11 is a diagram illustrating a fifth operation example of avoiding bus contention according to the present invention.

FIG. 12 is a configuration diagram of a bus master notification of the present invention by an arbitration control line of an interlock bus.

FIG. 13 is a time chart of the arbitration operation in the interlock bus.

FIG. 14 is a diagram illustrating a first configuration example in which a plurality of processors are connected via a lower bridge device.

FIG. 15 is a diagram illustrating a second configuration example in which a plurality of processors are connected via a lower bridge device.

FIG. 16 is a diagram illustrating an example of address space mapping.

FIG. 17 is a diagram showing a sixth operation example of avoiding bus contention in the present invention.

FIG. 18 is a basic configuration diagram of conventional bus contention avoidance.

[Explanation of symbols]

1-1 Processor 1-2 Memory 1-3 Bridge device 1-4 ₁ First IO device 1-4 ₂ Second IO device 1-5 ₁ Interlock bus ( ₁₎ for connecting a processor, a memory, etc., and a bridge device ( local bus) 1-5 ₂ bridge and split-bus (system bus connecting the IO device, etc.) 1-6 ₁ first bus arbitration circuit 1-6 ₂ split bus bus arbitration performing bus arbitration interlocking bus Bus arbitration circuit that performs

Claims (11)

[Claims] 1. A processor system comprising a bridge device for connecting an interlock bus and a split bus and holding information including an access address received from the interlock bus in a buffer, wherein the bridge device includes an interlock bus. If a data transfer request from the split bus to the interlock bus is received during data transfer from the split bus to the split bus, a retry request response is sent to the interlock bus, and the buffer is sent from the interlock bus to the split bus. Holding the information including the address during the data transfer to the interlock bus, transferring the data by accessing the interlock bus received from the split bus, and then re-entering the information including the address of the access received from the interlock bus and the buffer. Compare with the contents stored in And receiving data from the interlock bus and, when a match is detected by the comparison, waiting for answer transfer reception without performing new order transfer to the split bus. Bus contention avoidance method in a processor system. 2. If the comparison detects a mismatch between information including an access address received from the interlock bus and the content held in the buffer, a retry request response is made to the access. 2. The method of claim 1, further comprising the step of rejecting data reception from the interlock bus. 3. When the comparison detects a match between the information including the access address received from the interlock bus and the content held in the buffer, the content of the buffer is erased. 2. The method of claim 1, further comprising the step of invalidating the step. 4. When a data transfer request from a split bus to an interlock bus is received during a burst write transfer from the interlock bus to the split bus, the burst write transfer comprising a plurality of addresses having consecutive addresses,
Sending a retransmission request response to the interlock bus, retaining information including an address related to the access that made the retransmission request response in the buffer, and transferring data by accessing the interlock bus received from the split bus And then comparing the information including the address of the access received from the interlock bus again with the content held in the buffer, and receiving data from the interlock bus when a match is detected by the comparison. 2. The bus contention avoiding method in the processor system according to claim 1, further comprising: a step of waiting for answer transfer reception without newly performing order transfer to the split bus. 5. When the comparison detects a mismatch between the information including the address of the access received from the interlock bus and the content held in the buffer, a retry request response is made to the access, and 5. The method according to claim 4, further comprising the step of rejecting data reception from the lock bus. 6. When the comparison detects a match between the information including the access address received from the interlock bus and the contents held in the buffer, the contents of the buffer are erased, and the comparing step is performed. 5. The method according to claim 4, further comprising the step of invalidating the bus contention. 7. A data transfer request from a split bus to an interlock bus is received during a burst write transfer of a specific access composed of a plurality of macro accesses whose addresses are not consecutive from the interlock bus to the split bus. Responding to the interlock bus, responding to the interlock bus, and holding, in the buffer, information including the address of the first word of the burst data that has responded to the retransmission request; A step of comparing data including the address of the access received from the interlock bus with the contents held in the buffer after transferring the data by accessing the bus, and, when a match is detected by the comparison, While receiving data from the lock bus, a new split bus Bus conflict avoidance method in a processor system according to claim 1, characterized in that it comprises the steps of a reception waiting state of the answer transfer without over da transfer, a. 8. A process of notifying the arbitration result of the bus contention by the arbitration circuit in the interlock bus to the bridge device, and based on the arbitration result, the bridge device identifies a bus master and an access received from a specific bus master. And determining the specific access as the specific access. 8. The method according to claim 7, further comprising: 9. The bridge device identifies a bus master notified by an individual line from devices capable of performing burst write transfer in which addresses are continuous and burst write transfer in which addresses are not continuous, and performs access received from a specific bus master. 8. The bus contention avoiding method in a processor system according to claim 7, comprising a step of determining the specific access. 10. The bridge device determines an address space of transfer data based on address information of a head micro access transferred on the interlock bus, and determines the specific access based on the determination of the address space. 9. The method of claim 7, further comprising the step of: 11. A bus master receiving a retransmission request response to a retransmission request for a burst write transfer of a specific access composed of micro-accesses whose addresses are not continuous from the interlock bus to the split bus,
8. The bus contention avoiding method in a processor system according to claim 7, further comprising a step of returning retransmission data of only word data.