JP2001057513A - Agc circuit and method for its gain control - Google Patents

Agc circuit and method for its gain control

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Publication number
JP2001057513A
JP2001057513A JP11231191A JP23119199A JP2001057513A JP 2001057513 A JP2001057513 A JP 2001057513A JP 11231191 A JP11231191 A JP 11231191A JP 23119199 A JP23119199 A JP 23119199A JP 2001057513 A JP2001057513 A JP 2001057513A
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JP
Japan
Prior art keywords
signal
power
gain
value
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11231191A
Other languages
Japanese (ja)
Inventor
Masayuki Kanazawa
昌幸 金澤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Denshi KK
Original Assignee
Hitachi Denshi KK
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Filing date
Publication date
Application filed by Hitachi Denshi KK filed Critical Hitachi Denshi KK
Priority to JP11231191A priority Critical patent/JP2001057513A/en
Publication of JP2001057513A publication Critical patent/JP2001057513A/en
Pending legal-status Critical Current

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  • Control Of Amplification And Gain Control (AREA)
  • Noise Elimination (AREA)
  • Circuits Of Receivers In General (AREA)

Abstract

PROBLEM TO BE SOLVED: To obtain an optimum gain for a desired wave even when an adjacent channel interference wave is inputted to a receiver by calculating the difference between the power of a signal to be inputted to a band-pass filter(BPF) and the power of its output signal and adding a correction value corresponding to the magnitude of this differential signal to the input of an integrator. SOLUTION: The power of an input signal of a BPF 3 is detected, the power of an output signal of the BPF 3 is also detected, power values calculated by the respective detections are inputted to an adder 8-3 to calculate the difference between the both, a controller 13 outputs a gain correction signal by this differential signal to be added to an integrator 9, and the control gain of an automatic gain control(AGC) circuit 4 is adjusted. According to this configuration, it is possible to obtain an optimum gain for a desired wave all the time even when an adjacent channel interference wave is inputted to a receiver because the control gain is corrected by calculating the difference between the input and output powers of the BPF 3 and adding a correction signal corresponding to this differential signal to the integrator 9.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明はAGC(Auto Gain con
trol:自動利得制御)回路に関し、特にディジタル移動
体通信等の受信装置に用いられるAGC回路の改良に関す
るものである。
[0001] The present invention relates to an AGC (Auto Gain con
The present invention relates to a trol (automatic gain control) circuit, and more particularly to an improvement of an AGC circuit used in a receiving apparatus such as a digital mobile communication.

【0002】[0002]

【従来の技術】多値QAM等の線形変調方式を用いたディ
ジタル移動体通信用受信機においては、受信電力の距離
的な減衰やフェージングによる受信電力の変動による受
信品質の低下を回避するため、受信電力の変動を補償し
て所定電力値に自動的に調整するAGC(Auto Gain contr
ol:自動利得制御)回路が用いられる。
2. Description of the Related Art In a digital mobile communication receiver using a linear modulation method such as multi-level QAM, in order to avoid a decrease in reception quality due to a reception power fluctuation due to a distance attenuation of reception power or fading, AGC (Auto Gain contr) that compensates for fluctuations in received power and automatically adjusts to a predetermined power value
ol: automatic gain control) circuit.

【0003】従来のAGC回路を図2によって説明する。
図2は、ディジタル無線用受信機に用いられるフィード
バック方式のAGC回路の構成を示すブロック図である。1
-1と1-2は入力端子、2は出力端子、3-1は帯域制限フィ
ルタ(BPF)、4は可変利得増幅器、5は検波器、6-1はA/
D変換器、7は電力算出部、8-1は加算器、9は積分器、10
はD/A変換器である。図2において、アンテナで受信さ
れて中間周波数帯の信号に周波数変換された中間周波受
信信号(受信IF信号)が入力端子1-1を介して可変利得
増幅器4に入力する。可変利得増幅器4は、D/A変換器10
から入力される利得制御信号により、入力端子1-1から
の入力信号の電力が所定の基準値P0となるように利得調
節されてBPF3に送られる。BPF3において入力信号から希
望波以外の妨害波成分を帯域制限された信号は、検波器
5に送られ検波される。検波器5で検波された信号はA/D
変換器6-1でデジタル信号に変換され出力端子2から、例
えば復調処理部に、出力される。
A conventional AGC circuit will be described with reference to FIG.
FIG. 2 is a block diagram showing a configuration of a feedback type AGC circuit used in a digital wireless receiver. 1
-1 and 1-2 are input terminals, 2 is an output terminal, 3-1 is a band limiting filter (BPF), 4 is a variable gain amplifier, 5 is a detector, 6-1 is A /
D converter, 7 is a power calculator, 8-1 is an adder, 9 is an integrator, 10
Is a D / A converter. In FIG. 2, an intermediate frequency reception signal (reception IF signal) received by an antenna and frequency-converted into an intermediate frequency band signal is input to a variable gain amplifier 4 via an input terminal 1-1. The variable gain amplifier 4 includes a D / A converter 10
The gain control signal input from the power of the input signal from the input terminal 1-1 is sent to BPF3 are gain adjusted to a predetermined reference value P 0. In BPF3, the signal of which the band of the interference signal other than the desired signal is band-limited from the input signal is
It is sent to 5 and detected. The signal detected by detector 5 is A / D
The signal is converted into a digital signal by the converter 6-1 and output from the output terminal 2 to, for example, a demodulation processing unit.

【0004】また、A/D変換器6-1の出力は、電力算出部
7にも送られる。電力算出部7では、入力した信号の電力
値P1を算出して加算器8-1の負(減算)入力側に出力す
る。一方、加算器8-1の正(被減算)入力側には、入力
端子1-2を介して、入力信号電力の基準値P0が入力され
る。加算器8-1では、この入力信号の基準電力値P0
ら、入力した信号の電力値P1を減算した誤差信号( P0
- P1 )を出力する。この誤差信号は積分器9に入力され
て積分処理された後、D/A変換器10に出力される。D/A変
換器10は、積分器9の出力に基いて可変利得増幅器4に制
御信号を出力して可変利得増幅器4の利得を設定する。
[0004] The output of the A / D converter 6-1 is supplied to a power calculator.
Also sent to 7. The power calculation unit 7 calculates the power value P 1 of the input signal and outputs the negative (subtraction) input of the adder 8-1. On the other hand, the positive adder 8-1 (minuend) input via the input terminal 1-2, the reference value P 0 of the input signal power is inputted. The adder 8-1 outputs an error signal (P 0) obtained by subtracting the power value P 1 of the input signal from the reference power value P 0 of the input signal.
- Output P 1). This error signal is input to the integrator 9 and integrated, and then output to the D / A converter 10. The D / A converter 10 outputs a control signal to the variable gain amplifier 4 based on the output of the integrator 9, and sets the gain of the variable gain amplifier 4.

【0005】以上により、受信機の入力信号が変動した
場合でも入力信号の電力が一定になるように可変利得増
幅器4のフィードバック制御がなされる。
[0005] As described above, the feedback control of the variable gain amplifier 4 is performed so that the power of the input signal becomes constant even when the input signal of the receiver fluctuates.

【0006】しかし図3(a)に示すように、前述の技術
では、受信する目的の信号(希望波:中心周波数f0)の
電力PS[dBm]に比べて、隣接する無線チャネルからの
妨害波(隣接チャネル妨害波:中心周波数f1)の電力Pd
[dBm]が受信機の選択度(隣接チャネル妨害波に対す
るBPF3の減衰量L[dB])よりも大きい場合、BPF3出力
は図3(b)に示すように、希望波電力PSと妨害波に対す
るBPF3の抑圧残Pe( Pe= Pd - L)の合成となる。図3
はBPF3に入力と出力の信号について、隣接チャネル妨害
波がある場合を説明するスペクトル図で、図3(a)は入
力信号、図3(b)は出力信号である。AGC回路では上記合
成電力P2( P2 = PS + Pe )が基準値P0と一致するよう
に利得制御が働く。その結果、隣接チャネル妨害波が無
い場合に比べて、妨害波成分Peの分だけ希望波電力に対
する可変利得増幅器4の利得が低下するため、A/D変換器
6-1の出力では希望波に対する量子化雑音がPeだけ増加
して、S/Nが低下する。その結果、受信誤り率特性等の
受信特性が劣化する。
However, as shown in FIG. 3A, in the above-described technique, the power P S [dBm] of a target signal to be received (desired wave: center frequency f 0 ) is compared with the power P S [dBm] from an adjacent radio channel. Power P d of jammer (adjacent channel jammer: center frequency f 1 )
If [dBm] is larger than the receiver selectivity (attenuation amount L [dB] of BPF3 with respect to the adjacent channel interference wave), the output of the BPF3 becomes the desired power P S and the interference wave as shown in FIG. the synthesis of - (L P e = P d ) BPF3 suppression residual P e for. FIG.
FIG. 3A is a spectrum diagram illustrating a case where adjacent channel interference waves are present in the input and output signals of the BPF3. FIG. 3A shows an input signal, and FIG. 3B shows an output signal. In AGC circuit gain control so as to coincide with the combined power P 2 (P 2 = P S + P e) the reference value P 0 acts. As a result, compared with the adjacent channel interference wave is not, since the amount corresponding gain of the variable gain amplifier 4 for desired signal power of the interference wave component P e is decreased, A / D converter
The output of the 6-1 quantization noise for the desired wave is increased by P e, S / N is lowered. As a result, reception characteristics such as a reception error rate characteristic deteriorate.

【0007】[0007]

【発明が解決しようとする課題】前述の従来技術には、
受信する目的の信号の電力に比べて、隣接する無線チャ
ネルからの妨害波の電力が受信機の選択度よりも大きい
場合には、隣接チャネル妨害波が無い場合に比べて、妨
害波成分の分だけ希望波電力に対する可変利得増幅器の
利得が低下するため、S/Nが低下する。その結果、受信
特性(例えば、受信誤り率特性)が劣化する欠点があっ
た。
The above-mentioned prior art includes the following:
If the power of the interfering wave from the adjacent radio channel is greater than the receiver selectivity compared to the power of the signal to be received, the component of the interfering wave component is compared to the case where there is no adjacent channel interfering wave. However, since the gain of the variable gain amplifier with respect to the desired signal power is reduced, the S / N is reduced. As a result, there is a disadvantage that the reception characteristics (for example, the reception error rate characteristics) deteriorate.

【0008】本発明の目的は、上記のような欠点を除去
し、受信機の選択度よりも大きな隣接チャネル妨害波が
受信機に入力した場合でも、希望波に対して最適な利得
を与えるAGC回路を提供することにある。
SUMMARY OF THE INVENTION It is an object of the present invention to eliminate the above-mentioned drawbacks and to provide an AGC which provides an optimum gain for a desired signal even when an adjacent channel interference signal having a greater selectivity than the receiver is input to the receiver. It is to provide a circuit.

【0009】[0009]

【課題を解決するための手段】上記の目的を達成するた
め、本発明のAGC回路は、BPFに入力する信号とAGC回路
の出力信号との電力の差分を求め、この差分信号の大き
さに応じた補正値を積分器の入力に加算する構成とする
ことによって、受信機の選択度よりも大きな隣接チャネ
ル妨害波が受信機に入力した場合でも、希望波に対して
最適な利得を与えるAGC回路を実現したものである。
In order to achieve the above object, an AGC circuit according to the present invention obtains a difference in power between a signal input to a BPF and an output signal of the AGC circuit, and determines the magnitude of the difference signal. By adding the corresponding correction value to the input of the integrator, even if an adjacent channel interference wave larger than the receiver's selectivity is input to the receiver, the AGC that gives the optimum gain to the desired wave A circuit is realized.

【0010】[0010]

【発明の実施の形態】図1によって本発明の一実施例を
説明する。図1は本発明のAGC回路の構成を示すブロッ
ク図である。図2と同一機能の構成要素には同一の番号
を付した。その他、11は電力検出器、6-2はA/D変換器、
12-1と12-2は増幅器、8-2と8-3は加算器、13は制御装置
である。図1において、入力端子1-1より受信IF信号が
入力され、可変利得増幅器4に送られる。可変利得増幅
器4は、D/A変換器10の出力信号によって設定される利得
で増幅されて出力され、BPF3と電力検出器11に送られ
る。BPF3から出力端子2までの動作は、図2で説明した
通りなので説明を省略する。A/D変換器6-1の出力はま
た、電力算出部7にも送られ、電力算出部7では入力した
信号の電力値P1を算出して加算器8-1の負入力(被減算
入力側)端子及び増幅器12-2に送る。一方、加算器8-1
の正(被減算)入力側には、入力端子1-2を介して、入
力信号電力の基準値P0が入力される。加算器8-1では、
この入力信号の基準電力値P0から、入力した信号の電力
値P1を減算した誤差信号を出力する。この誤差信号は加
算器8-2に送られ、制御装置13の出力信号と加算された
後、積分器9に入力して積分処理された後、D/A変換器10
に積分結果を出力する。D/A変換器10は、入力信号に基
いた電圧を可変利得増幅器4の制御電圧として供給す
る。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram showing the configuration of the AGC circuit of the present invention. Components having the same functions as those in FIG. 2 are denoted by the same reference numerals. In addition, 11 is a power detector, 6-2 is an A / D converter,
12-1 and 12-2 are amplifiers, 8-2 and 8-3 are adders, and 13 is a control device. In FIG. 1, a reception IF signal is input from an input terminal 1-1 and sent to a variable gain amplifier 4. The variable gain amplifier 4 is amplified and output with a gain set by the output signal of the D / A converter 10 and sent to the BPF 3 and the power detector 11. The operation from the BPF 3 to the output terminal 2 is as described in FIG. The output of the A / D converter 6-1 is also sent to a power calculating unit 7, a negative input (minuend of the adder 8-1 by calculating the power value P 1 of the signal inputted in the power calculation section 7 Input side) terminal and send to amplifier 12-2. On the other hand, adder 8-1
Positively (minuend) input via the input terminal 1-2, the reference value P 0 of the input signal power is inputted. In the adder 8-1,
From the reference power value P 0 of the input signal, and outputs an error signal obtained by subtracting the power value P 1 of the input signal. This error signal is sent to the adder 8-2, added to the output signal of the control device 13, and then input to the integrator 9 for integration, and then the D / A converter 10
The integration result is output to. The D / A converter 10 supplies a voltage based on the input signal as a control voltage for the variable gain amplifier 4.

【0011】一方、例えばRSSI(Received Signal Stre
ngth Indicator)回路のような、入力信号の電力値(単
位:dBm)に比例した電圧(以下、RSSI電圧と称する)
を出力する電力検出器11は、BPF3の入力信号に対するRS
SI電圧を出力する。このRSSI電圧を持つ信号はA/D変換
器6-2に入力してディジタルデータに変換された後、増
幅器12-1でK1倍に増幅され(電力値:P2)、加算器8-3
の正入力(被減算入力側)端子に入力する。一方、電力
算出部7の出力電力信号(電力値:P1)は増幅器12-2でK
2倍に増幅され(電力値:P3)、加算器6-2の負入力(減
算入力側)端子に入力する。尚、係数K1とK2は、加算器
8-3に入力する2つの電力信号の利得差(それぞれの経
路に対する変換利得の差)を校正するための補正係数で
ある。加算器8-3は2つの入力信号の差分ΔP(ΔP = P2
- P3)を計算して出力し、制御装置13に送る。制御装
置13は、入力した差分信号ΔPに応じたAGC回路の利得に
対する補正値ΔGを出力して加算器8-2に送る。加算器8-
2は加算器8-1から送られてくる誤差信号( P0 - P1
に補正値ΔGを加算して積分器に送る。
On the other hand, for example, RSSI (Received Signal Stre
ngth Indicator) A voltage proportional to the power value (unit: dBm) of the input signal, such as a circuit (hereinafter referred to as RSSI voltage)
The power detector 11 that outputs
Output SI voltage. The signal having the RSSI voltage is input to the A / D converter 6-2, where the signal is converted into digital data, amplified by K 1 times by the amplifier 12-1 (power value: P 2 ), Three
To the positive input (subtracted input side) terminal. On the other hand, the output power signal (power value: P 1 ) of the power calculation unit 7 is K
It is amplified by a factor of 2 (power value: P 3 ) and input to the negative input (subtraction input) terminal of the adder 6-2. Note that the coefficient K 1 and K 2 are adders
8-3 is a correction coefficient for calibrating a gain difference between two power signals input to 8-3 (a difference in conversion gain for each path). The adder 8-3 calculates the difference ΔP between the two input signals (ΔP = P 2
-Calculate and output P 3 ) and send it to the controller 13. The control device 13 outputs a correction value ΔG for the gain of the AGC circuit according to the input difference signal ΔP and sends it to the adder 8-2. Adder 8-
2 is sent from the adder 8-1 come error signal (P 0 - P 1)
And the correction value ΔG is sent to the integrator.

【0012】ここで、制御装置13の動作について図4を
用いて説明する。図4は希望波電力を基準とした妨害波
電力比[dB](横軸)と前記電力の差分ΔP[dB](縦
軸)の関係(ΔP特性と呼ぶ)を示している。また、図
4はBPF3の隣接チャネルに対する選択度がL = 45[dB]
の場合の一例である。また、図4における漸近線(傾き
= 1)と上記ΔP特性との差ΔGは、妨害波入力時の希望
波に対するAGC回路の利得の不足分を表している。例え
ば、妨害波電力比が45[dB]の場合、電力差分ΔP = 42
[dB]で、この時、希望波に対してAGC回路の制御利得
がΔG = 3[dB]だけ不足する。制御装置13には、予め
ΔPに対する利得補正値ΔGの情報(あるいは演算式)が
格納されており、入力した差分信号ΔPを引数として、
ΔG値(または、ΔGに相当する値)を出力して積分器9
に加算して制御利得を補正を行う。
Here, the operation of the control device 13 will be described with reference to FIG. FIG. 4 shows the relationship (referred to as ΔP characteristic) between the interference wave power ratio [dB] (horizontal axis) and the power difference ΔP [dB] (vertical axis) based on the desired signal power. FIG. 4 shows that the selectivity of the BPF3 for the adjacent channel is L = 45 [dB].
This is an example of the case. Also, the asymptote (slope in FIG. 4)
= 1) and the difference ΔG between the ΔP characteristic and the ΔP characteristic indicate the shortage of the gain of the AGC circuit with respect to the desired wave when the interference wave is input. For example, when the interference power ratio is 45 [dB], the power difference ΔP = 42
At this time, the control gain of the AGC circuit for the desired wave is insufficient by ΔG = 3 [dB]. The control device 13 stores information (or an arithmetic expression) of the gain correction value ΔG for ΔP in advance, and uses the input difference signal ΔP as an argument,
The ΔG value (or a value corresponding to ΔG) is output to the integrator 9
To correct the control gain.

【0013】[0013]

【発明の効果】以上のように本発明によれば、帯域制限
フィルタの入力電力と出力電力との差分を求め、この差
分信号に応じた補正信号を積分器に加算して制御利得を
補正する構成により、受信機に妨害波が入力した場合で
も、希望波に対して常に最適な利得を与えることが可能
なAGC回路を実現できる。
As described above, according to the present invention, the difference between the input power and the output power of the band limiting filter is obtained, and a correction signal corresponding to the difference signal is added to the integrator to correct the control gain. With this configuration, it is possible to realize an AGC circuit that can always provide an optimum gain to a desired wave even when an interference wave is input to the receiver.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明のAGC回路の一実施例の構成を示すブ
ロック図。
FIG. 1 is a block diagram showing a configuration of an embodiment of an AGC circuit according to the present invention.

【図2】従来技術のAGC回路の構成を示すブロック
図。
FIG. 2 is a block diagram showing a configuration of a conventional AGC circuit.

【図3】隣接チャネル妨害波がある場合の帯域制限フィ
ルタの入力と出力スペクトルを示す説明する図。
FIG. 3 is an explanatory diagram showing an input and output spectrum of a band limiting filter when there is an adjacent channel interference wave.

【図4】本発明のAGC回路の制御装置の制御特性の一例
を示す説明する図。
FIG. 4 is an explanatory diagram showing an example of control characteristics of the control device of the AGC circuit according to the present invention.

【符号の説明】[Explanation of symbols]

1-1,1-2:入力端子、 2:出力端子、 3-1:帯域制限
フィルタ(BPF)、 4:可変利得増幅器、 5:検波
器、 6-1,6-2:A/D変換器、 7:電力算出部、8-1,8
-2,8-3:加算器、 9:積分器、 10:D/A変換器、 1
1:電力検出器、 12-1,12-2:増幅器、 13:制御装
置、
1-1, 1-2: input terminal, 2: output terminal, 3-1: band limiting filter (BPF), 4: variable gain amplifier, 5: detector, 6-1, 6-2: A / D conversion , 7: Power calculation section, 8-1, 8
-2, 8-3: adder, 9: integrator, 10: D / A converter, 1
1: Power detector, 12-1, 12-2: Amplifier, 13: Control device,

フロントページの続き Fターム(参考) 5J100 AA02 AA15 AA22 BA01 BB01 BC05 CA01 CA23 CA28 CA29 CA31 CA32 DA06 FA02 JA01 JA02 JA05 KA05 LA03 LA06 LA09 LA11 QA01 QA03 SA02 5K052 AA01 AA14 BB02 CC00 DD04 EE04 EE06 EE32 GG19 GG45 GG48 5K061 AA10 CC00 CC25 CC52 JJ24Continued on the front page F term (reference) 5J100 AA02 AA15 AA22 BA01 BB01 BC05 CA01 CA23 CA28 CA29 CA31 CA32 DA06 FA02 JA01 JA02 JA05 KA05 LA03 LA06 LA09 LA11 QA01 QA03 SA02 5K052 AA01 AA14 BB02 CC00 DD04 EE04 EE19 GG04 GG04 CC25 CC52 JJ24

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 受信信号を利得制御信号によって利得制
御して増幅する可変利得増幅器を備え、帰還信号電力と
所定の基準電力との差分を前記利得制御信号とすること
にによって、前記可変利得増幅器の利得を制御するAGC
(Auto Gain Control)回路において、 前記増幅された信号から妨害波を除去するための帯域制
限フィルタと、 前記帯域制限フィルタに入力する信号と前記帰還信号電
力との電力の差分を求め、該差分信号の大きさに応じた
補正値を積分器の入力に加算する補正手段を有し、 該補正手段によって前記利得制御信号を補正することを
特徴とするAGC回路。
1. A variable gain amplifier, comprising: a variable gain amplifier that amplifies a received signal by performing gain control with a gain control signal, wherein a difference between a feedback signal power and a predetermined reference power is used as the gain control signal. Controlling AGC
(Auto Gain Control) circuit, a band limiting filter for removing an interfering wave from the amplified signal, and a power difference between a signal input to the band limiting filter and the feedback signal power is obtained. An AGC circuit, comprising: a correction unit that adds a correction value corresponding to the magnitude of the gain control signal to an input of an integrator, wherein the correction unit corrects the gain control signal.
【請求項2】 受信信号を利得制御信号によって利得制
御して増幅する可変利得増幅器と、該増幅された信号か
ら妨害波を除去するため帯域制限する帯域制限フィルタ
と、該帯域制限された信号を検波する検波器と、該検波
された信号をディジタルデータに変換するA/D変換器
と、該ディジタルデータをAGC(Auto Gain Control)回
路の出力信号とすると共にその電力値を算出する電力算
出手段と、該算出された電力を所定の基準電力と比較し
て誤差信号を出力する加算器と、該誤差信号を積分する
積分器と、該積分器によって出力された信号をアナログ
信号に変換するD/A変換器とを備え、該アナログ信号を
前記利得制御信号として前記可変利得増幅器の利得を制
御することによって、前記受信信号の利得の制御を行う
AGC回路において、 前記帯域制限フィルタに入力する信号の電力値を求める
電力検出手段と、 前記電力検出手段によって検出された前記帯域制限フィ
ルタに入力する信号の電力値と、前記電力算出手段によ
って算出された前記電力との差分を求める差分値算出手
段と、 該差分値算出手段によって求められた前記電力の前記差
分値から、前記加算器が出力する前記誤差信号を補正す
る補正値を出力する補正値出力手段と、 該補正値出力手段によって出力された補正値によって、
前記誤差信号の値を補正する補正手段とを有し、 該補正手段によって補正した誤差信号によって前記可変
利得増幅器の利得を制御することによって受信信号の利
得制御することを特徴とするAGC回路。
2. A variable gain amplifier for amplifying a received signal by gain control with a gain control signal, a band limiting filter for band limiting to remove an interference wave from the amplified signal, and a band limiting filter for filtering the band limited signal. A detector for detecting, an A / D converter for converting the detected signal into digital data, and power calculating means for converting the digital data into an output signal of an AGC (Auto Gain Control) circuit and calculating a power value thereof An adder that compares the calculated power with a predetermined reference power and outputs an error signal; an integrator that integrates the error signal; and a D that converts the signal output by the integrator into an analog signal. / A converter, and controls the gain of the received signal by controlling the gain of the variable gain amplifier using the analog signal as the gain control signal.
In the AGC circuit, a power detection unit that calculates a power value of a signal input to the band-limiting filter, a power value of a signal input to the band-limiting filter detected by the power detection unit, and a power value calculated by the power calculation unit. And a correction value for outputting a correction value for correcting the error signal output by the adder from the difference value of the power obtained by the difference value calculation means. Output means, and a correction value output by the correction value output means.
An AGC circuit comprising: a correction unit that corrects the value of the error signal, wherein the gain of the received signal is controlled by controlling the gain of the variable gain amplifier based on the error signal corrected by the correction unit.
【請求項3】 請求項1記載のAGC回路において、 前記電力検出手段は、前記帯域制限フィルタへ入力する
信号を入力して電力検出を行う電力検出器と、該電力検
出器によって出力をディジタルデータに変換する第2の
A/D変換器であり、 前記差分値算出手段は、前記第2のA/D変換器が出力す
る前記ディジタルデータと、前記電力算出手段によって
算出された電力値との差分を算出する加算器であること
を特徴とするAGC回路。
3. The AGC circuit according to claim 1, wherein said power detection means performs power detection by inputting a signal to be input to said band limiting filter, and outputs a digital data by said power detector. Convert to the second
An A / D converter, wherein the difference value calculating means is an adder for calculating a difference between the digital data output by the second A / D converter and a power value calculated by the power calculating means. An AGC circuit characterized by the following.
【請求項4】 請求項1記載のAGC回路において、前記
補正値出力手段は、前記帯域制限フィルタの入力電力と
出力電力との差分情報であり、前記補正値出力手段の出
力は、前記AGC回路の利得を補正する制御情報であり、
前記補正値出力手段は予め前記差分情報に対応した利得
補正値または利得補正値を算出する演算式を格納し、入
力した差分情報に基づいて格納あるいは算出した利得補
正値を出力し、前記積分器によって加算することによっ
て前記AGC回路の利得を補正することを特徴とするAGC回
路。
4. The AGC circuit according to claim 1, wherein said correction value output means is difference information between input power and output power of said band-limiting filter, and said correction value output means outputs said AGC circuit. Control information for correcting the gain of
The correction value output means stores in advance a gain correction value corresponding to the difference information or an arithmetic expression for calculating the gain correction value, and outputs the stored or calculated gain correction value based on the input difference information. AGC circuit wherein the gain of the AGC circuit is corrected by adding
【請求項5】 受信信号を増幅し、該増幅された信号か
ら妨害波を除去するため帯域制限し、該帯域制限した信
号を検波し、該検波した信号をディジタルデータに変換
し、該変換したディジタルデータをAGC(Auto Gain Con
trol)回路の出力信号とすると共にその電力値を算出
し、該算出した電力を所定の基準電力と比較して誤差信
号を出力し、該誤差信号を積分し、該積分した信号をア
ナログ信号に変換し、該変換したアナログ信号を前記利
得制御信号として、前記受信信号の利得の制御を行うAG
C回路制御方法において、 前記帯域制限する前の信号の電力値を求め、前記帯域制
限する前の信号の電力値と、前記AGC回路の出力信号の
電力値との差分値を求め、該差分値から前記誤差信号を
補正する補正値を出力し、該補正値によって前記誤差信
号の値を補正し、該補正した誤差信号によって前記受信
信号の利得を制御することを特徴とするAGC回路利得制
御方法。
5. A received signal is amplified, a band is limited to remove an interference wave from the amplified signal, the band-limited signal is detected, the detected signal is converted into digital data, and the converted signal is converted. AGC (Auto Gain Con
trol) as an output signal of the circuit and calculating a power value thereof, comparing the calculated power with a predetermined reference power, outputting an error signal, integrating the error signal, and converting the integrated signal into an analog signal. AG that performs conversion and controls the gain of the received signal using the converted analog signal as the gain control signal.
In the C circuit control method, a power value of the signal before the band limitation is obtained, and a difference value between a power value of the signal before the band limitation and a power value of an output signal of the AGC circuit is obtained. AGC circuit gain control method comprising: outputting a correction value for correcting the error signal from the output signal; correcting the value of the error signal with the correction value; and controlling the gain of the reception signal with the corrected error signal. .
JP11231191A 1999-08-18 1999-08-18 Agc circuit and method for its gain control Pending JP2001057513A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11231191A JP2001057513A (en) 1999-08-18 1999-08-18 Agc circuit and method for its gain control

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JP2001057513A true JP2001057513A (en) 2001-02-27

Family

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001168664A (en) * 1999-12-08 2001-06-22 Nec Corp Receiving power calculation circuit and receiver using the same
JP2002290278A (en) * 2001-03-28 2002-10-04 Toshiba Corp Wireless communication terminal and its control circuit
WO2013008747A1 (en) 2011-07-08 2013-01-17 日本電気株式会社 Reception device, and gain control method
CN112235855A (en) * 2020-09-25 2021-01-15 锐迪科微电子(上海)有限公司 Signal processing method and device
CN115765775A (en) * 2022-11-08 2023-03-07 北京智芯微电子科技有限公司 Data receiving device, method and chip for power line carrier communication

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001168664A (en) * 1999-12-08 2001-06-22 Nec Corp Receiving power calculation circuit and receiver using the same
US6731703B2 (en) 1999-12-08 2004-05-04 Nec Corporation Reception power level calculating circuit and receiver using the same
JP2002290278A (en) * 2001-03-28 2002-10-04 Toshiba Corp Wireless communication terminal and its control circuit
WO2013008747A1 (en) 2011-07-08 2013-01-17 日本電気株式会社 Reception device, and gain control method
US9118294B2 (en) 2011-07-08 2015-08-25 Nec Corporation Receiving device and gain control method
CN112235855A (en) * 2020-09-25 2021-01-15 锐迪科微电子(上海)有限公司 Signal processing method and device
WO2022062883A1 (en) * 2020-09-25 2022-03-31 锐迪科微电子(上海)有限公司 Signal processing method and apparatus
CN112235855B (en) * 2020-09-25 2022-09-30 锐迪科微电子(上海)有限公司 Signal processing method and device
CN115765775A (en) * 2022-11-08 2023-03-07 北京智芯微电子科技有限公司 Data receiving device, method and chip for power line carrier communication

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