JP2001057087A - Non-volatile memory having burst mode reading function and page mode reading function during interruption period of electric change operation - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a memory having a burst mode reading function and a page mode reading function while erasing or programming one sector in a semiconductor memory having two or more memory sectors S1-S9. SOLUTION: This semiconductor memory is provided with first control circuit means 4, 6 for controlling the electrical change operation of contents of a memory. The first control circuit means 4 (6) can execute selectively the operation for changing electrically one content of a memory sector and can interrupt the execution so as to be possible to reading-access the other memory sectors. The memory is characterized by providing second control circuit means 8, 6 which can permit burst mode reading or page mode reading operation for reading contents of the other memory sectors.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of semiconductor memories, and more particularly, to EPROMs, EEPROMs, and flash memories.
It relates to electrically changeable (programmable or programmable and erasable) non-volatile memory, such as EPROM.

[0002]

2. Description of the Related Art A normal read operation of a memory (hereinafter referred to as a standard read) is performed to provide an address to the memory that identifies a corresponding location in the memory. After a special time interval, called access time, the data stored at said location is available at the output of the memory.

[0003] In addition to the standard read operation, memories are known that can perform page mode read operations, which operate only when the lower order bits of the address provided at the input of the memory change. It is possible to obtain valid data at the output of the memory in a time shorter than the access time.

[0004]

However, other known memories have the possibility of performing so-called burst mode reads in addition to the possibility of performing standard reads. By providing the memory with an external clock signal and an address corresponding to the initial memory location, the memory automatically increments the address internally and outputs new data corresponding to successive memory addresses on each cycle of the clock signal. To be generated. Instead of accessing randomly distributed locations in memory space,
In all cases where a certain number of adjacent locations need to be accessed, this read mode allows the access time to be significantly reduced.

[0005] Also known are electrically programmable and erasable non-volatile memories organized in sectors, or portions of memory that can be erased and programmed independently of one another. This type of memory also has a functional capability called temporary erasure interruption ("erase interruption") or temporary programming interruption ("program interruption"), which is one of the other memory sectors. Allows a temporary interruption of a sector erase or programming operation to perform a standard read access to the However, since the read is a standard type of read, the possibility of reducing the access time provided by the two read modes described above is not used. Rapid access to the memory in burst read or page read mode is performed only upon completion of programming or erasing.

In view of the foregoing state of the art, it is an object of the present invention to provide a memory having the capability of burst mode reading and / or page mode reading while erasing or programming sectors.

[0007]

According to the invention, this object is achieved by the electrically changeable semiconductor memory according to the invention. The present invention comprises two or more memory sectors whose contents can be individually changed, and first control circuit means for controlling an operation of electrically changing the contents of the memory. Permitting the selective execution of an operation that electrically alters the contents of one of the above memory sectors and interrupting it to allow read access to the other of the two or more memory sectors; A second control circuit means capable of permitting a burst mode read or a page mode read operation for reading the contents of the other memory sector during an interruption period in an electrically changeable semiconductor memory. It is characterized by having.

[0008]

BRIEF DESCRIPTION OF THE DRAWINGS The features and advantages of the present invention will become apparent from the following detailed description of one of the embodiments illustrated by way of example in the accompanying drawings. However, the technical scope of the present invention is not limited by these examples. Referring to the drawing,
For example, EPROM, EEPROM, Flash EEPROM
A non-volatile memory 1 having electrically modifiable contents, such as an OM, comprises a plurality of memory sectors S1-S9 or, in the example of a flash EEPROM memory, a memory portion which can be erased independently of each other; Decoding and line selection circuit 2 and circuit 3 for reading memory cells
("Sensing circuit") and an output buffer block 30, the circuits 2, 3, 30 being well known per se and therefore only shown schematically as functional blocks.

Block 10 shows the internal control logic for memory 1. The block 10 includes an external address signal ADD from the external address signal bus to the memory 1, a DAT signal from the external data bus to the memory 1,
, An external signal WEN (writable) for controlling the operation of changing the contents of the memory 1, an external clock signal CK, and a new address valid for the memory 1 are present on the address bus. At this time, for example, an external signal AD externally activated by a microprocessor that manages the memory 1 is received.

As shown in more detail in FIG.
The control logic circuit 10 includes an interface logic circuit 11, and interpretation of external commands is executed by, for example, PLA (programmable logic array) means. Logic circuit 11
Interprets the sequence of commands given to it by the signals ADD and DAT, the fact that the memory has been enabled (CEN signal active) and its contents should be changed (or the "write" Mode MODIFY) and activates the signal MODIF. Logic circuit 11 generates signal SUSP by interpreting the sequence of commands received by signals ADD and DAT, and this signal SUSP is used to temporarily change the memory contents to be performed in order to perform a memory read. It is activated whenever it needs to be temporarily interrupted.

The control logic 10 further comprises a block 12 for detecting a burst read or page read mode. Block 12 receives signal AD and clock CK. If the external clock signal CK is present, the signal AD
Determines the activation of the burst / page signal, and the activation of the burst / page signal determines the entry to burst read or page read mode.

Returning to FIG. 1, block 4 identifies circuitry for controlling the operation of electrically altering the contents of memory 1, and, for example, in the case of a flash EEPROM memory, circuitry for controlling the programming and erasing operations. Identify. Circuit 4 receives signals MODIF and SUSP. If signal MODIF is active (either high or low logic level), memory sector S1-
One of S9 indicates that a programming or erase operation is to be performed. If signal SUSP is active (either high or low logic level), the erase operation performed on one of memory sectors S1-S9 should be temporarily interrupted to perform a read operation. Indicates that there is.

The circuit 4 has (groups of) output signals 5 for controlling an address counter 6. Address counter 6
Enables internal scanning of the address of the memory and supplies a signal 7 to the decode and line select circuit 2 which propagates the memory location address. The address counter 6 also outputs the signal M
ODIF, signal burst / page, and external address signal ADD are received.

Block 8 identifies circuitry for controlling a burst mode read or page mode read operation. Circuit 8 includes signal burst / page, MODIF, SU
SP, CK and a subset LSB of the address signal ADD including the lower digit bits of the address given to the memory 1
(ADD) is received. The block 8 supplies (a group of) control signals 9 to the address counter 6, and further controls the read circuit 3 through the control signal 13.

The output of the read signal 3 is supplied to an output buffer block 30 and then to an external data bus DAT.

The two control circuits 4, 8 for controlling a programming or erasing operation and a burst mode reading or a page mode reading operation, respectively, operate simultaneously and perform an erasing or programming operation performed in one of the memory sectors S1-S9. Enable an interrupt, thereby performing a burst mode read or a page mode read on any one of the remaining memory sectors.

FIG. 3 further shows, by a block diagram, the control operated by the block 8 in the address counter 6 and the read circuit 3 in more detail, and also provides the latter (read circuit 3?) In more detail. . Signal 9
Includes a signal AD1, which is activated by the circuit 8 so that the address counter 6 outputs the external address signal AD1.
D and the signal INCADD is loaded with the currently existing address, and the signal INCADD is activated to instruct the address counter 6 to increment the internal address 7 provided to the selection circuit 2.

The read circuit 3 shown schematically in FIG.
Comprises a plurality of actual read circuits 14, of a type well known per se, which comprises memory sectors S1-S
The reading is performed in parallel at a plurality of positions at one of the nine positions, for example, the reading is performed at four positions in parallel. The read circuit 14 receives from the block 8 the signals 15 necessary for their operation, for example the signal for starting the phase of the discharge of the selected bit line and for storing the data read. The output of the read circuit 14 is provided to a decoder 16 which, upon command of the signal 17 provided by block 8, selects one of the outputs of the plurality of read circuits 14,
Provides the selected output to a latch bank 18 operated by a signal LOAD provided by Latch output
18 is provided to the output buffer block 30.

FIG. 4 schematically illustrates the operation of block 8 for a logic gate. The signal AD1 which is energized so as to load the address ADD with the address currently present in the signal ADD is applied to the external signal AD (address bus ADD).
Is activated when a valid address is activated, but only when there is no change operation of the contents of the memory sectors S1-S9 to be executed (the signal MODIF is not activated), or the change operation is performed. During the operation (signal MODI
F is active), a command to interrupt the operation arrives to enable reading (SUSP signal is active).

The internal address 7 is determined by the address counter 6.
Is generated in synchronization with the external clock signal CK.
Only if the page signal is active, and (a)
If there is no operation of changing the contents of memory sectors S1-S9 to be performed (signal MODIF is not activated),
Or (b) the change operation is being performed, but the signal SUSP
Is active (interrupt change to allow read access to another memory sector). However, if an operation to change the contents of the sector has taken place and no interrupt command has arrived, the signal INCADD is a logic circuit controlling an algorithm for changing the contents of the memory, for example the internal clock generated by block 4 in FIG. Signal INT
Generated in synchronization with CK.

For example, in memory sector S1, an erase operation ("erase mode") is performed, and it is desired to access another sector, eg, memory sector S2, simultaneously to perform a burst mode read or a page mode read. Suppose that. The operation of changing the contents of the sector is performed, and the signal SUSP is activated, thereby causing the control circuit 4 to interrupt the erase operation by the signal MOP.
DIF is active. The burst / page signal is further activated, so that the control circuit 8 can start a burst mode read or page mode read operation in the sector S2 by the address counter 6.

A memory according to the present invention provides for quick access to another memory sector in burst mode or page mode during a memory sector erase operation without having to wait for the sector erase to be completed (standard This has the advantage of permitting faster access than that performed by a simple read.

Obviously, the memory 1 can also operate in a standard mode for reading a memory sector by interrupting the programming or erasing operation of the contents of another sector.

Obviously, modifications and / or additions may be made to the above description and illustrations without departing from the scope of the invention, which is defined in the claims.

[Brief description of the drawings]

FIG. 1 is a schematic diagram of a main functional block and a memory according to the present invention.

FIG. 2 is a block diagram of a logic circuit for controlling the memory of FIG. 1;

FIG. 3 is a more detailed block diagram of a portion of the memory of FIG. 1;

FIG. 4 is a simplified diagram of the operation of a logic gate and a circuit for controlling a burst mode read or page mode read operation of the memory of FIG. 1;

 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Lorenzo Vedalida, Italy, 20007 Bimercate, Via Grandi, 7 (72) Inventor Mauro Sari, Italy, 20079 Santo Angelo Lodiziano, Via Lega Lombarda, 8 / Bee (72) Inventor Antonio Lusso Italy, 20056 Trezzo sul Adad, Via Piave, 6

Claims (5)

[Claims] At least two memory sectors whose contents can be individually changed, and first control circuit means for controlling an operation of electrically changing the contents of the memory, the first control circuit means comprising: To allow selective execution of an operation that electrically alters the contents of one of the at least two memory sectors and suspend it to allow read access to the other of the at least two memory sectors An electrically changeable semiconductor memory capable of interrupting the execution, wherein during the interruption period, a burst mode read operation or a page mode read operation for reading the contents of the other memory sector can be permitted. An electrically changeable semiconductor memory comprising a second control circuit means. 2. The second control circuit, wherein the first control circuit means includes a circuit for controlling an electrical change operation, and a scanning circuit for scanning a memory location of the at least two memory sectors. 2. The memory of claim 1, wherein the means comprises a circuit for controlling a burst mode read or a page mode read operation, and the scanning circuit. 3. The circuit for controlling a burst mode read or page mode read operation includes the steps of: providing an external address to a scan circuit which is currently provided to a memory and identifies an initial memory location of the burst mode read or page mode read operation. 3. The memory of claim 2, controlling a load, and further controlling a continuous scan of a memory location adjacent to the initial memory location. 4. The first and second control circuit means comprises:
4. The memory according to claim 3, wherein the memory operates under the control of a third control circuit means for receiving and interpreting a command signal external to the memory. 5. The third control circuit means for generating a signal for the first control circuit means to electrically change the contents of one of the at least two memory sectors. And controlling the interruption of said execution, and further generating a signal for said second control circuit means to read the other burst mode or page mode of said at least two sectors during said interruption period The memory according to claim 4, wherein the operation is controlled.