JP2001053827A - Isochronous communication node and local clock circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an isochronous communication node and a local clock circuit that isochronous communication by a common local clock can be performed. SOLUTION: A control circuit CTL successively outputs an SET1, RST1 and SET2 according to a cycle start signal. A counter CTR counts a local clock SLCK, and this counter CTR is reset by the RST1. A latch LCH latches a count value ICx of the counter CTR according to the SET1. A reference count value IC0 is subtracted from the ICx so that an ICd can be obtained. A data adjusting part DTU/D cumulatively adds the ICd according to the SET2, and outputs an SCd. The SCd is added to reference frequency data F0, and D/A converted by a D/A converter DAC, and supplied through a low pass filter LPF to a varicap D so that local clock frequencies can be controlled.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to an isochronous communication system used for synchronous transfer of data by a high-speed serial bus interface conforming to the 4 interface standard, and in particular, isochronous communication that enables a local clock at an isochronous communication node to be synchronized with a cycle master with high accuracy. The present invention relates to a node and a local clock circuit used for the node.

[0002]

2. Description of the Related Art For example, a personal computer (hereinafter, referred to as a personal computer)
The IEEE (Institute of Electrical and Industrial Technology) is one of the digital interfaces for connecting a peripheral device such as a hard disk, a printer, a digital camera, a camera-integrated digital VTR, and the like.
Electronics Engineers-Institute of Electrical and Electronics Engineers (IEEE), IEEE 1394 interface standard (IE)
An IEEE 1394 interface, which is a high-speed serial bus interface compliant with the IEEE 1394-1995 standard and the like, is being used. The IEEE 1394 interface, also called "Fire Wire" or "i.LINK" (both trademarks), can obtain a high data transfer rate, can form a network with a flexible connection form, Realization of real-time communication of information and voice information is easy, and it has a mechanism to automatically recognize the system configuration when turning on the system, connecting new equipment or disconnecting equipment on the system, ID (Identifier to identification information) for each device
It has attracted attention as a high-speed serial bus interface capable of constructing a network having various features, such as automatic setting of a network (so-called "hot plug-in").

In the IEEE 1394 interface, an isochronous mode, which is a kind of synchronous transfer for guaranteeing a data transfer speed, and an asynchronous (asynchronous to asynchronous transfer) method, which guarantees a transfer without guaranteeing a transfer speed, are used for data transfer. asynchronous) mode. That is, 125 μs
Is a cycle, data packets in the isochronous mode are transferred within a range of 80% or less of the bandwidth starting from the cycle start packet, and data packets in the asynchronous transfer mode are not interrupted during the remaining period. To transfer.

The transfer destination device of each isochronous data packet is given by the number of the isochronous data packet called a channel. In isochronous transfer, there is a priority order depending on the channel. If the remaining time used by the isochronous transfer being executed by another device before the required time for the isochronous transfer to be newly executed is not permitted, the new isochronous transfer is not permitted. Therefore, the isochronous transfer being executed is absolutely present on the bus. The asynchronous data packet transmits the ID (identifier) of the transmission source and the reception destination together with the packet data for each transaction. The destination of the asynchronous data packet is
An acknowledgment signal is inserted between asynchronous data packets and returned to the transmission source. If no acknowledgment signal is returned, the transmission source retransmits the asynchronous data.

An example of such a data transfer system using the IEEE 1394 interface is disclosed in Japanese Patent Laid-Open No. 10-3.
It is disclosed in Japanese Patent No. 22414. JP-A-10-32
No. 2414 describes in detail isochronous transfer, asynchronous transfer, and the like in the IEEE 1394 interface.

Each node constituting a communication system such as a network using the above-mentioned IEEE 1394 interface includes:
It functions as a cycle master or a cycle slave to execute data communication by isochronous transfer.
The cycle master issues a cycle start packet as a reference for the communication cycle, and the cycle slave operates according to the communication cycle determined by the cycle start packet. Therefore, the communication system includes one node serving as a cycle master and one or more nodes serving as cycle slaves. Each node is configured to function as both a cycle master and a cycle slave.

In the isochronous communication in the IEEE 1394 interface, each cycle slave receives a cycle start packet issued by the cycle master and operates so as to adjust the time to the cycle master. By this operation, all devices connected by the IEEE 1394 interface, that is, all nodes, apparently have the same cycle time (Cycle TIME). Then, a time stamp or the like is generated in each node device based on the cycle time.

[0008]

SUMMARY OF THE INVENTION By the way, IEEE1
In a communication system such as a network using a 394 interface, a clock system for managing cycle time is not a single one, but is independent as a local clock for each node. That is, in the IEEE 1394 interface, a clock generation unit provided independently for each node generates a local clock of 24.576 MHz common to all nodes. When the cycle slave node receives the cycle start packet transmitted from the node serving as the cycle master, the cycle slave node adjusts the cycle time based on the information included in the packet. If the local clock of each node is exactly 2
There is no problem if it is generated at 4.576 MHz, but it is inevitable that each local clock generator has a slight error in the oscillation frequency.

[0009] Here, referring to FIG.
A specific configuration of a node configuring a communication system using four interfaces will be described. As shown in FIG. 3, the IEEE 1394 interface includes a LINK unit 110 forming a link (LINK) layer and a PHY unit 12 forming a physical (physical) layer, as shown in FIG.
0. LINK unit 110 and PHY
The unit 120 is configured as a semiconductor IC (integrated circuit) chip called a LINK chip, a PHY chip, or the like. The PHY unit 120 includes an I for connection between nodes.
This is a part for generating an electric signal to be transmitted to the EEE1394 cable, and performs encoding and decoding of input / output signals and control of a connector port and the like. The LINK unit 110 is a PHY
This is a part for controlling a digital signal above the unit 120, and performs packet transfer, cycle time control, and the like.

The LINK unit 110 has an isochronous interface (isochronous I / F) 111, a host interface (host I / F) 112, and a PHY interface (PHY-I / F) 113. PHY
The unit 120 includes a LINK interface (LINK-I /
F) 121, crystal oscillator 122 and PLL (PhaseLoc)
ked Loop 123).

The isochronous interface 111 of the LINK unit 110 is an interface for signals related to isochronous transfer. The host interface 112 of the LINK unit 110 is an interface for connecting to the host system of the node. The PHY interface 113 of the LINK unit 110 is an interface connected to the PHY unit 120 to exchange information, and is connected to the LINK interface 121 of the PHY unit 120.

The LINK interface 121 of the PHY unit 120 is an interface that connects to the LINK unit 110 to exchange information, and is connected to the PHY interface 113 of the LINK unit 110. Crystal oscillator 122
Are connected to a crystal resonator X externally attached to the PHY section 120, and capacitors C1 and C2 inserted between both ends thereof and a common potential (ground), respectively. The crystal oscillation unit 122 and the PLL 123
A local clock having a frequency of 4.576 MHz is generated.

As described above, the crystal oscillator 122 and the PL
A local clock generation unit composed of L123 oscillates using the crystal oscillator X and generates a predetermined local clock of 24.576 MHz used for isochronous transfer. However, it is inevitable that the local clock frequency has a slight error due to variations in the crystal unit X and other fluctuation factors in the crystal oscillation unit 122. Since the value of such an error differs depending on the device, the frequency of the local clock for each node varies. As described above, if there is a variation in the frequency of the local clock, even if it is minute, it causes a problem in the isochronous transfer.

As described above, since the local clock is generated by the local clock generator for each node, the oscillation accuracy of the local clock generator in each node slightly differs. Therefore, it is considered that the following problem may occur. When the cycle start packet is received, even if the timing is once adjusted, the error of the cycle offset (Cycle Offset) value corresponding to a fractional part in the cycle time gradually increases until the next cycle start packet is received. It varies every time. As a result, the time stamps of the respective nodes are shifted, and in the isochronous communication using the time stamps, a timing error occurs between the transmitting node and the receiving node.

Next, an adverse effect when the cycle offset value varies from node to node will be described in detail. FIG. 4 shows a case where the local clock frequency at the transmitting node and the local clock frequency at the receiving node are different from the master clock, that is, the local clock and frequency of the cycle master node. 3 shows a difference between the transmitting side and the receiving side of the isochronous time based on the cycle offset value in a certain node.

In FIG. 4, the local clock frequency CLKm of the cycle master is 24.576 MHz, and the local clock frequency of the transmitting node is CLKt.
And the local clock frequency of the receiving node is CLK
An example is shown in which the relationship between the local clock frequencies when r is such that CLKr <CLKm <CLKt.

If the transmitting node captures the time stamp SYTx when the isochronous time is Ttx, the cycle offset value becomes Cotx
Becomes When the time stamp SYTx is sent from the transmitting node to the receiving node, the receiving node attempts to reproduce the isochronous time Ttx based on the value. However, in the receiving node, since the frequency of the local clock is not the same as that of the transmitting node and is lower than that of the transmitting node, the time actually reproduced is equal to the reproduced isochronous time Trx.
Will be.

As described above, in the isochronous transfer using the time stamp, since the frequency of the local clock is not the same on the transmitting side and the receiving side, an error t occurs in the reproduction time on the receiving side. Would.

The present invention has been made in view of the above circumstances, and adjusts the local clock frequency of all nodes involved in isochronous communication to a master clock which is a local clock of a node serving as a cycle master. It is an object of the present invention to provide an isochronous communication node and a local clock circuit capable of performing isochronous communication according to the above.

[0020]

In order to achieve the above object, an isochronous communication node according to a first aspect of the present invention comprises: an isochronous communication node that performs isochronous communication; , During cycle slave operation,
Based on the reception timing of the isochronous packet, the isochronous cycle period is actually measured using the local clock, compared with a reference value, and the clock generation means is controlled based on the comparison result to correct and control the frequency of the local clock. Clock correction means.

The clock correction means counts the local clock based on the reception timing of the isochronous packet, and measures time of the isochronous cycle period. The clock correction means compares the value measured by the time measurement means with a reference value to obtain error information. It may include an error detecting means to obtain, and a correction control means for controlling the clock generating means to correct the error based on the error information.

In the cycle slave operation, the clock correction means controls the correction of the frequency of the local clock, and in the cycle master operation, the operation of the clock correction means is suppressed so that the clock generation means operates at a predetermined frequency. It may further include control means for operating.

Further, a local clock circuit according to a second aspect of the present invention is a local clock circuit provided in an isochronous communication node for performing isochronous communication, wherein the local clock circuit generates a local clock, and a local clock circuit based on a reception timing of the isochronous packet. A timer for counting the local clock and actually measuring the isochronous cycle period; an error detector for comparing the actual value measured by the timer with a reference value to obtain error information; and correcting an error based on the error information. Correction control means for controlling the clock generation means.

[0024] A local clock circuit according to a third aspect of the present invention is a local clock circuit provided in an isochronous communication node for performing isochronous communication.
A timer for counting the local clock and actually measuring an isochronous cycle period based on a reception timing of the isochronous packet; an error detector for obtaining error information by comparing an actually measured value of the timer with a reference value; Correction control means for controlling the clock generation means to correct the error based on the following, discriminate between the cycle slave operation and the cycle master operation, during the cycle slave operation, the clocking means, the error detection means and the correction control means Control means for performing correction control of the frequency of the local clock, and controlling the clock generation means at a predetermined frequency by suppressing the operation of the clock means, the error detection means and the correction control means during the cycle master operation. Have.

The isochronous communication node and the local clock circuit according to the present invention measure the isochronous cycle period by using the local clock based on the reception timing of the isochronous packet during the cycle slave operation of the isochronous communication node performing the isochronous communication. The frequency is compared with the value and the clock generation means is controlled based on the comparison result to correct and control the frequency of the local clock. In the isochronous communication node and the local clock circuit, the local clock frequency of each node related to the isochronous communication is controlled so as to correctly match the local clock frequency of the cycle master node. Isochronous communication using the local clock.

[0026]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a configuration of a main part of an isochronous communication node using an IEEE1394 interface according to an embodiment of the present invention.

The isochronous communication node shown in FIG.
LINK constituting the link layer almost similarly to the case of FIG.
Unit 1 and a PHY unit 2 constituting a physical layer, and a PHY unit
The unit 2 includes a crystal unit X and capacitors C1 and C2 that constitute an external circuit. The isochronous communication node in FIG. 1 further includes a control circuit CTL, a counter CTR, a latch LCH, a reference value storage unit CRF, a first adder ADD1, a data adjustment unit DTU / D, a frequency storage unit FDT as additional circuits according to the present invention. Second adder ADD
2. D / A (digital-analog ~ digital-to-analo)
gue) A clock correction circuit is configured by providing a converter DAC, a low-pass filter LPF, a resistor R, a varicap D, and a capacitor C3. LINK section 1 and P
The HY unit 2 is configured as a semiconductor IC chip called a LINK chip and a PHY chip, respectively.

The PHY unit 2 is an IEEE for connection between nodes.
This is a part for generating an electric signal flowing through the E1394 cable, and performs encoding and decoding of input / output signals and control of a connector port and the like. The LINK unit 1 controls a digital signal at a higher level than the PHY unit 2, and performs packet transfer, cycle time control, and the like.

The LINK unit 1 has an isochronous interface (isochronous I / F) 11, a host interface (host I / F) 12, and a PHY interface (PHY-I / F) 13. PHY part 2 is L
It has an INK interface (LINK-I / F) 21, a crystal oscillator 22, and a PLL (Phase Locked Loop) 23.

The isochronous interface 11 of the LINK unit 1 is an interface for signals related to isochronous transfer, and as shown in FIG.
~ 0], OUTEN #, ICLK, ITREQ, ITX
#, IEOP #, IRX #, IRCV #, IRERR
#, BE # [1-0], CT, CH [1-0] and I
It has each signal path of CS. Signal IDATA [15-0]
Is an input / output bidirectional signal, and signals OUTEN #,
ITREQ and IEOP # are input signals. Then, the signals ICLK, ITX #, IRX #, IRCV #,
IRERR #, BE # [1-0], CT, CH [1-
0] and ICS are output signals. The signal ICS is a cycle start signal output from the LINK unit 1 when a cycle start packet is received and indicating the start of an isochronous cycle. The host interface 12 of the LINK unit 1 is an interface for connecting to the host system of the node. LINK part 1 P
The HY interface 13 is an interface connected to the PHY unit 2 for exchanging information.
It is connected to the NK interface 21.

LINK interface 21 of PHY section 2
Is an interface connected to the LINK unit 1 for exchanging information. The PHY interface 1 of the LINK unit 1 is
3 is connected. As shown, the signal paths of the PHY interface 13 of the LINK unit 1 and the LINK interface 21 of the PHY unit 2 include signals LREQ and CTL [1].
0], D [3-0], DIRECT, LPS and S
It is composed of LCK. The signals LREQ and LPS are L
These signals are supplied from the INK unit 1 to the PHY unit 2, and include signals CTL [1 to 0], D [3 to 0], and DIRECT.
Is a bidirectional signal from the LINK unit 1 to the PHY unit 2 and from the PHY unit 2 to the LINK unit 1, and the signal SLCK
Is a signal supplied from the PHY unit 2 to the LINK unit 1. This signal SLCK is transmitted to the crystal oscillation section 22 of the PHY section 2.
And a local clock signal generated by the PLL 23 and the like.

The crystal oscillating unit 22 is connected to a crystal unit X externally attached to the PHY unit 2 and capacitors C1 and C2 inserted between both ends and a common potential (ground). Crystal oscillator 22 and PLL 23
Generates a local clock having a predetermined frequency of 24.576 MHz. The local clock generation unit having the crystal oscillator 22 and the PLL 23 oscillates using the crystal oscillator X and uses a predetermined 24.576 used for isochronous transfer.
Generate a local clock of MHz. The local clock frequency has an error due to variations in the crystal unit X and other fluctuation factors in the crystal oscillation unit 22. Therefore, the error of the oscillation frequency of the local clock is corrected by a clock correction circuit surrounded by a broken line in FIG.

Next, the configuration of the clock correction circuit will be described. The capacitor C3 and the varicap D are sequentially connected in series between the connection point between one end of the crystal unit X and the first capacitor C1 and the common potential, with the anode side of the varicap D as the common potential side as shown in the figure. Connecting. A resistor R is connected to the connection point between the capacitor C3 and the varicap D in series.
To one end.

The control circuit CTL operates using the local clock signal SLCK output from the link interface 21 of the PHY section 2 as a clock. Control circuit CTL
Is LINK when the master signal MAST is "1".
In response to a cycle start signal ICS output from the unit 1, a first set signal SET1, a first reset signal RST1, and a second set signal SET2 are sequentially output, and a latch LCH, a counter CTR, and a data adjustment unit are respectively provided. Supply to DTU / D. That is, the first set signal SET1 is a set signal of the latch LCH,
The first reset signal RST1 is a reset signal for the counter CTR, and the second set signal SET2 is a set signal for the data adjustment unit DTU / D. When the master signal MAST is “0”, the control circuit CTL always outputs the second reset signal RST2 and supplies the second reset signal RST2 to the data adjustment unit DTU / D. That is, the second reset signal RST2 is a reset signal for the data adjustment unit DTU / D.

The counter CTR counts the local clock signal SLCK output from the link interface 21 of the PHY section 2 and is reset by a first reset signal RST1 provided from the control circuit CTL. The latch LCH responds to the first set signal SET1 given from the control circuit CTL, latches the count value of the counter CTR, and outputs an actually measured count value ICx corresponding to one cycle of the isochronous cycle. The reference value storage unit CRF previously stores a reference count value IC0 indicating a count number corresponding to one cycle of a reference isochronous cycle. The first adder ADD1 has a latch LC
Subtract the reference count value IC0 stored in the reference value storage unit CRF from the actually measured count value ICx latched at H,
The difference data ICd is obtained and supplied to the data adjustment unit DTU / D.

The data adjustment unit DTU / D repeatedly and sequentially adds the difference data ICd output from the first adder ADD1 in response to the second set signal SET2, and outputs the result as adjustment data SCd. . The data adjustment unit DTU / D is reset by a second reset signal RST2 provided from the control circuit CTL, and initializes the adjustment data SCd to “0”. Frequency storage unit FDT
Is the reference frequency of the isochronous cycle, 24.576.
Reference frequency data F0 corresponding to MHz is stored in advance. The second adder ADD2 adds the data adjustment unit DTU to the reference frequency data F0 held in the frequency storage unit FDT.
The adjustment data SCd output from / D is added to obtain D /
Supply to A converter DAC.

The D / A converter DAC has a second adder AD.
The addition result output from D2 is converted to an analog voltage Vc0. The low-pass filter LPF is a D / A converter DA
An unnecessary high frequency component of the analog voltage Vc0 output from C is removed. The voltage obtained by removing unnecessary high-frequency components of the analog voltage Vc0 by the low-pass filter LPF is the resistance R.
Is supplied to the varicap D via

The varicap D has a small capacitance when the applied voltage is high, and has a large capacitance when the applied voltage is low. Therefore, the crystal oscillator 22 using the crystal oscillator X
Is higher when the capacitance of the varicap D is small, and lower when the capacitance is large.

Incidentally, the master reset signal MRST input to the control circuit CTL, when the system is started,
This is a control signal for initializing the clock correction circuit when a bus reset occurs on the IEEE 1394 bus or when a node becomes a cycle master. The master signal MAST input to the control circuit CTL is a control signal for suppressing the function of the clock correction circuit when the node becomes a cycle master.

Here, the cycle time register will be described. The cycle time register is mounted on all nodes that perform the isochronous transfer service. Also,
The node corresponding to the isochronous transfer has a local clock circuit for generating a local clock of 24.576 MHz as described above. The local clock is used for arbitration of the cycle time register. When writing to the cycle time register, the local clock is initialized to the value included in the write transaction. Also, bus resets and command resets must not affect the local clock. The cycle time register provides a field that specifies the current time value. FIG. 2 shows a field format of the cycle time register.

In FIG. 2, the second count field is a 7-bit readable / writable field, and increases each time a carry from the cycle count field occurs. As an exception, when the value increases when the value is "127", the value returns to "0" in a cyclic manner, and is carried up to a predetermined field of the bus time register mounted on the cycle master node.

The cycle count field is a 13-bit readable / writable field, and increases each time a carry from the cycle offset field occurs. As an exception, if the value increases when the value is "7999", the value is circulated to return to "0" and the carry is carried to the second count field. This value is a fractional part of the number of seconds at the current time, and has a unit of 125 μs.

The cycle offset field is a 12-bit readable / writable field, and is 24.576.
Update every tick of MHz local clock. As an exception, when the value increases when the value is "3071", the value returns to "0" in a circulating manner, and the carry is increased to the cycle count field. This value is the decimal part of the isochronous cycle at the current time, and one cycle of 24.576 MHz is used as a unit.

The cycle slave updates the value of the cycle time register based on the time value received by each cycle start packet. The cycle master node arbitrates the bus to send a cycle start packet each time the cycle count field increases. The cycle master inserts the current cycle time value between each cycle start packet. The value of the cycle time inserted between the cycle start packets is not the time of the cycle start event but the time at which the cycle start packet is transmitted.

Next, the operation of the above-described isochronous communication node will be specifically described mainly with respect to the operation of the clock correction circuit. When the node is operated in the cycle slave mode, the master signal MAST input to the control circuit CTL is set to "1". When the node is operated in the cycle master mode, the master signal MAST is set to "0".

<< Cycle slave (MAST =
"1") >> The cycle start signal ICS is output from the LINK unit 1 when the node receives the cycle start packet. That is, the cycle start signal IC
The output of S indicates the start of the isochronous cycle.

In the cycle slave mode, when the cycle start signal ICS is input to the control circuit CTL,
The control circuit CTL sequentially outputs these signals in the order of the first set signal SET1 → the first reset signal RSET1 → the second set signal SET2.

The first set signal SET1 is supplied to the control circuit C
When TL is input to the latch LCH, the latch LCH
Captures and holds the count value of the counter CTR at that time. The counter CTR has a first reset signal RS
It is reset by T1 and its operation clock is:
The local clock SCLK output from the PHY unit 2 is supplied.

The counter CTR measures the period of the isochronous cycle by counting the local clock, and the latch LCH stores the actually measured count value IC of one cycle of the isochronous cycle measured by the counter CTR.
Hold x.

The reference value storage section CRF stores a reference count value IC0 corresponding to one cycle of a reference isochronous cycle in advance. This reference count value I
The first adder ADD calculates C0 and the actually measured count value ICx.
1, and the difference data ICd shown in Expression 1 is obtained.

[0051]

## EQU1 ## ICd = ICx-IC0

The data adjustment unit DTU / D accumulatively adds the output difference data ICd of the first adder ADD1 in response to the second set signal SET2 and holds the result. It is output as adjustment data SCd.

[0053]

## EQU2 ## SCd = SCd + ICd

The initial value of the adjustment data SCd output from the data adjustment unit DTU / D is "0".

The frequency storage section FDT stores reference frequency data F0 corresponding to the reference frequency 24.576 MHz of the isochronous cycle. The reference frequency data F0 and the previously calculated adjustment data SCd are calculated in a second adder ADD2, and the result is input to a D / A converter DAC and converted into an analog voltage Vc0. Then, the analog voltage Vc0 is applied to the varicap D through the low-pass filter LPF.

From the relationship of Equation 1, the difference data ICd has a negative value when the frequency of the local clock SCLK is low, and a positive value when the frequency of the local clock SCLK is high. The varicap D has a small capacitance when the applied voltage is high, and has a large capacitance when the applied voltage is low. When the capacitance of the varicap D decreases, the oscillation frequency of the crystal oscillation unit 22 increases, and when the capacitance increases, the frequency of the crystal oscillation unit 22 decreases.

As a result, the local clock frequency of the cycle slave becomes the same as the local clock frequency of the cycle master. Therefore, since all the local clock frequencies are equal, the reference cycle offset value such as a time stamp is also equal at all nodes.

<< Cycle Master (MAST = "0") >>
In the cycle master mode, the control circuit CTL always outputs the second reset signal RST2. Therefore, the data adjustment unit DTU / D keeps the reset state, and as a result, always outputs the adjustment data SCd = "0".

Therefore, crystal oscillation section 22 oscillates at an oscillation frequency determined by the set value of frequency storage section FDT.

The master reset signal MRST is used to control the initialization of this clock correction circuit when the system is started, when a bus reset occurs on the IEEE1394 bus, or when a node becomes a cycle master. Supplied to

The master signal MAST is supplied to suppress and control the function of the clock correction circuit when the node becomes a cycle master.

As described above, the frequencies of the local clocks of all the nodes during the isochronous transfer can be made to match the frequency of the same cycle master.

[0063]

As described above, according to the present invention, the local clock frequencies of all the nodes involved in the isochronous communication are adjusted to the master clock which is the local clock of the node serving as the cycle master, and the common clock is always used. An isochronous communication node and a local clock circuit capable of performing isochronous communication can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram schematically showing a configuration of an isochronous communication node to which a local clock circuit according to an embodiment of the present invention is applied.

FIG. 2 is a schematic diagram showing a field format of a cycle time in isochronous transfer for explaining the isochronous communication node of FIG. 1;

FIG. 3 is a block diagram schematically showing a configuration of a conventional isochronous communication node.

FIG. 4 is a diagram for explaining a problem in a case where local clock frequencies of transmitting and receiving nodes do not match in isochronous communication.

[Explanation of symbols]

 Reference Signs List 1 LINK section (link layer) 2 PHY section (physical layer) 11 isochronous interface 12 host interface 13 PHY interface 21 LINK interface 22 crystal oscillation section 23 PLL (phase lock loop) X crystal resonator C1 capacitor C2 capacitor C3 capacitor R resistance D Varicap CTL control circuit CTR counter LCH latch CRF Reference value storage ADD1 First adder DTU / D data adjuster FDT Frequency storage ADD2 Second adder DAC D / A (digital-analog) converter LPF low-pass filter

Claims (5)

[Claims] 1. An isochronous communication node for performing isochronous communication, comprising: a clock generating means for generating a local clock of the node; and a cycle slave operation, wherein the isochronous cycle period is determined by using the local clock based on an isochronous packet reception timing. Clock correction means for measuring and comparing the measured value with a reference value, and controlling the clock generation means based on the comparison result to correct and control the frequency of the local clock. 2. The clock correction means according to claim 1, wherein the clock correction means counts the local clock based on a reception timing of the isochronous packet and measures an isochronous cycle period. The isochronous communication node according to claim 1, further comprising: an error detection unit that obtains information; and a correction control unit that controls the clock generation unit to correct an error based on the error information. 3. The clock correction means controls the frequency of the local clock by the clock correction means at the time of cycle slave operation, and suppresses the operation of the clock correction means at the time of cycle master operation so that the clock generation means operates at a predetermined speed. 3. The isochronous communication node according to claim 1, further comprising control means for operating at a frequency. 4. A local clock circuit provided in an isochronous communication node for performing isochronous communication, comprising: a clock generating means for generating a local clock; and counting the local clock based on an isochronous packet reception timing to measure an isochronous cycle period. A time measuring means, an error detecting means for obtaining error information by comparing a measured value of the time measuring means with a reference value, a correction control means for controlling the clock generating means to correct an error based on the error information, A local clock circuit comprising: 5. A local clock circuit provided in an isochronous communication node for performing isochronous communication, comprising: a clock generating means for generating a local clock; and counting the local clock based on a reception timing of the isochronous packet to measure an isochronous cycle period. A time measuring means, an error detecting means for obtaining error information by comparing a measured value of the time measuring means with a reference value, a correction control means for controlling the clock generating means to correct an error based on the error information, A cycle slave operation and a cycle master operation are discriminated, and in the cycle slave operation, the clocking means, the error detection means and the correction control means are used to perform correction control of the frequency of the local clock. ,error By suppressing the operation of the means and the correction control means output, the local clock circuit, characterized by comprising a control means for operating said clock generating means at a predetermined frequency.