JP2001053280A - Mos transistor and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a MOS transistor and a method of manufacturing it, where a substrate bias effect peculiar to an SOI substrate ca be restrained without increasing a MOS transistor formed on the SOI substrate in element area or in junction leakage caused by crystal defects. SOLUTION: A MOS transistor is equipped with an SOI substrate, composed of a support substrate 10 and a buried insulating film 11 and a body region 12 provided to the substrate 10, a gate electrode 14 formed on the body region 12 trough the intermediary of a gate insulating film 13, and a drain region 15 and a source region 16 are formed in the body region 12 sandwiching the gate electrode 14 between them, where the source region 16 is equipped with an source region 17 extended in the direction of the drain region 15 along an interface between the buried insulating film 11 and the body region 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a MOS transistor and a method of manufacturing the same, and more particularly, to a MOS transistor in which a substrate bias effect is reduced by adding an extension region to a source region, and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, to reduce the power consumption and speed of a CMOS LSI in a low power supply voltage operation, a body region comprising a buried oxide film and a silicon single crystal film on a silicon substrate has been conventionally used. S with
Using an OI (Silicon On Insulator) substrate, this SOI
It is known that it is effective to form a CMOS on a substrate, and various semiconductor devices using an SOI substrate are applied to multimedia-related devices such as mobile phones and mobile terminal devices. .

A MOS transistor formed on an SOI substrate realizes lower power consumption and higher speed than a MOS transistor formed on bulk silicon. The biggest reason is that the buried oxide film of the SOI substrate reduces the parasitic capacitance such as the junction capacitance of the semiconductor element. This will be described in more detail as follows.

The power consumption (P) and signal delay time (τ) of a CMOS LSI are expressed by the following equations. P = C _load · Vdd · f (1) τ = C _load · Vdd / I _DSAT (2) (C _load is the load capacity of the circuit, Vdd is the power supply voltage, f is the operating frequency, and I _DSAT is saturated. This is the drain current.)

The capacitance of the gate insulating film is C _OX , the gate width is W,
Assuming that the gate length is L, the carrier mobility is μ, and the threshold value of the MOS transistor is Vth, the saturation drain current _IDSAT
It is expressed as _{I DSAT = W · μ · C} OX / L · (Vdd-Vth) 2.

[0006] In a MOS transistor formed on an SOI substrate, the source / source voltage is reduced by the capacity of a depletion layer under a buried oxide film.
Since the drain junction capacitance is reduced, C _load in the above equation (1) is reduced, and power consumption is reduced. Further, the body region made of silicon single crystal on the buried oxide film is completely depleted. In the FD (Fully Depleted) mode, the gate voltage is effectively applied to the gate insulating film capacitance because the body region capacitance and the buried oxide film capacitance are connected in series to reduce the total parasitic capacitance. As a result, the sub-threshold characteristic of the MOS transistor formed on the SOI substrate becomes sharp, the threshold voltage (Vth) at the same off-current decreases, and _IDSAT increases in the above equation (2), and the signal delay time increases. Reduced.

However, since the body region on the SOI substrate on which the MOS transistor is formed is surrounded by the buried oxide film and the element isolation film and is in an electrically floating state, charges tend to accumulate. There is a problem that it is easily affected by the potential. These effects are called substrate bias effects. In a MOS transistor, electrons generate high energy due to a strong electric field near the drain and cause impact ionization. However, in the case of a MOS transistor formed on an SOI substrate, holes generated by impact ionization are easily accumulated in a body region, and the body region is damaged. Be positively biased. The accumulation of holes in the body region is caused by the potential barrier (Φh) with respect to the holes at the source end being PD
(Partially Depleted) mode is remarkable in the SOI MOS transistor. In this case, the body region is positively biased, the threshold voltage of the MOS transistor decreases, and the drain voltage-drain current characteristic (Vds-Ids)
Characteristic), a kink phenomenon occurs in which Ids abnormally increases. FD (Fu) having a low potential barrier against holes at the source end
lly Depleted) mode is PD (Partially Depleted)
Although no kink like the mode appears, majority carriers generated by impact ionization serve as a base current, and a parasitic bipolar transistor operates, resulting in a decrease in source-drain breakdown voltage and an increase in off-state current.

As a method for solving this problem, holes can be escaped from the body region by making a substrate contact with the body region, and the above-described substrate bias effect in the SOI element can be eliminated. But with this method,
An increase in the area of a region for making contact with the body region hinders high integration of the LSI.

On the other hand, as a method of suppressing the substrate bias effect without increasing the element area, a method of introducing a crystal defect into source / drain regions has been devised. For example, Japanese Patent Application Laid-Open No. 9-219528 and References (T. Ohno, M. Takahashi, AO
htaka, Y. Sakakibara and T. Tsuchiya: “Suppression of
the Parasitic Bipolar Effect in Ultra-Thin-FilmnM
OSFETs / SIMOX by ArIon Implantation into Source / Dra
in Regions ”: IEDMTech.Dig.pp627-630 (1995))
As shown in FIG. 5, a gate insulating film 13 and a gate insulating film 13 are formed on an SOI substrate including a buried oxide film 11 formed sequentially on a silicon substrate 10 and a body region 12 made of p-type silicon single crystal. An electrode 14 is formed, and an SOI including a drain 15 and a source 16 formed so as to sandwich gate electrode 14 in body region 12 is formed.
In the MOS transistor, a method is described in which a rare gas ion such as Ar is implanted into the drain 15 and the source 16 to form the crystal defect layer 50. In this method, crystal defects introduced by argon ions serve as recombination centers for electrons and holes, and holes are extinguished to reduce accumulation in the body region.

However, this SOI MOS transistor has the following problems. That is, in order for crystal defects introduced into the source 16 and the drain 15 by the argon ion implantation to function as recombination centers of holes generated in the body region 12, the crystal defect layer 50 must be formed at the junction surface between the source 16 and the drain 15. Should be arranged within a distance of less than the diffusion length of holes as minority carriers.
Due to their very short duration, they are very difficult to control by ion implantation and annealing. This crystal defect layer 5
If 0 crosses the junction surface of the source 16 or the drain 15, the junction leak of the source 16 or the drain 15 increases remarkably, causing a problem of deteriorating the MOS transistor characteristics.

Another method for suppressing the substrate bias effect without increasing the element area is to lower the electron barrier (Φh) for the source and drain holes. For example, JP-A-8-213622 and literature (M. Yoshimi, M.
Terauchi, A. Murakoshi, M. Takahashi, K. Matsuzaw
a, N.Shigyo and Y.Ushiku: “Technology Trends ofs
ilicon-On-Insulator-It's advantages and problems t
o be Solvde "IEDM Tech. Dig. Pp429-432 (1994)) has a buried oxide film 11 sequentially formed on a silicon substrate 10 and a body region composed of a p-type silicon single crystal as shown in FIG. A gate insulating film 13 and a gate electrode 14 are formed on an SOI substrate constituted by the SOI substrate 12 and a drain 15 and a source 16 are formed in the body region 12 so as to sandwich the gate electrode 14. In this SOI MOS transistor, a method is described in which a SiGe layer 60 of germanium (Ge) ions is formed between a drain 15 and a source 16. In this method, the source 16 and the drain 15 are formed of SiGe and Si.
By forming an Sn or PbS layer, the source 16 and the drain 1
5, the electron barrier (Φh) for the holes is lowered, and the holes are more likely to flow into the source 16, so that the accumulation of holes can be prevented. However, in this method, the use of germanium (Ge) or lead (Pb) causes a problem of complicated processes and apparatuses and a problem of cross contamination of the processes.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and suppresses a substrate bias effect peculiar to an SOI substrate without increasing a junction leak due to an element area or a crystal defect of a MOS transistor formed on the SOI substrate. And a method for manufacturing the same.

[0013]

According to the present invention, there is provided an SOI substrate in which a buried insulating film and a body region are laminated on a support substrate, and a gate electrode formed on the body region via a gate insulating film. A drain region formed on one side of the body region and a source region formed on the other side of the body region so as to sandwich the gate electrode, wherein the source region extends along the interface between the buried insulating film and the body region. MO having extended source region extended in two directions
An S transistor is provided.

Further, according to the present invention, there is provided (a) an SO having a buried insulating film and a body region laminated on a supporting substrate.
Forming a gate electrode on the I-substrate via a gate insulating film; (b) ion-implanting arsenic and phosphorus into a source region forming region in the body region; Heat treatment for a predetermined time to form a source region having an extended source region extending in the direction of the drain region along the interface between the buried insulating film and the body region; and (c) forming a drain region in the body region. A method for manufacturing a MOS transistor is provided, in which arsenic and / or phosphorus is ion-implanted into a region and heat-treated at a temperature higher than the temperature and for a shorter time than the predetermined time to form a drain region.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A MOS transistor according to the present invention
Basically, an SOI substrate in which a buried insulating film and a body region are laminated in this order on a supporting substrate, a gate electrode formed on the body region via a gate insulating film, and a body region sandwiching the gate electrode And a source region formed on the other side. Here, the SOI substrate is not particularly limited as long as it is a commonly used material, structure, film thickness, and the like. For example, bonded SOI (BESOI), SIM
Examples include those used as OX (Separation by Implantation of Oxygen) type substrates.

As the supporting substrate, for example, an element semiconductor substrate such as silicon, germanium, etc., GaAs, AlN, Z
Various substrates such as a compound semiconductor of III-V group or II-VI group such as nSe and CdTe, and an insulating substrate such as sapphire, quartz, glass, and plastic can be used.
Among them, silicon is preferable, and single crystal silicon is particularly preferable.

As the buried insulating film, for example, SiO ₂
Film, SiN film and the like. Above all, a SiO ₂ film is preferable. At this time, the film thickness can be appropriately adjusted in consideration of the characteristics of the semiconductor device to be obtained, the height of an applied voltage when the obtained semiconductor device is used, and the like.
About 00 to 400 nm.

The body region is a semiconductor thin film functioning as an active layer for forming a transistor, and includes an element semiconductor such as silicon and germanium, GaAs, AlN, and the like.
It can be formed as a thin film made of a compound semiconductor of III-V group or II-VI group such as ZnSe or CdTe. Among them, a silicon thin film, particularly a single crystal silicon thin film, is preferable. The film thickness of the body region is determined, for example, by taking into account the characteristics of the semiconductor device to be obtained and the like.
It can be adjusted as appropriate by various parameters such as the junction depth of the drain region, the depth of the channel region on the surface of the surface semiconductor layer, and the impurity concentration. In the body region, a source / drain region is formed as will be described later, and a channel region is formed. Therefore, the impurity concentration (for example, phosphorus,
The N type such as arsenic or the P type such as boron) is preferably set to correspond to the threshold value of the semiconductor device to be obtained.

The gate insulating film and the gate electrode formed on the body region are not particularly limited as long as they are generally used in a semiconductor device, such as a material and a film thickness. A film, a silicon nitride film, a laminated film of these, or the like, can be formed to a thickness of about 3 to 10 nm, and the gate electrode is made of polysilicon;
A silicide of a refractory metal such as W, Ta, Ti, Mo, etc .; a polycide composed of these silicides (for example, MoSi ₂ , WSi ₂ ) and polysilicon;
It can be formed with a thickness of about 100 to 200 nm.
Note that the gate electrode may have a sidewall spacer formed of an insulating film in consideration of diffusion of impurities for forming source / drain regions in a lateral direction.

The source / drain regions formed in the body region so as to sandwich the gate electrode are preferably formed with a junction depth equivalent to the thickness of the body region. The impurities may be either N-type or P-type, but are preferably N-type, for example, arsenic or phosphorus in consideration of simplicity of the manufacturing method and practicality. The impurity concentration is not particularly limited. For example, N-type (or P-type)
It may be contained in an amount of about × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ . Note that the source / drain regions preferably contain the same level of impurities. However, the impurity concentration of the drain region may be different from that of the source region depending on the manufacturing method as long as operation is not hindered. Also,
The source / drain regions may have an LDD structure. Further, the source region includes an extended source region extending in the direction of the drain region along the interface between the buried insulating film and the body region. Here, the extended source region preferably has, for example, an N-type (or P-type) impurity concentration lower than that of the source region, for example, 1 × 10 ¹⁹ to 1 × 10 ^20.
about atoms / cm ³ . Further, the extended source region has, for example, a width of 10 to the junction depth of the source region.
It can be formed in a shape of about 30% and a length of about 30 to 50% of the entire channel region.

According to the manufacturing method of the present invention, in the step (a), a gate electrode is formed on a SOI substrate having a buried insulating film and a body region laminated on a supporting substrate via a gate insulating film. I do. The gate insulating film and the gate electrode formed here can be formed by a known method using a known material for forming an ordinary MOS transistor.

In the step (b), arsenic and phosphorus are ion-implanted into the source region forming region in the body region. In this case, the ion implantation is preferably performed by a known method using an implantation mask using a resist or the like so that the ion implantation can be performed only in the source region formation region. This ion implantation needs to be performed so that the source region and the extended source region as described above can be formed by a later heat treatment. For example, arsenic ions are accelerated with an acceleration energy of about 5 to 10 keV, 5 × 10
^At a dose of about ^{14 to} 5 × 10 ¹⁵ atoms / cm ² , phosphorus ions are accelerated at an acceleration energy of about 10 to ²⁰ keV,
A method of implanting at a dose of about 5 × 10 ^{13 to} 5 × 10 ¹⁴ atoms / cm ² may be used. Any of these ion implantations may be performed first. As will be described later, when ions are implanted into the source region simultaneously with the ion implantation into the drain region formation region in the subsequent step (c), the impurity concentration of the finally obtained source / drain region is reduced. In order to obtain an appropriate concentration, the implantation of arsenic ions here is preferably performed at about 5 × 10 ^{14 to} 5 × 10 ¹⁵ atoms / cm ² .

After the ion implantation, heat treatment is performed for a predetermined time at a temperature at which phosphorus diffuses in the body region at an accelerated rate. Here, the temperature at which phosphorus is acceleratedly diffused in the body region is a temperature at which phosphorus is transiently diffused until point defects such as vacancies and interstitial silicon in the body region are recombined to become an equilibrium state. Means The duration of the accelerated diffusion of phosphorus varies depending on the doses of arsenic and phosphorus, the acceleration energy, and the like.
20 minutes, 800 ° C for 30 minutes, 900 ° C for 10 minutes,
It is about 30 seconds at 1000 ° C., and is more remarkable at lower temperatures. Therefore, the temperature at which phosphorus is acceleratedly diffused in the body region can be appropriately selected depending on conditions of ion implantation, the amount of point defects in the body region, and the like.
A temperature lower than 00 ° C, more preferably a temperature of 800 ° C or less, and further preferably a temperature of about 600 to 800 ° C.

The term "predetermined time" means a time during which phosphorus can be diffused at an accelerated rate to form an extended source region in a predetermined area. A predetermined time, for example, corresponding to the above temperature, 1
The time is about 20 to 30 seconds, preferably about 120 to 10 minutes, more preferably about 90 to 30 minutes. The heat treatment here can be performed, for example, by a method such as furnace annealing, lamp annealing, and laser annealing. Thus, a source region having an extended source region extending in the drain region direction along the interface between the buried insulating film and the body region can be formed.

In the step (c), arsenic and / or phosphorus ions are implanted into the drain region forming region in the body region. In this case, ion implantation can be performed by a known method using an implantation mask using a resist or the like so that the ion implantation can be performed only in the drain region formation region. Further, in order to omit the mask forming step, the ion may be similarly implanted into the source region simultaneously with the ion implantation into the drain region forming region without using a mask.
The ion implantation at this time is, for example, arsenic ion,
Acceleration energy of about 10 to 50 keV, 5 × 10 ¹⁴ to
At a dose of about 5 × 10 ¹⁵ atom / cm ² and phosphorus ions, acceleration energy of about 10 to 20 keV,
A method of implanting at a dose of about 5 × 10 ^{13 to} 5 × 10 ¹⁴ atom / cm ² may be used. When both arsenic ions and phosphorus ions are used, it can be performed according to the case where only arsenic ions or only phosphorus ions are used.

After the ion implantation, a heat treatment is performed at a temperature higher than the temperature at which the above-mentioned phosphorus is acceleratedly diffused in the body region and for a shorter time than a predetermined time. Here, higher than the temperature at which phosphorus is acceleratedly diffused in the body region means a temperature at which arsenic implanted in the body region can be electrically activated,
For example, 1000 ° C. or higher, preferably 1000 to 110
About 0 ° C, more preferably about 1025 to 1050 ° C. Further, the time shorter than the predetermined time can be appropriately adjusted depending on the processing temperature.
For about 60 seconds. The high-temperature, short-time heat treatment here can be realized by, for example, RTA.

According to the above-described method for manufacturing a MOS transistor, a MOS having a source region having an extended source region is provided.
A transistor can be formed, and a substrate bias effect can be suppressed. Specifically, it will be described below.

Usually, during heat treatment after ion implantation, impurities diffuse while interacting with crystal defects induced during ion implantation. The diffusion speed in this case is increased as compared with the case where the point defects such as vacancies and interstitial silicon have an equilibrium concentration. This enhanced diffusion continues until the point defects recombine and reach an equilibrium state, and the transient enhanced diffusion (TE
D: Transient Enhanced Diffusion). Therefore, phosphorus and the like in the body region (for example, silicon) pair with interstitial silicon and the like to cause enhanced diffusion. The duration of the enhanced diffusion is, for example, at 700 ° C. for 120 minutes, and is more prominent at lower temperatures.

When phosphorus and arsenic are ion-implanted into the source region of the SOI substrate, the concentration of vacancies and interstitial silicon generated by arsenic implantation becomes higher than the arsenic ion concentration. Therefore, after this, if annealing is performed at a low temperature of, for example, about 700 ° C. for a relatively long time, arsenic does not cause enhanced diffusion, but phosphorus interacts with vacancies and interstitial silicon to cause enhanced diffusion. Since interstitial silicon and the like are excessively generated below the source region in contact with the buried oxide film, the enhanced diffusion of phosphorus is performed along the interface between the buried oxide film and the body region from the source region to the drain region. At the same time as pile-up at the interface with the body region, and at the same time, is taken in the buried oxide film near the interface with the body region. As a result, an extended source region extending at the interface between the buried oxide film and the body region is formed. Since the distance between the source region and the drain region is usually several hundred nm or more in a MOS transistor, the source region and the drain region are easily short-circuited by the source region extended by the accelerated diffusion of phosphorus. Annealing can be controlled.

Thereafter, arsenic is implanted into the drain region,
For example, RTA (rapid Thermal An
neal), arsenic in the source region and the drain region is electrically activated, and at the same time, phosphorus in the source region and phosphorus diffused in the vicinity of the interface between the buried oxide film and the body region due to enhanced diffusion are also electrically activated. Activate. Furthermore, this R
Crystal defects including point defects such as vacancies and interstitial silicon induced by ion implantation during the ion implantation are recovered. less than,
A MOS transistor and a method for manufacturing the same according to the present invention will be described with reference to the drawings.

As shown in FIG. 1, the MOS transistor of the present invention has a buried oxide film 11 on a silicon substrate 10.
A gate electrode 14 is formed on a SOI substrate in which a body region 12 made of p-type silicon single crystal is laminated with a gate insulating film 13 interposed therebetween. The source region 16 is formed in the region 15 and the other. This source area 16
Has an extended source region 17 extending toward the drain region 15 along the interface between the buried oxide film 11 and the body region 12. The MOS transistor is electrically isolated from other MOS transistors by an element isolation film 18 formed from the surface of the body region 12 to a depth reaching the buried oxide film 11. Note that this MOS
The transistor has a surface covered with a plasma silicon oxide film 19 and a source region 16 and a drain region 15.
Are connected to a source electrode 21 and a drain electrode 20, respectively. The MOS transistor can be manufactured by the following method.

First, as an SOI substrate, a film thickness of 700-8
Silicon substrate 1 made of single crystal silicon of about 00 μm
0, acceleration energy about 200 keV, dose 4 ×
10 ¹⁷cm^-2About oxygen (O) ions are implanted,
By annealing at about 1300 ° C., silicon
A buried oxide film 1 having a thickness of about 100 nm is formed on a substrate 10.
1 and a body region 12 having a thickness of about 100 nm,
Then, to ITOX (Internal Thermal Oxidation)
Therefore, the pinhole density of the buried oxide film 11 is reduced.
Then, SIMOX (Separation) as shown in FIG.
 by Implanted Oxygen) A substrate was prepared.

By oxidizing the body region 12 of this SOI substrate, a silicon oxide film 22 was formed. At this time, the silicon oxide film 22 can be adjusted in consideration of the initial film thickness of the body region 12 so that a predetermined film thickness (finally about 60 nm) can be secured in the body region 12. For example, the thickness of the silicon oxide film 22 is 65
In this case, the silicon consumption of the body region 12 is about 30 nm. Therefore, body region 1
2 has a thickness of about 70 nm.

Next, as shown in FIG. 2B, the silicon oxide film 22 on the body region 12 was removed with buffered hydrofluoric acid to which diluted hydrofluoric acid (HF) or ammonium fluoride was added. After that, LOCOS method and STI
The element isolation film 1 having a depth reaching the buried oxide film 11 by using an element isolation technique of a (shallow trench isolation) method.
8 was formed. The body region 12 is treated with buffered hydrofluoric acid to which diluted hydrofluoric acid or ammonium fluoride is added.
If a surfactant is added to the buffered hydrofluoric acid when removing the upper silicon oxide film 22, it is possible to suppress the surface roughness of the body region 12 when the silicon oxide film 22 is over-etched.

Subsequently, as shown in FIG. 2C, a gate insulating film 13 is formed on the body region 12 by a thermal oxidation method, and subsequently, a polycrystalline silicon layer doped with phosphorus (P) by a low pressure CVD method. Is deposited, and the gate electrode 14 is formed by photolithography and reactive ion etching.
Formed. Here, the gate insulating film 13 has a temperature of 800 ° C.
It was formed by pyrogenic oxidation in which oxygen and hydrogen were burned, and had a thickness of about 7 nm. The impurity concentration of phosphorus (P) in the polycrystalline silicon layer is 10 ²⁰ cm ⁻³ or more. The gate electrode 14 is formed of a TCP (Transfo) using chlorine (Cl ₂ ).
Patterning was performed to a line width of 0.35 μm by reactive ion etching using rmer coupled plasma.

Next, as shown in FIG. 3D, one of the gate electrodes 14 is coated with a photoresist 23, and phosphorus (P) is applied to the source region formation region 16a with an acceleration energy of 2.
Arsenic (As) is accelerated at an energy of about 30 keV and a dose of 5 × with a dose of about 0 keV and a dose of about 5 × 10 ¹⁴ cm ^−2.
Ion implantation was performed at about 10 ¹⁵ cm ⁻² . Since the buried oxide film 11 and the gate insulating film 13 are easily broken down by the charging of the SOI substrate, the beam current is used at 1 mA or less, and electrons for neutralizing the charging by the PFG (Plasma Flood Gun) are used for the SOI substrate. The ion implantation was performed while supplying the solution to the substrate.

Subsequently, as shown in FIG. 3E, the photoresist 23 was removed by ashing using oxygen plasma, and low-temperature annealing was performed at 700 ° C. for 1 hour in a diffusion furnace in a nitrogen (N ₂ ) atmosphere. . Due to this annealing, phosphorus (P) causes enhanced diffusion while interacting with vacancies and interstitial silicon generated in large amounts under the source region 16 by arsenic (As) implantation. Since the interstitial silicon is excessively generated below the source region 16 which is in contact with the buried oxide film 11, the enhanced diffusion of phosphorus (P) is caused in the buried oxide film 1 from below the source region 16 toward the drain region.
1 along the interface between the body region 12 and pile up to the interface with the body region 12, and at the same time, are taken into the buried oxide film 11 near the interface with the body region 12 to form the extended source region 17. . The length of the extended source region 17 can be easily adjusted by the annealing time. Here, it was adjusted to about 150 nm.

Next, as shown in FIG. 3F, the source region 16 is covered with a photoresist 24, and arsenic (As) is applied to the drain region forming region 15a with an acceleration energy of 30%.
Ion implantation was performed at about keV and at a dose of 5 × 10 ¹⁵ cm ⁻² . At this time, the buried oxide film 11 and the gate insulating film 13
Was used, the beam current was 1 mA or less, and ion implantation was performed while supplying electrons for neutralizing the charge to the SOI substrate by PFG.

Thereafter, as shown in FIG. 4 (g), the photoresist 24 is removed by ashing using oxygen plasma, and RTA (Rapid Thermal Anneal) is applied at 1000 ° C. for 1 hour.
Performed for 0 seconds. RTA was performed in a nitrogen (N ₂ ) atmosphere at a rate of temperature increase / decrease of 100 ° C./min. By this annealing, arsenic (As) of the source region 16 and the drain region 15 is formed.
Are electrically activated at the same time, the phosphorus (P) in the extended extended source region 17 is also electrically activated. In addition,
The distance between the source / drain regions at this time is 0.4 μm
Adjusted to the extent. In the case of a logic device or the like that requires high speed, the source region 16 and the drain region 1
Thereafter, in order to lower the resistance of No. 5, a silicide layer using titanium (Ti) or cobalt (Co) may be formed on the surfaces of the source region 16 and the drain region 15 by an ordinary method.

Next, as shown in FIG.
A plasma silicon oxide film 19 was deposited by a plasma CVD method using S (Si (OCO ₂ H ₅ ) ₄ ) as a reaction gas, and the plasma silicon oxide film 19 was flattened by CMP (Chemical Mechanical Polishing). Then, RIE by normal photolithography and ICP (Inductive Coupled Plasma) using C ₂ F ₆ as an etching gas.
Then, a contact was opened, and a source electrode 21 and a drain electrode 20 were formed, thereby completing the MOS transistor of this example. Since the thickness of the body region of the SOI substrate is about 70 nm according to this embodiment, the operation is performed in a PD (Partially Depleted) mode at this film thickness.

[0041]

According to the present invention, the source region includes the extended source region extending in the direction of the drain region along the interface between the buried insulating film and the body region. The effective contact area can be increased, and since the source region does not include a crystal defect layer as in the conventional MOS transistor, the junction leakage due to the crystal defect does not increase.
It is possible to eliminate the accumulation of holes in the body region caused by impact ionization, and to suppress a substrate bias effect such as a kink phenomenon.

Further, when the extended source region is set at an impurity concentration lower than the impurity concentration of the source region, the potential barrier of holes caused by the impurity concentration difference is reduced, and the drain region is reduced. Holes generated by impact ionization in the vicinity are drawn into the source region more, so that the accumulation of holes can be eliminated and the substrate bias effect can be further suppressed. Further, according to the method for manufacturing a MOS transistor of the present invention, problems such as cross-contamination can be solved while preventing the manufacturing process from becoming complicated, thereby improving the yield and reducing the manufacturing cost. .

[Brief description of the drawings]

FIG. 1 is a schematic sectional view of a main part showing an embodiment of a MOS transistor of the present invention.

FIG. 2 is a schematic cross-sectional manufacturing process diagram of a main part showing an embodiment of a method for manufacturing a MOS transistor according to the present invention.

FIG. 3 is a schematic cross-sectional manufacturing process diagram of a main part showing an embodiment of a method for manufacturing a MOS transistor according to the present invention.

FIG. 4 is a schematic cross-sectional manufacturing process view of a main part showing an embodiment of a method for manufacturing a MOS transistor according to the present invention.

FIG. 5 is a schematic sectional view of a main part showing a conventional MOS transistor.

FIG. 6 is a schematic sectional view of a main part showing a conventional MOS transistor.

[Explanation of symbols]

 Reference Signs List 10 silicon substrate (support substrate) 11 buried oxide film 12 body region 13 gate insulating film 14 gate electrode 15 drain region 16 source region 17 extended source region 18 element isolation film 19 plasma silicon oxide film 20 drain electrode 21 source electrode 22 silicon oxide film 23, 24 Photoresist

Continued on the front page F term (reference) HL05 HM02 HM12 HM15 NN02 NN23 NN33 NN62 NN66 QQ04 QQ17 QQ19

Claims (4)

[Claims] An SOI substrate in which a buried insulating film and a body region are stacked on a supporting substrate; a gate electrode formed on the body region via a gate insulating film; and the body region sandwiching the gate electrode. And a source region formed on the other side, wherein the source region includes an extended source region extending in a drain region direction along an interface between the buried insulating film and the body region. A MOS transistor, comprising: a MOS transistor; 2. The MOS transistor according to claim 1, wherein said extended source region has an impurity concentration lower than that of said source region. 3. A gate electrode is formed via a gate insulating film on an SOI substrate in which a buried insulating film and a body region are stacked on a supporting substrate, and (b) a source region in the body region. Arsenic and phosphorus are ion-implanted into the formation region, and a heat treatment is performed for a predetermined time at a temperature at which phosphorus is acceleratedly diffused in the body region, and is extended in a drain region direction along an interface between the buried insulating film and the body region. (C) ion-implanting arsenic and / or phosphorus into the drain region forming region in the body region, and performing a heat treatment at a temperature higher than the temperature and for a shorter time than the predetermined time. Forming a drain region by forming the drain region. 4. The method according to claim 3, wherein in the step (c), ions are implanted into the source region simultaneously with the drain region forming region, and heat treatment is performed at the same temperature and time.