JP2001045380A - Video data processing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a video data processing circuit for reducing the scale and occupancy area of a memory circuit for storing fixed pattern noise data, and for miniaturizing the chip at the time of realizing one chip integration. SOLUTION: A fixed pattern noise extracting circuit 12 extracts fixed pattern noise data indicating a fixed pattern noise from video data, and a data compressing circuit 21 compresses the extracted fixed pattern noise data, and a memory circuit 13 stores the data, and a data expanding circuit 22 reads the fixed pattern noise data of the memory circuit, and expands and decodes the data at a ratio corresponding to the data compression rate of the data compressing circuit, and a fixed pattern noise removing circuit 14 calculates a difference between the video data and the decoded fixed pattern noise data, and outputs it as corrected video data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a video data processing circuit for removing fixed pattern noise data (digital data) representing fixed pattern noise from video data (digital data).

[0002]

2. Description of the Related Art As a conventional circuit of this kind, for example, there is a circuit disclosed as an "offset correction circuit" in Japanese Patent Publication No. Hei 7-61133. FIG. 2 is a configuration example in the case where the technology described in this publication is applied to a general imaging device. In the figure, video data output from an image sensor 11 typified by a CCD type, a MOS type, a CMOS type, etc., includes fixed pattern noise.

[0003] In order to remove the fixed pattern noise, for example, a fixed pattern noise is obtained by integrating video data obtained when a subject having a uniform color and brightness is photographed several times and extracting data from which random noise has been removed. An extraction circuit 12. The fixed pattern noise extraction circuit 12
The fixed pattern noise data for one frame extracted in step (1) is stored in the frame memory 13, and the fixed pattern noise elimination circuit 14 receives the video data output from the image sensor 11 as one input, and
Is read out as the other input, and the data obtained by calculating the difference between the two for each pixel is output as corrected video data.

[0004]

In recent years, there has been an increasing demand for downsizing of the device. In response to this demand, the image sensor 11 has been reduced, and the fixed pattern noise extraction circuit 12, the frame memory 13 and the fixed pattern noise elimination circuit 14 have been required. Is considered to be a one-chip LSI in which the data is stored in a one-chip LSI.
The area occupied by the reduction in the size of the image sensor 11 is determined by the specifications of the optical system. On the other hand, when considering each circuit as a single chip, there is a problem to be solved that the area occupied by the frame memory 13 is the largest and it is difficult to reduce the size of the chip.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and has been made to reduce the size and area occupied by a memory circuit for storing fixed pattern noise data.
It is an object of the present invention to provide a video data processing circuit capable of realizing miniaturization (reduction) of a chip when it is formed into a chip.

[0006]

According to the present invention, there is provided a fixed pattern noise extraction circuit for extracting fixed pattern noise data representing fixed pattern noise from video data, and a fixed pattern noise extraction circuit. A data compression circuit for compressing the extracted fixed pattern noise data, a memory circuit for storing the fixed pattern noise data compressed by the data compression circuit, and a fixed pattern noise data stored in the memory circuit. A data decompression circuit that decompresses and decodes data at a ratio corresponding to the data compression ratio, and calculates a difference between video data and fixed pattern noise data decoded by the data decompression circuit, and outputs the result as corrected video data. A video data processing circuit comprising: a fixed pattern noise elimination circuit; .

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on preferred embodiments shown in the drawings. FIG. 1 is a block diagram showing a configuration of an embodiment of a video data processing circuit according to the present invention. In the figure, the same elements as those in FIG. 2 showing the conventional circuit are denoted by the same reference numerals, and the description thereof will be omitted. This circuit comprises a fixed pattern noise extraction circuit 12 and a frame memory 1
2 is different from FIG. 2 in that a data compression circuit 21 is provided between the frame memory 3 and the data compression circuit 21 and a data decompression circuit 22 is provided between the frame memory 13 and the fixed pattern noise elimination circuit 14. That is, the video data circuit according to the present invention comprises a fixed pattern noise extraction circuit 12 for extracting fixed pattern noise data representing fixed pattern noise from video data.
A data compression circuit 2 for compressing the fixed pattern noise data extracted by the fixed pattern noise extraction circuit 12
1; a memory circuit 13 for storing the fixed pattern noise data compressed by the data compression circuit 21; and a readout of the fixed pattern noise data stored in the memory circuit 13 corresponding to the data compression ratio of the data compression circuit 21. A data decompression circuit 22 for decompressing and decoding data at a predetermined ratio, and the video data and the data decompression circuit 2
And a fixed pattern noise elimination circuit 14 for obtaining a difference from the fixed pattern noise data decoded in step 2 and outputting it as corrected video data.

The data compression circuit 21 includes:
MPEG (Moving Picture Experts Group) or H.264. 26
D such as 1, which is adopted in the international standard method of image compression
A device adopting a high efficiency coding technique (data compression) using orthogonal transform called CT (Discrete Cosine Transform) is used. In response to this, a data decompression circuit 22 that decodes video data by an arithmetic process called inverse DCT is used. In this case, the compression ratio of the data compression circuit 21 and the data expansion circuit 2
2 and the elongation ratio.

As described above, the fixed pattern noise data extracted by the fixed pattern noise extraction circuit 12 is subjected to high-efficiency encoding, that is, data compression by the data compression circuit 21 and is stored in the frame memory 13. By reading data and decoding it by the data expansion circuit 22, that is, by expanding the data and adding it to the fixed pattern noise removal circuit 14, the scale of the frame memory 13 as a memory circuit and its occupied area can be reduced. Each circuit other than the image sensor 11 is
When a chip is formed, the size of the chip can be reduced.

In addition, when viewed as a video signal, a fixed noise pattern has a higher rule than a normal video, so that a high compression rate can be expected, and the circuit scale of the frame memory due to the adoption of data compression and decompression is reduced. A great effect can be obtained for reduction.

In particular, in a configuration such as a CMOS type image sensor in which a sensor portion and a peripheral circuit are mixed on one chip, the effect of reducing the chip size by reducing the scale of the memory circuit is great. .

[0012]

As is apparent from the above description, according to the present invention, the fixed pattern noise data is compressed and stored in the memory circuit, this data is read and decoded, and the data is used for correcting the video data. Therefore, the size and the area occupied by the memory circuit for storing the fixed pattern noise data can be reduced, and the size of the chip can be reduced when it is integrated into one chip.

Particularly, in a CMOS image sensor, the effect of reducing the chip size by reducing the scale of the memory circuit is great.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a video data processing circuit according to the present invention.

FIG. 2 is a block diagram illustrating a configuration of a video data processing circuit in which a conventional offset correction circuit is applied to a general imaging device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Image sensor 12 Fixed pattern noise extraction circuit 13 Frame memory (memory circuit) 14 Fixed pattern noise removal circuit 21 Data compression circuit 22 Data expansion circuit

Claims (1)

[Claims] A fixed pattern noise extraction circuit for extracting fixed pattern noise data representing fixed pattern noise from video data; a data compression circuit for compressing the fixed pattern noise data extracted by the fixed pattern noise extraction circuit; A memory circuit for storing the fixed pattern noise data compressed by the data compression circuit, and reading the fixed pattern noise data stored in the memory circuit and expanding the data at a ratio corresponding to the data compression ratio of the data compression circuit. A video decompression circuit for decoding, and a fixed pattern noise elimination circuit for obtaining a difference between the video data and the fixed pattern noise data decoded by the data decompression circuit and outputting the difference as corrected video data. Data processing circuit.