JP2001045091A - Data converter and data transmission/reception method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain input/output of data between devices that have a same digital interface but have provision for different data forms only. SOLUTION: The data converter 1 receives DV data with a DV format externally, decodes the DV data into a base band signal, encodes the base band signal into MPEG data with an MPEG format and outputs the MPEG data externally as its feature so as to interconnect devices that have provision for different data forms from each other in spite of provision of a digital interface of a same standard in compliance with different data forms.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data converter and a data transmitting / receiving method for inputting and outputting data between digital data having a first data format and digital data having a second data format.

[0002]

2. Description of the Related Art In recent years, AV (Audio Video)
With the development of devices and information processing methods, for example, various types of AV devices such as digital televisions and digital video cameras may be connected to personal computers to form a network and used. Transmission and reception of data between devices in this network is performed for desired data between arbitrary devices in this network. In such a case, the device that outputs data and the device that inputs data need to be compatible with data of the same format and have the same decoding circuit and / or encoding circuit.

[0003]

In the above-described network system, the devices must be unified into the same data format in the network, and the device that outputs data and the device that inputs data are the same. Except for the case of having the same decoding circuit and / or encoding circuit corresponding to the format, even if data is transmitted from a device that inputs data, the data cannot be processed. As described above, when data formats are different between arbitrary devices, at present, the devices cannot input / output data despite having a digital interface of the same standard.

The present invention has been proposed in view of such circumstances, and has a digital interface of the same standard, and enables connection between devices that support digital data of different formats. It is an object of the present invention to provide a data conversion device and a data transmission / reception method that allow a user to freely use desired data having a different format between desired devices constituting a network without being aware of the data format.

[0005]

According to the present invention, there is provided a data conversion apparatus for inputting first digital data having a first digital format and transmitting a first digital data having a second digital format. And I / O means for outputting the second digital data, and signal conversion means for converting the first digital data having the first digital format into the second digital data having the second digital format. And

[0006] The data converter according to the present invention configured as described above connects devices that have a common digital interface but support only different formats.

A data transmitting / receiving method according to the present invention, which achieves the above object, inputs first digital data having a first data format to be transmitted, and converts the first digital data into a baseband signal. And encoding the baseband signal into second digital data having a second data format different from the first data format, and outputting the second digital data.

The data transmission / reception method according to the present invention configured as described above performs data input / output between devices having a common digital interface but corresponding to different types of digital data.

[0009]

FIG. 1 is a block diagram showing a specific configuration of a first embodiment of a data conversion device to which the present invention is applied. This device uses the IEEE as shown in FIG.
E (The Institute of Electrical and Electronics En
gineers, Inc.) and is characterized by isochronous transfer, IEEE Std. 1394-1995 IEEE Standard for a
HighPerforance serial Bus standard (hereinafter IEEE13)
This is a data conversion device 1 for inputting digital data and / or outputting digital data via an IEEE 1394 serial bus conforming to IEEE standard 94.

The data converter 1 includes an input / output circuit 3 for inputting DV data and / or outputting MPEG data via an IEEE 1394 serial bus 2, and a signal converter 4. The signal conversion unit 4 includes a DV decoding circuit 5 for decoding DV data into a baseband signal, and an MPEG encoding circuit 6 for encoding the baseband signal into MPEG data.

In the data converter 1 described above, the input / output circuit 3 is connected to the D / D converter via the IEEE1394 serial bus 2.
V data is input, and this DV data is supplied to the DV decoding circuit 5. And the MPEG encoding circuit 6
G data is supplied, and the MPEG data is transferred to IEEE1
Output via the 394 serial bus 2.

The DV decoding circuit 5 outputs a DV signal from the input / output circuit 3.
Supplied with data. The DV decoding circuit 5 decodes the DV data into a baseband signal, and supplies the baseband signal to the MPEG encoding circuit 6. MPE
The G encoding circuit 6 converts the supplied baseband signal to MP
The data is encoded into EG data, and the MPEG data is supplied to the input / output circuit 3.

In the data conversion device 1 comprising the components functioning as described above, the input DV data is converted into MPEG data through a series of steps shown in FIG. 2 and then output.

First, in step S 1, the input / output circuit 3 sends a DV signal having a DV format from outside the data converter 1 via the IEEE 1394 serial bus 2.
The data is input, and the DV data is supplied to the DV decoding circuit 5. Next, in step S2, the DV decoding circuit 5 decodes the DV data into a baseband signal,
It is supplied to the MPEG encoding circuit 6. Next, step S
In step 3, the MPEG encoding circuit 6 encodes the baseband signal into MPEG data and supplies it to the input / output circuit 3. Next, in step S4, the input / output circuit 3 converts the MPEG data from the MPEG encoding circuit 6 into
Output via the IEEE 1394 serial bus 2.

At this time, the DV data supplied from the input / output circuit 3 to the DV decoding circuit, the baseband signal decoded by the DV decoding circuit 5, and the input / output circuit 3 are supplied from the MPEG encoding circuit 6 to perform data conversion. FIG. 3 shows the difference in the frame pulse phase between the MPEG data output to the outside of the apparatus 1 and the MPEG data.

That is, the frame pulse of the baseband signal shown in FIG. 3B decoded by the DV decoding circuit 5 is input to the input / output circuit 3 and supplied to the DV decoding circuit 5 in FIG. The frame pulse of the input DV data shown is delayed by the time Ta required for the DV decoding circuit 5 to decode the DV data into a baseband signal.
In addition, with respect to the frame pulse of the baseband signal shown in FIG. 3B, the frame pulse of the output MPEG data shown in FIG. It is delayed by the time Tb required for the encoding circuit 6 to encode the baseband signal into the MPEG data.

Therefore, the data converter 1 shown in FIG.
Then, the frame pulse (A in FIG. 3) of the DV data which is input to the input / output circuit 3 and supplied to the DV decoding circuit 5, and M
Between the frame pulse (C in FIG. 3) of the MPEG data supplied from the PEG encoding circuit 6 to the input / output circuit 3, the DV decoding circuit 5 decodes the DV data into a baseband signal. A certain synchronization deviation represented by a predetermined delay time Tc (= Ta + Tb) corresponding to the sum of the time Ta required and the time Tb required for the MPEG encoding circuit 6 to encode the baseband signal into MPEG data. It will exist.

By using the data converter 1 having the input / output circuit 3 as described above, it becomes possible to input DV data having the DV format and to output MPEG data having the MPEG format. For example, by decoding DV data,
It can be encoded into EG data.

Next, another configuration of the above-described data converter 1 will be described with reference to FIGS. First, as a second embodiment, a data converter 10 shown in FIG. 4 has a basic configuration similar to that of the data converter 1 shown in FIG. 11 and a second input / output circuit 12. Therefore, the same components as those of the data conversion device 1 shown in FIG. 1 are denoted by the same reference numerals, and detailed description will be omitted.

In the data converter 10, the first input / output circuit 11 inputs DV data via the IEEE 1394 serial bus 2 and supplies the DV data to the DV decoding circuit 5. In addition, the second input / output circuit 12
MPEG data is supplied from the EG encoding circuit 6, and the MPEG data is output via the IEEE 1394 serial bus 2.

Data conversion device 1 configured as described above
0, the DV data input from the outside of the data conversion device 10 undergoes a series of steps shown in FIG.
After being converted into EG data, it is output.

First, in step S5, the first input / output circuit 11 inputs DV data having a DV format from the outside via the IEEE1394 serial bus 2, and supplies the DV data to the DV decoding circuit 5. .
Next, in step S6, the DV decoding circuit 5 decodes the DV data into a baseband signal and supplies the baseband signal to the MPEG encoding circuit 4. Next, in step S7, the MPEG encoding circuit 6 encodes the baseband signal into MPEG data and supplies the MPEG data to the second input / output circuit 12. Next, in step S8, the second input / output circuit 12 outputs the M signal supplied from the MPEG encoding circuit 6.
The PEG data is output to the outside via the IEEE 1394 serial bus 2.

As described above, the first input / output circuit 11 for receiving DV data input from outside the data conversion device 10 outputs the MPEG data to the outside of the data conversion device 10. By providing the input / output circuit 12, DV data, which is a signal having a different format, and MPEG
Data can be separated. As a result, it is possible to avoid confusion that may occur when DV data and MPEG data occupy the same band in the same transmission / reception circuit.

As a third embodiment, a data converter 20 shown in FIG. 6 has the same basic configuration as the data converter 10 shown in FIG. 4, but has a first input / output circuit 21 and a second input / output circuit 21. An output circuit 22 and a delay circuit 23 are provided, and the first input / output circuit 21 can supply DV data to the second input / output circuit 22 with a delay of a predetermined delay time. are doing. Therefore, the same components as those of the data conversion device 1 shown in FIG. 1 are denoted by the same reference numerals, and detailed description will be omitted.

In the data converter 20, a first input / output circuit 21 receives DV data from the outside via the IEEE1394 serial bus 2 and converts the DV data into a DV signal.
It is supplied to the decoding circuit 5. Also, the first input / output circuit 21
Supplies DV data to the second input / output circuit 22.
The second input / output circuit 22 outputs D
V data is supplied directly. The second input / output circuit 2
2 is supplied with MPEG data from the MPEG encoding circuit 6. The delay circuit 23 delays the frame pulse of the DV data supplied directly from the first transmission / reception circuit to the second input / output circuit 22 by a delay time, and synchronizes it with the MPEG data supplied from the MPEG encoding circuit. IEEE1
Output via the 394 serial bus 2.

Data converter 2 configured as described above
0, the DV data input from the outside of the data converter 20 undergoes a series of steps shown in FIG.
After being converted into EG data, it is output to the outside.

First, in step S 9, the first input / output circuit 21 inputs DV data having the DV format via the IEEE 1394 serial bus 2, supplies the DV data to the DV decoding circuit 5, and The signal is supplied to the circuit 23. Next, in step S10, the DV decoding circuit 5 decodes the DV data into a baseband signal, and supplies the baseband signal to the MPEG encoding circuit 6. Next, in step S11, the MPEG encoding circuit 6
Is supplied with a baseband signal from the DV decoding circuit 5,
This baseband signal is encoded into MPEG data,
It is supplied to the second input / output circuit 22. Next, step S
12, the second input / output circuit 22 uses the MPEG
The data and the DV data delayed by a predetermined time by the delay circuit 23 are synchronized, and the MPEG data and the DV data are simultaneously output to the outside via the IEEE 1394 serial bus 2.

When a signal is sent in the process described above,
The input DV data input from the first input / output circuit 21 and supplied to the DV decoding circuit 5, the baseband signal decoded by the DV decoding circuit 5, and the second input / output circuit 22
The output MPEG data supplied and output from the EG encoding circuit 6 and the first input / output circuit 21 to the second input / output circuit 2
The difference in the frame pulse phase between the output DV data directly supplied to the output 2 and output is as shown in FIG.

A shown in FIG. 8 is a frame pulse of DV data which is inputted to the first input / output circuit 21 and supplied to the DV decoding circuit 5, and B is a frame pulse obtained by the DV decoding circuit 5 based on the DV data. Time Ta required for decoding into band signal
C is a frame pulse delayed only by B, and the MPEG encoding circuit 6
This is a frame pulse of MPEG data output from the second input / output circuit, delayed by a time Tb required for encoding into G data, and delayed by a time Tc (= Ta + Tb) compared to A. D is a frame pulse of DV data that is delayed by the delay circuit 23 by the same time as the time Tc and directly supplied to the second output circuit 22.

The delay circuit 23 converts the DV data directly supplied from the first input / output circuit 21 to the second input / output circuit 22 into a processing time required by the DV decoding circuit 5 and the MPEG encoding circuit 6. Delay by a predetermined delay time Tc,
The output is synchronized with the MPEG data.

As described above, the delay circuit 23 delays the frame pulse of the DV data supplied directly from the first input / output circuit 21 to the second input / output circuit 22 by the above-described delay time. The MPEG data output from the converter 20 is a signal that is always synchronized with the input DV data. As a result, it is possible to avoid confusion that may occur due to a phase shift between the frame pulse of the input DV data and the frame pulse of the output MPEG data.

Next, a fourth embodiment shown in FIG. 9 is an application of the data converter 20 shown in FIG.
It comprises a data conversion device 31 and another data processing device 32. The data converter 31 includes input circuits 33, 34, and 35 for inputting DV data, a first input / output circuit 36 for outputting MPEG data and DV data via the IEEE 1394 serial bus 2, and a second input / output circuit. 37,
A third input / output circuit 38, and input circuits 33, 34 and 35;
Decoding circuits 5a, 5b and 5c corresponding to the MPEG decoding circuit 5a, 5b and 5c
a, 6b and 6c and delay circuits 23a, 23b and 23
c.

The other data processing device 32 includes another input / output circuit 39, and can input and output data to and from the data conversion device 31 via the IEEE1394 serial bus 2.

In the above-described fourth embodiment shown in FIG. 9, each component functions as follows. Input circuit 33
Receives DV data and supplies the DV data to the DV decoding circuit 5a. Further, the input circuit 33 directly supplies the DV data to the first input / output circuit 36 via the delay circuit 23a. The input circuit 34 inputs DV data,
This DV data is supplied to the DV decoding circuit 5b. Further, the input circuit 34 directly supplies the DV data to the second input / output circuit 37 via the delay circuit 23b. Input circuit 3
5 inputs the DV data and supplies the DV data to the DV decoding circuit 5c. The input circuit 35 directly supplies the DV data to the third input / output circuit 38.

The first input / output circuit 36 includes a delay circuit 23a
DV data is directly supplied from the input circuit 33 via the. The first input / output circuit 36 is supplied with MPEG data from the MPEG encoding circuit 6a. These DVs
The data and the MPEG data are synchronized.

The second input / output circuit 37 includes a delay circuit 23b
DV data is directly supplied from the input circuit 34 via the. The second input / output circuit 37 is supplied with MPEG data from the MPEG encoding circuit 6b. These DVs
The data and the MPEG data are synchronized. Third
Is directly supplied with DV data from the input circuit 35 via the delay circuit 23c. Further, the third input / output circuit 38 outputs an MPEG signal from the MPEG encoding circuit 6c.
Supplied with data. These DV data and MPEG data are synchronized.

The other input / output circuit 39 includes input circuits 33 and 3
4 and 35, the desired DV data
The selected data is transmitted to the input / output circuits 36 to 38 to which the desired DV data is supplied, and the input / output circuits other than the selected input / output circuit are supplied with the DV data. Make a transmission stop request. The other input / output circuit 39 is supplied with MPEG data from the first input / output circuit 36, the second input / output circuit 37, and the third input / output circuit 38, and receives desired MPEG data from the selected input / output circuit. DV data is supplied. At that time, the 3
One MPEG data and one DV data are I
Stored in an EEE1394 isochronous packet,
The data is output from the input / output circuits 36 to 38 to another data processing device 32 via the IEEE 1394 serial bus 2.

The delay circuits 23a, 23b and 23c are provided from the input circuits 33, 34 and 35 to the first input / output circuit 36,
Each of the DV data supplied to the second input / output circuit 37 and the third input / output circuit 38 is converted into the DV decoding circuits 5a to 5a.
c and a predetermined delay time corresponding to the processing time required by the MPEG encoding circuits 6a to 6c, and is output in synchronization with the MPEG data.

The DV decoding circuit 5a decodes the DV data supplied from the input circuit 33 into a baseband signal, and supplies this baseband signal to the MPEG encoding circuit 6a. The DV decoding circuit 5b decodes the DV data supplied from the input circuit 34 into a baseband signal, and supplies the baseband signal to the MPEG encoding circuit 6b.
The DV decoding circuit 5c outputs the DV supplied from the input circuit 35.
The data is decoded into a baseband signal, and this baseband signal is supplied to the MPEG encoding circuit 6c.

The MPEG encoding circuit 6a encodes the baseband signal supplied from the DV decoding circuit 5a into MPEG data, and supplies the MPEG data to the first input / output circuit 36. The MPEG encoding circuit 6b converts the baseband signal supplied from the DV decoding circuit 5b into an MPEG signal.
The MPEG data is supplied to the second input / output circuit 37. The MPEG encoding circuit 6c
The baseband signal supplied from the DV decoding circuit 5c is represented by M
The MPEG data is encoded into PEG data,
Is supplied to the input / output circuit 38.

In the above-described fourth embodiment, the DV data input to the data converter 31 is converted into MPEG data through a series of steps as shown in FIG. 10, and is output. Here, it is assumed that the input / output circuit 36 is selected by the other input / output circuit 39, for example.

First, in step S13, the input circuits 33, 34 and 35 input DV data, respectively.
These DV data are supplied to the DV decoding circuits 5a, 5b and 5c corresponding to the input circuits 33, 34 and 35, and also to the delay circuits 23a, 23b and 23c corresponding to the input circuits 33, 34 and 35. .

Next, in step S14, the DV decoding circuits 5a, 5b and 5c switch the input circuits 33, 34 and 3
5 are respectively decoded into baseband signals and supplied to MPEG encoding circuits 6a, 6b and 6c.

Next, in step S15, the MPEG
The encoding circuits 6a, 6b and 6c encode the baseband signal from the DV decoding circuit into MPEG data, respectively, and provide a first input / output circuit 36, a second input / output circuit 37, and a third input / output circuit 38 To supply.

Next, in step S16, the first input / output circuit 36, the second input / output circuit 37, and the third input / output circuit 38 are connected to the corresponding MPEG encoding circuit 6 respectively.
The MPEG data is supplied from a, 6b and 6c, and the MPEG data and the DV data delayed by a predetermined time in the delay circuit in step S13 are synchronized and supplied to another input / output circuit 39. Other input / output circuits 39
Selects the desired DV data from the DV data supplied to the first input / output circuit 36, the second input / output circuit 37, and the third input / output circuit 38.

Next, in step S17, the other input / output circuit 39 issues a DV data transmission request to the selected first input / output circuit 36, and outputs the second input / output circuit 37 and the second input / output circuit 37. A request to stop transmission of DV data is made to the input / output circuit 38 of No.3.

Next, in step S18, the first input / output circuit 36 selected by the other input / output circuit 39 and receiving the request for transmitting the DV data transmits the DV data and the MPEG data.
The data is supplied to another input / output circuit 39 in synchronization with the data. The input / output circuits 37 and 38 which have received the DV data transmission stop request in step 17 supply only the MPEG data to the other input / output circuits 39. At this time, the three MPEG data and one DV data supplied to the other input / output circuit 39 are stored in the IEEE 1394 isochronous packet, respectively, and output via the IEEE 1394 serial bus 2.

That is, in the above-described steps, the IEEE1394 output from the input / output circuits 36, 37 and 38
The bandwidth of the isochronous packet is as shown in FIG.
MPEG data 101 to 103 and DV data 104
Is arranged. A signal 100 is an IEEE 1394 cycle start packet, and includes MPEG data 10
1, 102 and 103 are MPEG encoding circuits 6a, 6
And 6c. The DV data 104 is directly supplied from the input circuit 33 selected by another input / output circuit 39. These different types of data are stored and output in IEEE 1394 isochronous packets.

It should be noted that the input circuits 33, 34 and 35
It may be an input / output circuit capable of inputting and outputting via an IEEE 1394 serial bus. It is assumed that the IEEE 1394 isochronous packet has a capacity other than the above-mentioned packet.

As described above, by outputting the desired DV data in addition to the MPEG data in addition to the MPEG data, a limited band can be effectively used and a large number of bands are allocated to the desired data. Will be able to do it. That is, the data conversion device 30 can output desired data in a low-compression data format such as DV data while maintaining high quality.

Next, a plurality of DV data is input, and a plurality of baseband signals decoded by a plurality of
FIG. 12 exemplifies a case where the signals are combined by one encoding circuit. As a fifth embodiment, a data converter 40 shown in FIG. 12 has a basic configuration similar to that of the data converter 1 shown in FIG. 1, except for a first DV decoding circuit 51 and a second DV decoding circuit. 52 is provided.
Therefore, the same components as those of the data conversion device 1 shown in FIG. 1 are denoted by the same reference numerals, and detailed description will be omitted.

The first DV decoding circuit 51 includes an input / output circuit 3
One of a plurality of DV data input by
The data is decoded into a baseband signal, and the baseband signal is supplied to the MPEG encoding circuit 6. Second D
The V decoding circuit 52 decodes the other DV data of the plurality of DV data input by the input / output circuit 3 into a baseband signal, and supplies this baseband signal to the MPEG encoding circuit 6. Here, it is assumed that one of the plurality of DV data is video DV data, and the other DV data is audio DV data.

In the data converter 40, a plurality of DV data input from the outside are converted into MPEG data through a series of steps shown in FIG. 13 and output to the outside. First, in step S19, the input / output circuit 3 transmits the signal via the IEEE 1394 serial bus 2.
Video DV data and audio DV data are input. next,
In step S20, the input / output circuit 3 supplies the video DV data to the first DV decoding circuit 51 and the audio DV data to the second DV decoding circuit 52. Next, step S
At 21, the first DV decoding circuit 51 decodes the video DV data into a video baseband signal, and supplies the video baseband signal to the MPEG encoding circuit 6. On the other hand, the second DV decoding circuit 52
Decodes audio DV data into an audio baseband signal,
It is supplied to the MPEG encoding circuit 6. Next, step S
At 22, the MPEG encoding circuit 6 combines these two types of baseband signals, encodes them into MPEG data, and supplies them to the input / output circuit 3. Next, step S
At 23, the input / output circuit 3 outputs this MPEG data via the IEEE 1394 serial bus 2.

Although the case where a plurality of DV data having the DV format is input has been described above,
For example, the D / D decoding circuit receives the D / D
A signal other than the V data may be directly input.

As described above, the data conversion apparatus shown as an embodiment of the present invention can
It is possible to transmit and receive data between different formats such as the MPEG format and the MPEG format, and if further applied, it is possible to transmit and receive data between different formats while effectively using a limited band and maintaining high quality. .

In the above-described embodiment,
Although the signal flow has been described in detail in the case of receiving DV data and transmitting MPEG data, the MPEG decoding circuit is used instead of the DV decoding circuit, and the DV coding circuit is used instead of the MPEG coding circuit. Data can be received and DV data can be transmitted.

Further, by mounting both types of decoding circuits and encoding circuits, the above-mentioned transmission and reception can be freely performed in either direction.

Also, between data having a format other than the DV format and the MPEG format, data can be transmitted and received by providing a decoding circuit and an encoding circuit corresponding to a format other than the DV format and the MPEG format.

In the above-described embodiment, when converting DV data into MPEG data, decoding is performed up to a baseband signal and then encoded into MPEG data.
However, the format is not limited to time-series signals such as baseband signals.
It can also be encoded into data. This is effective without limiting to data transmission and reception between the DV format and the MPEG format.

Further, the above-described data conversion device can be realized by diverting an existing circuit, and can be mounted on an existing recording / reproducing device or the like.

Further, the transmission / reception here is effective not only in the case of the isochronous transfer illustrated but also in the case of the asynchronous transfer.

[0062]

As described above in detail, the data conversion apparatus according to the present invention has an input of first digital data having a first digital format to be transmitted and a second digital data having a second digital format. An input / output means for outputting digital data; a first digital data having a first digital format and a second digital data having a second digital format.
Signal conversion means for converting the digital data into digital data.

As a result, it becomes possible to connect devices that support digital data of different formats while having a digital interface of the same standard.

Further, the data transmitting / receiving method according to the present invention comprises:
First digital data having a first data format to be transmitted is input, the first digital data is decoded into a baseband signal, and the baseband signal is converted to a first data format different from the first data format. And encoding the second digital data having the second data format and outputting the second digital data.

According to this method, the user can freely use desired data having different formats between desired devices constituting the network without being aware of the data format.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a data conversion device shown as a first embodiment of the present invention.

FIG. 2 shows a data converter receiving DV data and MPEG
5 is a flowchart illustrating a process when transmitting data.

FIG. 3 is a diagram illustrating a frame pulse phase of the data converter.

FIG. 4 is a block diagram illustrating a configuration of a data conversion device shown as a second embodiment of the present invention.

FIG. 5 shows a data conversion device receiving DV data and MPEG
5 is a flowchart illustrating a process when transmitting data.

FIG. 6 is a block diagram illustrating a configuration of a data conversion device shown as a third embodiment of the present invention.

FIG. 7 shows a data converter receiving DV data and MPEG
5 is a flowchart illustrating a process when transmitting data.

FIG. 8 is a diagram illustrating a frame pulse phase of the data conversion device.

FIG. 9 is a block diagram illustrating a schematic configuration according to a fourth embodiment of the present invention.

FIG. 10 shows a data converter receiving DV data and MPE
9 is a flowchart illustrating a process when transmitting G data.

FIG. 11 is a diagram illustrating the bandwidth of an IEEE 1394 isochronous packet.

FIG. 12 is a block diagram illustrating a configuration of a data transmission / reception device shown as a fifth embodiment of the present invention.

FIG. 13 shows a data converter receiving DV data and MPE
9 is a flowchart illustrating a process when transmitting G data.

[Explanation of symbols]

1,10,20,31,40 Data conversion device, 2 I
EEE1394 serial bus, 3 input / output circuit, 4 signal conversion unit, 5, 5a, 5b, 5c DV decoding circuit, 6,
6a, 6b, 6c MPEG encoding circuit, 11, 21
First input / output circuit, 12, 22 Second input / output circuit, 2
3, 23a, 23b, 23c delay circuit, 32 other data converter, 33, 34, 35 input circuit, 38 third input / output circuit, 39 other input / output circuit, 51 first DV decoding circuit, 52 2 DV decoding circuits, 100 I
EEE1394 cycle start packet, 101,
102,103 MPEG data, 104 DV data

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference) DD03 HH61 PP03 PP04

Claims (23)

[Claims] An input / output means for inputting first digital data having a first digital format and outputting second digital data having a second digital format; Signal conversion means for converting the first digital data having the first digital data into the second digital data having the second digital format. 2. The signal conversion means according to claim 1, wherein said signal conversion means inputs first digital data having a first data format received by said input / output means, and decodes the digital data into a baseband signal. 2. The data conversion apparatus according to claim 1, further comprising: an encoding unit that inputs and encodes the second digital data having a second data format different from the first data format. 3. The input / output means has a first input / output means for inputting the first digital data and a second input / output means for outputting the second digital data. The data conversion device according to claim 1, wherein 4. The input / output means inputs the first digital data in real time by synchronous communication,
2. The data conversion device according to claim 1, wherein said second digital data is output in real time by synchronous communication. 5. The data conversion apparatus according to claim 1, wherein said input / output means inputs said first digital data by asynchronous communication and outputs said second digital data by asynchronous communication. . 6. The data conversion apparatus according to claim 3, further comprising delay means for delaying said first digital data input from said first input / output means for a predetermined time. 7. The second input / output means delays the first digital data inputted from the first input / output means by a predetermined time by the delay means, and outputs the second digital data inputted from the encoding means. 7. The data conversion device according to claim 6, wherein said first digital data and said second digital data are output in synchronization with said digital data. 8. The predetermined time is a time required for the decoding means to decode the first digital data into a baseband signal, and the encoding means converts the baseband signal to the second digital data. 7. The data conversion apparatus according to claim 6, wherein the sum is a sum of a time required for encoding. 9. A plurality of first input / output means, a plurality of decoding means and encoding means corresponding to each first input / output means, and the second input / output means comprises a plurality of A first input / output unit having a plurality of first data formats input to the first input / output means;
4. The data conversion apparatus according to claim 3, wherein desired digital data is selected from the digital data and input. 10. The second input / output means is connected to a selected input / output means which is a first input / output means for inputting digital data selected from a plurality of the first input / output means. A request for transmission of the selected digital data is made, and the first input / output means of the plurality of first input / output means other than the selected input / output means is sent to the first input / output means.
10. The data conversion apparatus according to claim 9, wherein a request to stop transmission of the first digital data having the data format is made. 11. The decoding means comprises: first decoding means for decoding one of the plurality of digital data input from the input / output means; and second decoding means for decoding the other digital data. 2. The data conversion device according to claim 1, further comprising means. 12. The encoding means decodes the baseband signal obtained by decoding the one digital data by the first decoding means, and decodes the other digital data by the second decoding means. 12. The apparatus according to claim 11, wherein the obtained baseband signals are input and encoded, and the obtained signals having the second data format are combined to form the second digital data. Data converter. 13. Inputting first digital data having a first data format to be transmitted, decoding the first digital data into a baseband signal, and converting the baseband signal into the first data format Encoding a second digital data having a second data format different from the first digital data, and outputting the second digital data. 14. The data transmission / reception method according to claim 13, wherein the input of said first digital data and the output of said second digital data are performed by a single input / output means. 15. The first digital data is received by a first input / output means, and the transmission of the second digital data is performed by a second transmission means different from the first input / output means. 14. The data transmission / reception method according to claim 13, wherein the method is performed. 16. The data transmission / reception method according to claim 13, wherein said first digital data is inputted in real time by synchronous communication, and said second digital data is outputted in real time by synchronous communication. . 17. The data transmission / reception method according to claim 13, wherein said first digital data is input by asynchronous communication, and said second digital data is output by asynchronous communication. 18. The second input / output means delays the first digital data input from the first input / output means for a predetermined time and outputs the second digital data input from the encoding means. 16. The data transmission / reception method according to claim 15, wherein the first digital data and the second digital data are transmitted in synchronization. 19. The predetermined time is a time required for decoding the first digital data into a baseband signal, and the encoding means converts the baseband signal to the second band.
19. The data transmission / reception method according to claim 18, wherein the sum is a sum of a time required for encoding the digital data and the digital data. 20. The second input / output means outputs desired digital data from a plurality of first digital data having the first data format inputted to the plurality of first input / output means. The data transmission / reception method according to claim 15, wherein the data is selected and input. 21. The second input / output means, for a selected input / output means which is a first input / output means for inputting digital data selected from a plurality of the first input / output means, A request for transmission of the selected digital data is made, and the first input / output means of the plurality of first input / output means other than the selected input / output means is sent to the first input / output means.
21. The data transmission / reception method according to claim 20, wherein a transmission stop request of the first digital data having the data format is made. 22. Among a plurality of digital data inputted from said input / output means, said one digital data is decoded by a first decoding means and the other digital data is decoded by a second decoding means. 14. The data transmission / reception method according to claim 13, wherein: 23. A baseband signal obtained by decoding said one digital data and a baseband signal obtained by decoding said other digital data, respectively, and said second data format obtained. 23. The data transmission / reception method according to claim 22, wherein the respective signals having the following are combined to form the second digital data.