JP2001044767A - Double balanced integrated mixer circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a double balanced integrated mixer circuit where as odd number order harmonic distortion characteristic of an IF signal output is improved and leakage of an LO signal is suppressed. SOLUTION: The double balanced mixer integrated circuit consists of an RF signal amplifier circuit 1 that receives an RF signal S1 and of a multiplier circuit 2 that receives an LO signal S2 and multiplies the LOS signal S2 by an amplified output of the RF signal amplifier circuit 1 to provide an output of an IF signal. The RF signal amplifier circuit 1 consists of MOS FETs Q1, Q2 and the multiplier circuit 2 consists of bipolar transistors(TRs) Q3-Q6. Since the output current with respect to the input voltage, that is, a transfer function of the MOS FETs being components of the RF signal amplifier circuit 1 changes in terms of the 2nd power with respect to the input voltage, the integrated circuit provides an IF signal with less odd number order harmonic distortion component in comparison with that of a amplifier circuit consisting of bipolar TFs where its output current with respect to its input voltage, that is, the transfer function, changes in terms of the x-th power of e. Since a larger mutual conductance can be obtained from the bipolar TRs being the components of the multiplier circuit 2 in comparison with MOS FETs, a small voltage of the LOS signal being the input signal to the multiplier circuit 2 is enough, resulting in decreasing a leakage voltage of the LO signal to the RF signal input and the IF signal output.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a double balanced mixer (DBM) integrated circuit, and more particularly to a DBM integrated circuit having improved distortion characteristics and local oscillation signal leakage of an IF output signal.

[0002]

2. Description of the Related Art Conventionally, in a DBM circuit using an analog multiplier, all active elements are constituted by bipolar transistors. For example, FIG. 3 shows an example, in which bipolar transistors Q11 and Q12 constitute an RF signal amplification circuit, and bipolar transistors Q13 to Q16 constitute a multiplication circuit. For example, an RF (high frequency) signal is input to the input of the amplifier circuit as the signal S1, and the signal S1 is input to the input of the multiplication circuit.
For example, an LO (local oscillation) signal is input as 2, and a frequency-converted IF (intermediate frequency) signal is output from the output of the multiplication circuit. R11 is a bias resistor, and R12 and R13 are load resistors. However, this DBM circuit has a problem that the third-order, fifth-order, and other odd-order harmonic distortion characteristics of the IF output signal that is the output signal are poor. That is, the transfer function of the bipolar transistor has a characteristic that the output current Iob changes with the ex voltage (ex potential) with respect to the input voltage Vib. Iob = Vib raised to the power of ex. Therefore, since the input circuit is formed of the bipolar transistor, the odd-order harmonic distortion characteristics such as the third and fifth harmonics of the IF output signal mixed with the LO signal are deteriorated.

[0003]

In order to solve such a problem, an MO having essentially superior third harmonic distortion is required.
It is conceivable to apply an S-type FET or a gallium arsenide MES-type FET to an active element.However, a MOS-type FET requires a large LO signal voltage because the transconductance is smaller than that of a bipolar transistor. There is a problem that the leakage voltage of the voltage to the RF input terminal and the IF output terminal increases, and the characteristics of the DBM circuit are lost. Further, when a gallium arsenide MES type FET having a larger mutual conductance than a MOS type FET is applied to an active element, there is a problem in that it is more expensive than that formed by a silicon active element.

An object of the present invention is to provide a DBM integrated circuit in which odd-order harmonic distortion characteristics are improved and LO signal leakage is suppressed.

[0005]

According to the present invention, there is provided a multiplication circuit which multiplies an RF signal amplifying circuit to which an RF signal is inputted and an amplified output of the RF signal amplifying circuit to which an LO signal is inputted and outputs an IF signal. And an RF signal amplifying circuit is constituted by a MOS-type FET, and the multiplying circuit is constituted by a bipolar transistor. Further, according to the present invention, the MOS type FET constituting the RF signal amplifier circuit and the bipolar transistor constituting the multiplication circuit are formed integrally on the same semiconductor substrate.

In the present invention, the transfer function of the MOS type FET constituting the RF signal amplifying circuit varies with the square of the output current with respect to the input voltage. Compared to an amplifier circuit composed of bipolar transistors, an RF amplified signal having less third-order, fifth-order, and other odd-order harmonic distortion components is obtained, and odd-order harmonic distortion components in the IF signal output can be suppressed. The bipolar transistor constituting the multiplication circuit is a MOS type F
Since a large transconductance is obtained as compared with ET, the signal voltage of the LO signal, which is an input signal of the multiplication circuit, can be reduced, and the leakage voltage of the LO signal to the RF signal input and the IF signal output can be reduced. Becomes possible.

Here, as a mixer circuit, for example, Japanese Patent Application Laid-Open No. 5-129636 discloses a circuit configuration in which a pair of bipolar transistors Q1 and Q2 are connected to FETs M9 and M10 as driving current sources in FIG. Thus, a technique in which a multiplication circuit that multiplies the LO signal and the RF signal is described, but the FETs M9, M10
Constitutes a current mirror circuit, and does not constitute an amplifier circuit for the input signal S1 as in the present invention.

[0008]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of an embodiment of a DBM integrated circuit according to the present invention, which comprises an amplification circuit 1 and a multiplication circuit 2. In the amplifier circuit 1, Q1 and Q2 are first and second MOS FETs, whose sources are commonly connected to a bias resistor R1 for constant current, an RF signal is complementarily input to each gate as a signal S1, and each drain is Multiplication circuit 2
And is configured as an RF signal amplification circuit. In the multiplication circuit 2, Q3 to Q6 are first to fourth bipolar transistors, and the emitters of the first and second bipolar transistors Q3 and Q4 are commonly connected to the drain of the first MOSFET Q1. The emitters of the third and fourth bipolar transistors Q5 and Q6 are commonly connected to the drain of the second MOSFET Q2. Further, the first and fourth bipolar transistors Q
The bases of the third and third transistors Q6 and Q6 are commonly connected, the bases of the second and third bipolar transistors Q4 and Q5 are commonly connected, and the LO signal is complementarily input as a signal S2 to each base common connection terminal. Further, the collectors of the first and third bipolar transistors Q3 and Q5 are commonly connected, connected to a power supply VCC via a load resistor R2, and the collectors of the second and fourth bipolar transistors Q4 and Q6 are commonly connected. Connected to the power supply VCC via a load resistor R3,
In addition, the IF signals are complementarily output from the respective drain common connection terminals.

Here, each element of the amplification circuit 1 and the multiplication circuit 2 constituting the DBM integrated circuit, that is, the MOS
Type FETs Q1, Q2, bipolar transistors Q3-Q
6 and each element of the resistors R1 to R3 are formed on one semiconductor substrate. FIG. 2 is a schematic cross-sectional view of FIG.
Type silicon substrate 11 is divided into at least an FET region and a bipolar transistor region by an element isolation oxide film 12,
An n-type well 13 is formed in each region. In the MOS region, a gate oxide film 14 and a gate electrode 15 are formed, and a source / drain region 16 is formed.
Q1 and Q2 are configured. In the bipolar region, n
^{A first} buried layer 17, an n ⁺ collector contact layer 18, a p base layer 19, and an n ⁺ emitter layer 20 are formed to constitute the first to fourth bipolar transistors Q3 to Q6 formed of npn transistors. Further, although not shown in FIG. 2, the resistors R1 to R3 are composed of an impurity diffusion layer provided on the epitaxial layer or a polycrystalline silicon film provided on the element isolation oxide film. in this way,
The DBM integrated circuit is constituted by a semiconductor integrated circuit having a Bi-MOS structure.

In the above-structured DBM integrated circuit, the S1 signal, that is, the RF signal is the first and second MOS FETs.
Input to the gates of Q1 and Q2,
The signal is amplified by the amplifier circuit 1 composed of Q1 and Q2.
The RF signal amplified by the amplifier circuit 1 is supplied as a source current to each of a pair of first and second bipolar transistors Q3 and Q4 and a pair of third and fourth bipolar transistors Q5 and Q6. S2 signal inputted to each gate of Q6
That is, the multiplication is performed with the LO signal, and the drain of each of the bipolar transistors Q3 to Q6 outputs R as an IF output signal.
The sum and difference between the F frequency and the local oscillation frequency are output.

In this operation, the first and second MOS FETs Q constituting the amplifying circuit 1 to which the RF signal is inputted.
In the transfer function of 1, Q2, the output current Iom changes by the square of the input voltage Vim. Vim = Iom squared. Therefore, when compared with an amplifier circuit having a transfer function of an ex-power bipolar transistor as described above,
An RF amplified signal having a small third-order or fifth-order odd-order harmonic distortion component is obtained, and as a result, it is possible to suppress the odd-order harmonic distortion component in the IF signal output that is the output of the multiplication circuit.

The first to fourth bipolar transistors Q3 to Q6 constituting the multiplying circuit 2 in which the RF signal and the LO signal are multiplied each have a large current change with a small input amplitude voltage, that is, a large current change, as compared with the MOS type FET. Since a large transconductance gm is obtained, the signal voltage of the S2 signal, that is, the LO signal, which is the input signal of the multiplication circuit, can be reduced, thereby reducing the leakage voltage of the LO signal to the RF signal input and the IF signal output. It is possible to do.

Therefore, in the DBM integrated circuit according to the above-described embodiment, while the odd-order harmonic distortion component in the IF signal output is suppressed, the LO signal can be prevented from leaking into the IF signal output from the RF signal. It is configured as a DBM integrated circuit. In addition, since each element of the MOS type FET and the bipolar transistor constituting the DBM integrated circuit and elements such as a resistor are integrally formed on one silicon substrate, a highly integrated DBM integrated circuit is formed. become.

The above-described embodiment shows an example of the present invention.
It is also possible to use an S-type FET, and it is also possible to use a PNP-type transistor as a bipolar transistor. Needless to say, the load resistance and the bias resistance can be configured by transistor elements.

[0015]

As described above, according to the present invention, since the RF signal amplifying circuit is constituted by the MOS type FET and the multiplying circuit is constituted by the bipolar transistor, the MOS type FET is constituted.
The third-order and fifth-order odd-order harmonic distortion components can be suppressed by utilizing the fact that the transfer function of the output current changes with the square of the input voltage, while utilizing the large transconductance of the bipolar transistor. Thus, the signal voltage of the LO signal can be reduced, the leakage voltage of the LO signal to the RF signal input and the IF signal output can be reduced, and a DBM integrated circuit having excellent mixing characteristics can be configured. Also,
By forming the MOS type FET and the bipolar transistor constituting each circuit on the same semiconductor substrate, it is possible to configure a highly integrated small DBM integrated circuit.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a DBM integrated circuit according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view schematically showing a main part of a configuration example in which the DBM integrated circuit of FIG. 1 is integrated on one silicon substrate.

FIG. 3 shows a conventional D-type bipolar transistor.
It is a circuit diagram of an example of a BM circuit.

[Explanation of symbols]

Q1 First MOS type FET Q2 Second MOS type FET Q3 First bipolar transistor Q4 Second bipolar transistor Q5 Third bipolar transistor Q6 Fourth bipolar transistor R1 Bias resistance R2, R3 Load resistance 1 RF signal amplification Circuit 2 Multiplying circuit 11 p-type silicon substrate 12 element isolation oxide film 13 n-type well 15 gate electrode 16 source / drain region 17 n ⁺ buried layer 18 n ⁺ collector contact layer 19 p-type base layer 20 n ⁺ emitter layer

Claims (4)

[Claims] 1. An RF signal amplification circuit to which an RF (high frequency) signal is input is multiplied by an amplified output of the RF signal amplification circuit to which a LO (local oscillation) signal is input to convert an IF (intermediate frequency) signal. A double-balanced mixer integrated circuit having a multiplying circuit for outputting the signal, wherein the RF signal amplifying circuit is constituted by a MOS FET, and the multiplying circuit is constituted by a bipolar transistor. 2. The RF signal amplifying circuit comprises a pair of first and second MOS-type FETs each having a source commonly connected to a bias resistor for constant current, and a complementary input of an RF signal to each gate. 2. The double balanced mixer integrated circuit according to claim 1, wherein each drain of the first and second MOS type FETs is connected to a drive current source of the multiplier circuit. 3. The multiplying circuit includes first to fourth four bipolar transistors, and the emitters of the first and second bipolar transistors are connected to the drain of one MOS-type FET of the RF signal amplifying circuit. The third and fourth bipolar transistors are commonly connected, and the emitters of the third and fourth bipolar transistors are the other MOS type FE of the RF signal amplifier circuit.
The bases of the first and fourth bipolar transistors are connected in common, and the bases of the second and third bipolar transistors are connected in common. Complementary input, the collectors of the first and third bipolar transistors are connected in common and connected to a power supply via a first load, and the collectors of the second and fourth bipolar transistors are connected in common and connected to a second power supply. 3. The double balanced mixer integrated circuit according to claim 1, wherein the power supply is connected to the power supply via the load, and IF signals are output complementarily from respective drain common connection terminals. 4. 4. The first and second MOSFETs constituting the RF signal amplifier circuit and the first to fourth bipolar transistors constituting the multiplier circuit are integrally formed on the same semiconductor substrate. 4. The double-balanced mixer integrated circuit according to claim 1, wherein: