JP2001044430A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make drift regions equipotential, that is bring them into uniform electric fields and attain a high breakdown voltage by forming between a body region and a drain region through lamination thin p-type and n-type drift regions which are completely depleted, when a high voltage close to a rated voltage is applied. SOLUTION: In a SiC field-effect transistor, when a high voltage is applied, so that the potential of the drain electrode 8 is higher than the potential of the source electrode 7, a junction constituted of drift regions 2 and 3 is reverse biased. As a result, a depletion layer extends in both drift regions 2 and 3, and almost the entire drift regions 2 and 3 are depleted completely. The potential distribution in the drift regions 2 and 3 becomes equipotential as it goes from a junction, composed of the drift region 3 and the drain region 6 toward a junction composed of the drift region 2 and the body region 4. In other words, the electric fields become almost uniform throughout the drift regions 2 and 3, and thus the breakdown voltage of the SiC field-effect transistor can be enhanced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a high withstand voltage power semiconductor device.

[0002]

2. Description of the Related Art A wide gap semiconductor material typified by silicon carbide (hereinafter referred to as SiC) is silicon (hereinafter referred to as SiC).
), A higher breakdown voltage can be achieved with the same impurity concentration as in the case of Si. Furthermore, there is an advantage that a high withstand voltage can be maintained while maintaining a low loss, the device can be operated even at a high temperature of 250 ° C. or higher, and heat conduction is good. A power MOSFET using the SiC and having a structure as shown in FIG. 15 is disclosed in Proceedings of the 10th International Symposiu published in 1998.
mon Power Semiconductor Devices & ICs, pp. 119-122. This power MOSFET is called a trench gate type MOSFET, and has an n-type MOSFET.
An n-type drift layer 102 is formed on an iC semiconductor substrate 101 by an epitaxial method. A p-type body region 103 is formed on n-type drift layer 102, and an n-type source region 104 is formed in a predetermined region of the p-type body layer. A recess 110 reaching the n-type drift region 102 from the n-type source region 104 and the p-type body region 103 is formed, and a gate electrode 106 is formed in the recess 110 with a gate insulating film 105 interposed therebetween. On the n-type source region 104, a source electrode 107 is formed. N-type Si
A drain electrode 108 is formed on the lower surface of the C semiconductor substrate.

A channel for flowing carriers between a source S and a drain D is formed as follows. That is, a voltage is applied to the gate electrode 106 to apply an electric field to the gate insulating film 105 sandwiched between the gate electrode 106 and the p-type body region 103 on the side wall of the recess 110. Thus, the conductivity type near the surface of p-type body region 103 in contact with gate insulating film 105 is inverted to n-type, and a channel is formed. With this structure, performance exceeding the theoretical limit of the Si power MOSFET, that is, a low on-resistance of 311 mΩcm ² per unit area at a withstand voltage of 1400 V can be obtained.

In recent years, the development and commercialization of a high-withstand-voltage power IC in which a control circuit and a protection circuit are combined with a high-withstand-voltage power output element have been promoted and contributed to the miniaturization and intelligentization of high-withstand-voltage semiconductor devices. . As a type of an output element of a high breakdown voltage power IC, a bipolar semiconductor device typified by an IGBT or a thyristor has been attracting attention from the viewpoint of low loss. The bipolar semiconductor device has the advantage that the internal resistance of the semiconductor device can be greatly reduced and the loss can be significantly reduced as compared with a monopolar semiconductor device typified by MOSFET and SIT due to the effect of conductivity modulation. There are a vertical structure and a horizontal structure as a structure of the high withstand voltage power output element, but a horizontal structure is mainly used in view of easy combination with a control circuit or the like and integration. FIG. 16 shows a typical horizontal structure IGBT made of Si.
Proceedings of the International Academic Conference held in 2006
8th International Symposium on Power Semiconduct
or Devices & ICs, page 101 to page 104.

In the IGBT, an SiO ₂ insulating film 213 is formed on a Si substrate 201, and then an n-type drift region 202 is laminated. Stacked drift region 20
2, a p-type body region 204 is formed at the right end, and an n-type emitter region 205 and a p-type contact region 214 are formed therein.
Are formed. An emitter electrode 218 is formed in the emitter region 205, and a base electrode 220 is formed in the contact region 214. Further, a gate electrode 211 is provided on the p-type body region 204 via the gate oxide film 210. At the left end of the drift region 202, an n-type buffer region 206, a p-type collector region 207, and an anode electrode 219 are sequentially provided.

The operation when the IGBT is turned off is as follows. The potential of the anode electrode 219 is
When a high voltage is applied so as to be higher than the potential of 18, the junction formed by the p-type body region 204 and the n-type drift region 202 is reverse-biased, and the depletion layer mainly spreads in the n-type drift region 202. The electric field in the depletion layer becomes maximum near the junction and gradually decreases toward the n-type buffer region 206. When the applied voltage is further increased, the depletion layer further expands toward the n-type buffer region 206, and the maximum electric field near the junction increases. The applied voltage at which the maximum electric field reaches about 0.3 MV / cm, which is the dielectric breakdown electric field of SiC, is the breakdown voltage of this IGBT.

On the other hand, the operation at the time of turning on is as follows.
In a state where a voltage is applied so that the potential of the anode electrode 219 becomes higher than the potential of the emitter electrode 218, the gate electrode 2
When a high voltage equal to or higher than the threshold voltage is applied to 11, electrons are collected on the surface of p-type body region 204 under gate electrode 211, and an inversion layer is formed. As a result, electrons flow from the n-type emitter region 205 through the inversion layer. Some of the electrons reach the n-type buffer region 206 through the n-type drift region 202 and promote the injection of holes from the p-type collector region 207. The injected holes are in the n-type drift region 2
02 and reaches the p-type body region 204 and flows out of the emitter electrode 218. At this time, the n-type drift region 20
Both electrons and holes are present in 2 and conductivity modulation occurs. Thereby, the resistance of the drift region can be significantly reduced. As a result, a semiconductor device having a low on-resistance, that is, a low loss can be realized despite having a higher breakdown voltage than the MOSFET. The breakdown voltage of this conventional example is 340 V, and the current capacity is 2 A. The ON voltage at a current density of 200 A / cm ² is 2.0 V, and the ON resistance in a voltage range higher than the built-in voltage is 46.6 mΩcm ^2.
It is.

[0008]

In order to use a semiconductor device for a large-capacity inverter for industrial use, an inverter for railway use such as a bullet train or a train, or a power conversion device for an electric power business, a higher withstand voltage and a lower loss are required. Things are needed. However, in order to increase the breakdown voltage with a trench gate type MOSFET as shown in FIG. 15, it is necessary to reduce the impurity concentration in the drain region to expand the depletion layer and reduce the electric field. As a result, the resistance of the drain region is increased, the on-resistance when the semiconductor device is turned on and a current flows is increased, and it is difficult to reduce the loss. Further, the electric field tends to concentrate on the bottom of the concave portion 110, and it is difficult to increase the breakdown voltage. In a semiconductor device using SiC or Si, the on-resistance is lowered by increasing the impurity concentration of the drift layer 102 because the breakdown electric field is high. In this case, the gate insulating film 105 at the bottom of the recess 110 is used.
The electric field of the light is high, and it is difficult to increase the withstand voltage.

The Si-IGBT shown in FIG. 16 has a low breakdown voltage and is insufficient in withstand voltage to be used for a high-voltage inverter for industrial use, an inverter for electric railways such as a Shinkansen train, a high-voltage power converter for a power business, and the like. Yes, even higher withstand voltage is required. In order to increase the breakdown voltage with the structure of FIG. 18, it is necessary to lower the impurity concentration of the drift region 202 to expand the depletion layer and reduce the electric field. However, in this case, the resistance of the drift region 202 increases, and the on-resistance when the semiconductor device is turned on and a current flows is increased, making it difficult to reduce the loss. For example, when the breakdown voltage is 1000 V or more, the on-resistance in a voltage range higher than the built-in voltage is 400 mΩcm ² or more, and when the breakdown voltage is 2000 V or more, it is 2500 mΩcm ² or more. SUMMARY OF THE INVENTION An object of the present invention is to provide a high-breakdown-voltage semiconductor device that has a high withstand voltage and a high reliability while reducing the electric field of the drain region and reducing the on-resistance without reducing the impurity concentration of the drain region. I have.

[0010]

A wide-gap semiconductor device according to the present invention comprises a first drift region of a first conductivity type formed on a high-resistance wide-gap semiconductor substrate; A second drift region of the second conductivity type having the same thickness and the same impurity concentration as the first drift region, and the first drift region formed to be in contact with the first and second drift regions. A buried region of the conductivity type, a first electrode formed in the buried region, a first electrode formed at a predetermined distance from the buried region and in contact with at least one of the first and second drift regions. A second conductivity type body region, a first conductivity type region formed in a part of the body region, a second electrode provided in the body region and the first conductivity type region, and the first conductivity type body region. Drift region and the body A control electrode formed in a region, wherein the thickness of the first and second drift regions is reduced by applying a voltage lower than a rated voltage between the first electrode and the second electrode. The second drift region is selected to be a substantially complete depletion layer.

A wide gap semiconductor device according to another aspect of the present invention is a first drift region of a first conductivity type formed on a high resistance wide gap semiconductor substrate, and formed on the first drift region. The second drift region of the second conductivity type having the same thickness and the same impurity concentration as the first drift region, the substrate, and the first and second drift regions.
A first conductivity type buried region formed so as to be in contact with the drift region, a first electrode formed in the buried region, and the first and second drift regions separated by a predetermined distance from the buried region. A second conductivity type body region formed to be in contact with at least one of the regions, a first conductivity type region formed in a part of the body region, the body region and the first region;
A second electrode provided in a region of the conductivity type, and a control electrode formed on the substrate, the first drift region and the body region via an insulating film, and a thickness of the first and second drift regions. Is selected such that when a voltage lower than the rated voltage is applied between the first electrode and the second electrode, the first and second drift regions become substantially complete depletion layers. And

In the wide-gap semiconductor devices of the above two inventions, when a voltage is applied so that the first electrode has a high potential and the second electrode has a low potential, the first conductive type region and the second conductive type are applied. Since the junction formed in the body region of the mold is forward-biased, the low potential region extends to the drift region of the second conductivity type. Further, the high potential region extends to the first conductivity type drift region via the buried region. As a result, the first junction formed by the first and second drift regions is reverse-biased, and the depletion layer extends to both the first and second drift regions. A second region composed of the buried region 6 and the second conductivity type drift region 3
Is also reverse-biased at the same time, and the depletion layer extends into the region of the second conductivity type. Further, the third junction formed by the body region of the second conductivity type and the drift region of the first conductivity type is simultaneously reverse-biased, and the depletion layer expands into the drift region of the first conductivity type. As described above, the depletion layers spread from both sides in both drift regions, and the first conductivity type drift region and the second conductivity type drift region are almost completely depleted before the second and third junctions break down. To make it thinner. At least before the applied voltage reaches the rated voltage of the semiconductor device, the drift region is completely depleted. As a result, at least when a voltage near the rated voltage is applied, the drift region 2
The distribution of the potential up to the junction formed by the body region 4 and the body region 4 becomes a substantially equipotential distribution, and the electric field becomes substantially uniform over both the drift regions. The applied voltage can be increased until the electric field reaches the breakdown electric field Ec of the wide gap semiconductor, so that a high breakdown voltage can be achieved.

Further, in the above configuration, the breakdown voltage is determined by the maximum breakdown field and the length of both drift regions, and does not depend on the thickness of both drift regions. As the thickness of both drift regions is reduced, complete depletion can be achieved even if the impurity concentration is increased, and a high breakdown voltage can be obtained. Generally, there is a relationship between the thickness of the depletion layer and the impurity concentration N that the thickness is substantially proportional to 1 / N to the 0.5 power. Therefore, when the thickness of both drift regions is reduced and the thickness of the depletion layer is set in this range, the effect of increasing the impurity concentration is remarkable. That is, the effect of reducing the on-resistance is remarkable. In the case of the conventional configuration, if the thickness of the drift region is reduced and the impurity concentration is increased, the on-resistance can be reduced, but the withstand voltage decreases non-linearly. Therefore, the resistance RonS per unit area is proportional to the 2.5th power of the withstand voltage. RonS increases significantly as the breakdown voltage increases. In the structure of the present invention, the breakdown voltage is proportional to the length of the drift region, but does not depend on the thickness. Therefore, only the effect of reducing the on-resistance can be enjoyed by reducing the impurity concentration without reducing the thickness and without deteriorating the breakdown voltage, and RonS has a relationship proportional to the first power of the breakdown voltage. Therefore, in the structure of the present invention, when the thickness of the drift layer is reduced to the limit, there is a great effect that a semiconductor device with a withstand voltage of 1000 V or more can reduce on-resistance by two digits or more in principle compared to the conventional structure. The limit of the thickness of the drift layer is that even if the concentration is increased, the built-in potential of the first junction exists, so that a depletion layer is formed due to the built-in potential. However, this is because the effect of reducing the on-resistance is lost. Further, when the same voltage is applied as compared with the conventional structure, the structure of the present invention can improve the reliability because the local concentration of the electric field is small and the maximum electric field is low.

A wide gap semiconductor device according to another aspect of the present invention comprises a plurality of sets of a first conductive type first drift region and a second conductive type formed on a high resistance wide gap semiconductor substrate. A first conductivity type formed on an inner wall surface of a first trench reaching the substrate through a set of the second drift region and the plurality of sets of the first and second drift regions. Embedded region, a first electrode formed in the embedded region, a body region of a second conductivity type formed in an uppermost drift region of the plurality of sets of first and second drift regions, and the body A first conductivity type region formed in a part of the region, the plurality of sets of the first and second drift regions, the body region, and the first region provided at positions separated by a predetermined distance from the first trench; A first region reaching the substrate through the region of the first conductivity type; Has an inner wall surface formed with an insulating film of the trench, the second control electrode and the provided via an insulating film on the inner wall surface of the trench, and a second electrode provided on the region and the body region.

A wide gap semiconductor device according to another aspect of the present invention is a second drift type first drift region formed on a high resistance wide gap semiconductor substrate and formed on the first drift region. The first drift region is formed to be in contact with the second drift region of the first conductivity type having substantially the same thickness and the same impurity concentration as the first drift region, the substrate, and the first and second drift regions. Buried region of the first conductivity type, the first electrode formed in the buried region, and a predetermined distance from the buried region so as to be in contact with the substrate and the first and second drift regions. A second conductive type body region formed, a first conductive type region formed in part of the body region, a second electrode provided in the region and the body region, and an insulating film interposed between the body region and the body region. Control electrode When the thickness of the first and second drift regions is set to a value lower than the rated voltage between the first and second electrodes, the first and second drift regions are substantially It is characterized in that it is selected so as to have a complete depletion layer.

A wide gap semiconductor device according to another aspect of the present invention is a first drift region of a first conductivity type formed on a high resistance wide gap semiconductor substrate, and formed on the first drift region. A second drift region of the second conductivity type having substantially the same thickness and the same impurity concentration as the first drift region, and a first drift region formed in contact with the first and second drift regions. Buried area of conductivity type,
A first electrode formed in the buried region, a second conductive layer formed in the first drift region so as to be separated from the buried region by a predetermined distance and to be in contact with the first and second drift regions; Body region, a first conductivity type region formed in a portion of the body region, a second electrode provided in the region, and a second body region of the first drift region and the region A control electrode provided with an insulating film interposed therebetween, the thickness of the first and second drift regions, when a voltage lower than the rated voltage is applied between the first electrode and the second electrode, The first and second drift regions are selected to be substantially complete depletion layers.

A wide-gap semiconductor device according to another aspect of the present invention uses a low-resistance second-type material formed on a wide-gap semiconductor substrate using a high-resistance first-type material. A first drift region of a first conductivity type, a second type of material formed on the first drift region and having substantially the same thickness and the same impurity concentration as the first drift region is used. A second drift region of the second conductivity type, a buried region of the first conductivity type formed to be in contact with the first and second drift regions, a first electrode formed in the buried region, A second conductivity type body region formed at a predetermined distance from the buried region and in contact with the first and second drift regions; a first conductivity type body region formed in a part of the body region; Region, a second electrode provided in the region, and A control electrode provided through an insulating film on the inner wall surface of the trench reaching the first drift region through the first region, and the thickness of the first and second drift regions is controlled by the first drift region. When a voltage lower than the rated voltage is applied between the electrode and the second electrode, the first and second drift regions are selected so as to become a substantially complete depletion layer.

In the semiconductor device according to the present invention, a first drift region of a first conductivity type formed on a substrate of a wide gap semiconductor having a high resistance, the first drift region formed on the first drift region. A second drift region of the second conductivity type having the same thickness and the same impurity concentration as the drift region, a buried region of the first conductivity type formed in contact with the first and second drift regions, A first portion formed in the buried region;
A second conductivity type body region formed so as to be separated from the buried region by a predetermined distance and to be in contact with at least one of the first and second drift regions, and formed in a part of the body region A first conductive type region, a second electrode provided in the body region and the first conductive type region, and a control electrode formed in the first drift region and the body region. And when the thickness of the second drift region is lower than the rated voltage between the first electrode and the second electrode, the first and second drift regions are substantially completely depleted. It is characterized by having been selected so that

According to another aspect of the present invention, there is provided a semiconductor device having a first conductivity type first drift region formed on a high resistance wide gap semiconductor substrate, wherein the first drift region is formed on the first drift region. A first conductive type second drift region having the same thickness and the same impurity concentration as the first drift region, the substrate, and the first drift region formed so as to be in contact with the first and second drift regions. A buried region of the conductivity type, a first electrode formed in the buried region, a first electrode formed at a predetermined distance from the buried region and in contact with at least one of the first and second drift regions. A second conductive type body region, a first conductive type region formed in a part of the body region, a second electrode provided in the body region and the first conductive type region, 1 drift region and body region A control electrode formed through an insulating film, wherein the thickness of the first and second drift regions is reduced by applying a voltage lower than a rated voltage between the first electrode and the second electrode. The first and second drift regions are selected to be substantially complete depletion layers.

In the above-described semiconductor devices of the two inventions, when a voltage is applied so that the first electrode has a high potential and the second electrode has a low potential, the region of the first conductivity type and the second conductivity type are applied. Since the junction formed in the body region is forward biased, the low potential region extends to the second conductivity type drift region. Further, the high potential region extends to the first conductivity type drift region via the buried region. As a result, the first junction formed by the first and second drift regions is reverse-biased, and the depletion layer extends to both the first and second drift regions. The second junction formed by the buried region 6 and the drift region 3 of the second conductivity type is also reverse biased at the same time, and the depletion layer extends into the region of the second conductivity type. Further, the third junction formed by the body region of the second conductivity type and the drift region of the first conductivity type is simultaneously reverse-biased, and the depletion layer expands into the drift region of the first conductivity type. As described above, the depletion layers spread from both sides in both drift regions, and the first conductivity type drift region and the second conductivity type drift region are almost completely depleted before the second and third junctions break down. To make it thinner. At least before the applied voltage reaches the rated voltage of the semiconductor device, the drift region is completely depleted. As a result, when at least a voltage near the rated voltage is applied, the potential distribution from the junction formed by the drift region and the buried region 6 to the junction formed by the drift region 2 and the body region 4 is substantially equal. The distribution becomes equipotential and the electric field becomes substantially uniform over the entire area of both drift regions. This electric field is the dielectric breakdown electric field E of the wide gap semiconductor.
Since the applied voltage can be increased until the voltage reaches c, the breakdown voltage can be increased.

Further, in the above configuration, the breakdown voltage is determined by the maximum breakdown field and the length of both drift regions, and does not depend on the thickness of both drift regions. As the thickness of both drift regions is reduced, complete depletion can be achieved even if the impurity concentration is increased, and a high breakdown voltage can be obtained. Generally, there is a relationship between the thickness of the depletion layer and the impurity concentration N that the thickness is substantially proportional to 1 / N to the 0.5 power. Therefore, when the thickness of both drift regions is reduced and the thickness of the depletion layer is set in this range, the effect of increasing the impurity concentration is remarkable. That is, the effect of reducing the on-resistance is remarkable. In the case of the conventional configuration, if the thickness of the drift region is reduced and the impurity concentration is increased, the on-resistance can be reduced, but the withstand voltage decreases non-linearly. Therefore, the resistance RonS per unit area is proportional to the 2.5th power of the withstand voltage. RonS increases significantly as the breakdown voltage increases. In the structure of the present invention, the breakdown voltage is proportional to the length of the drift region, but does not depend on the thickness. Therefore, only the effect of reducing the on-resistance can be enjoyed by reducing the impurity concentration without reducing the thickness and without deteriorating the breakdown voltage, and RonS has a relationship proportional to the first power of the breakdown voltage. Therefore, in the structure of the present invention, when the thickness of the drift layer is reduced to the limit, there is a great effect that a semiconductor device with a withstand voltage of 1000 V or more can reduce on-resistance by two digits or more in principle compared to the conventional structure. The limit of the thickness of the drift layer is that even if the concentration is increased, the built-in potential of the first junction exists, so that a depletion layer is formed due to the built-in potential. However, this is because the effect of reducing the on-resistance is lost. Further, when the same voltage is applied as compared with the conventional structure, the structure of the present invention can improve the reliability because the local concentration of the electric field is small and the maximum electric field is low.

A semiconductor device according to another aspect of the present invention includes a plurality of sets of a first drift region of a first conductivity type and a second conductivity type formed on a substrate of a high resistance wide gap semiconductor. A set with a second drift region, the plurality of sets,
A buried region of a first conductivity type formed on an inner wall surface of a first trench reaching the substrate through a pair of second drift regions and a first electrode formed in the buried region; A second conductivity type body region formed in an uppermost drift region of the set of first and second drift regions; a first conductivity type region formed in a part of the body region; A second trench that is provided at a predetermined distance from the trench and that reaches the substrate through the plurality of sets of the first and second drift regions, the body region, and the first conductivity type region; An insulating film formed on an inner wall surface, a control electrode provided on the inner wall surface of the second trench via the insulating film, and a second electrode provided on the region and the body region are provided.

According to another aspect of the present invention, there is provided a semiconductor device having a first drift region of a second conductivity type formed on a substrate made of a high-resistance wide gap semiconductor, and formed on the first drift region. A first conductive type second drift region having substantially the same thickness and the same impurity concentration as the first drift region, the substrate, and a second conductive region formed in contact with the first and second drift regions. Embedded region of the conductivity type of 1,
A first electrode formed in the buried region, a second conductivity type body region formed so as to be separated from the buried region by a predetermined distance and to be in contact with the substrate and the first and second drift regions; A first conductivity type region formed in a part of the body region, a second electrode provided in the region and the body region, and a control electrode provided in the body region via an insulating film; And the thickness of the second drift region
When a voltage lower than the rated voltage is applied between the first electrode and the second electrode, the first and second drift regions are selected so as to be substantially complete depletion layers. .

In a semiconductor device according to another aspect of the present invention, a first drift region of a first conductivity type formed on a substrate of a high-resistance wide gap semiconductor, and formed on the first drift region. A second drift region of a second conductivity type having substantially the same thickness and the same impurity concentration as the first drift region, a first conductivity type formed to be in contact with the first and second drift regions; Buried region, a first electrode formed in the buried region, a predetermined distance from the buried region, and formed in the first drift region so as to be in contact with the first and second drift regions. Body region of the second conductivity type, a region of the first conductivity type formed in a part of the body region, a second electrode provided in the region, and a second body of the first drift region Region and an insulating film on the region The first and second drift regions when a voltage lower than the rated voltage is applied between the first electrode and the second electrode. The region is selected to be a substantially complete depletion layer.

According to another aspect of the present invention, there is provided a semiconductor device formed on a wide-gap semiconductor substrate using a high-resistance first type material and using a low-resistance second type material. A first drift region having the same conductivity type as that of the first drift region and having the same impurity concentration as the first drift region. A second drift region of conductivity type 2;
A first conductivity type buried region formed in contact with the second drift region; a first electrode formed in the buried region; and a predetermined distance from the buried region. A second conductivity type body region formed in contact with the second drift region, a first conductivity type region formed in a part of the body region, a second electrode provided in the region, and the body region And a control electrode provided on the inner wall surface of the trench reaching the first drift region via an insulating film. The thickness of the first and second drift regions is
When a voltage lower than the rated voltage is applied between the first electrode and the second electrode, the first and second drift regions are selected so as to be substantially complete depletion layers. .

According to another aspect of the present invention, there is provided a semiconductor device including a first drift region of a first conductivity type formed on an insulating substrate, and a second conductivity type formed on a portion of the first drift region. The second drift region, the third drift region of the second conductivity type having an impurity concentration equal to or higher than the impurity concentration of the second drift region of the second conductivity type, which is formed in a portion above the first drift region. A drift region, a first region of a first conductivity type having a high impurity concentration formed in the third drift region, and the first drift region formed in contact with the first drift region and the second drift region. A second region of a first conductivity type having a higher impurity concentration than the drift region and the second drift region; and a second region having a high impurity concentration formed in contact with the second region of the first conductivity type. A third region of the conductivity type of A first electrode formed in a first region of the mold, a second electrode formed in a third region of the second conductivity type, and the first drift region, the third drift region, the first A bipolar semiconductor device comprising: a control electrode opposed to a region via an insulating film, wherein the first drift region and the second drift region have substantially the same thickness, and the respective thicknesses are different from each other. When a voltage smaller than the length and close to the rated voltage is applied between the first electrode and the second electrode, the first and second drift regions become substantially depleted layers. 2 is characterized in that the thickness of the drift region is selected.

In the above-described semiconductor device, when a high voltage is applied so that the second electrode has a high potential and the first electrode has a low potential, the first region of the first conductivity type and the second conductivity type are applied. Since a forward voltage is applied to the junction formed by the second region, the drift region of the second conductivity type has a low potential. The first drift region of the first conductivity type has a high potential via the third region of the second conductivity type and the second region of the first conductivity type.
As a result, a reverse voltage is applied to the first junction formed by the first and second drift regions, and the depletion layer expands in both the first and second drift regions. A second junction composed of the second region of the first conductivity type and the second drift region of the second conductivity type is also reverse-biased at the same time, so that the depletion layer is in the second drift region of the second conductivity type. Spreads out. A reverse junction is simultaneously applied to the third junction formed by the third drift region of the second conductivity type and the first drift region of the first conductivity type, and the depletion layer is formed of the first drift region of the first conductivity type. In the drift region.

As described above, since the depletion layer expands in the first and second drift regions in the vertical and horizontal directions,
Before the second and third junctions break down, the first of the first conductivity type
And the second drift region of the second conductivity type are easily and almost completely depleted before the applied voltage reaches the rated voltage of the semiconductor device. As a result, when at least a voltage near the rated voltage is applied, the junction composed of the second drift region and the second region is changed from the junction composed of the first drift region and the third drift region. Is substantially equal potential distribution, and the electric field is substantially uniform over the entire drift region. Since the applied high voltage can be increased until the electric field reaches the dielectric breakdown electric field of the semiconductor material, the withstand voltage can be increased.

In the conventional structure, even if a drift region having a constant impurity concentration is provided, the electric field in the depletion layer increases at a constant gradient as approaching the junction, and reaches a maximum at the junction. When the applied voltage increases and the electric field at this junction reaches the breakdown voltage Ec, breakdown occurs. On the other hand, in the structure of the present invention, the breakdown voltage is the integral value of the electric field in the depletion layer when the electric field reaches the breakdown voltage. Since the electric field has a constant breakdown voltage in the drift region at the time of breakdown, the breakdown voltage can be increased in principle compared to the conventional structure. Further, in the structure of the present invention, the breakdown voltage is determined by the maximum breakdown field and the lengths of the first and second drift regions, and does not depend on the thickness of both drift regions. Even if the impurity concentration is increased, if the thickness of both drift regions is reduced, both drift regions are easily and completely depleted, and a high breakdown voltage can be realized in the same manner as described above. Generally, there is a relationship between the thickness W of the depletion layer and the impurity concentration N that the thickness W is approximately proportional to 1 / N to the 0.5 power. If the thickness of both drift regions is reduced, the impurity concentration can be increased in proportion to the square of the drift region, so that the effect of reducing the on-resistance is remarkable.

In the case of the conventional structure, when the thickness of the drift region is reduced and the impurity concentration is increased, the on-resistance is reduced.
The breakdown voltage also decreases nonlinearly. For this reason, the resistance per unit area is proportional to the withstand voltage to the power of 2.5, and when the withstand voltage increases, the resistance increases significantly. In the structure of the present invention, since the withstand voltage is proportional to the length of the drift region and does not depend on the thickness, the on-resistance can be reduced while maintaining a high withstand voltage by reducing the thickness and the impurity concentration. That is, the resistance has a relationship proportional to the first power of the breakdown voltage.
Therefore, in the structure of the present invention, when the thickness of the drift layer is reduced to the limit, there is a great effect that the on-resistance can be reduced by two digits or more in principle with a semiconductor device having a withstand voltage of 1000 V or more as compared with the conventional structure. Even if the impurity concentration of the drift layer is increased due to the limit of the thickness of the drift layer, the built-in potential of the first junction exists, and thus a depletion layer is formed. If the thickness of the drift layer is less than the thickness of the depletion layer, the effect of reducing the on-resistance is lost, so that the thickness of the drift layer is limited. When the same voltage is applied, the structure of the present invention has a smaller local concentration of the electric field and a lower maximum electric field than the conventional structure, so that the reliability can be improved.

A semiconductor device according to another aspect of the present invention includes a plurality of sets of a first drift region of a first conductivity type and a second drift region of a second conductivity type formed on an insulating substrate. A first buried region of a first conductivity type formed on an inner wall surface of a first trench reaching the substrate through the first and second drift regions and the plurality of sets; A second buried region of a second conductivity type formed in contact with the first buried region;
A first electrode formed in the second buried region, a second conductivity type body region formed in contact with an uppermost one of the plurality of sets of the first and second drift regions, and the body region; A region of a first conductivity type formed in a part of
A second trench, which is provided at a predetermined distance from the trench and reaches the substrate through the plurality of sets of the first and second drift regions, the body region, and the first conductivity type region. An insulating film formed on the inner wall surface of the second
A control electrode provided on the inner wall surface of the trench through the insulating film, and a second electrode provided in the region and the body region.

In a semiconductor device according to another aspect of the present invention, a plurality of sets of a first drift region of a first conductivity type and a second drift region of a second conductivity type are formed on a substrate via an insulating film. A first conductive type first buried formed on an inner wall surface of a first trench reaching the substrate through the first and second drift regions and the plurality of sets. A region, a second buried region of a second conductivity type formed in contact with the first buried region, a first electrode formed in the second buried region, a plurality of first and second sets of the plurality of sets. A second conductivity type body region formed in contact with the uppermost drift region of the second drift region;
A first conductivity type region formed in a part of the body region;
A plurality of first and second drift regions, the body region, and a region of the first conductivity type, which are provided at a position separated by a predetermined distance from the first trench, reach the substrate through the plurality of sets of the first and second drift regions. An insulating film formed on the inner wall surface of the second trench,
A control electrode provided on the inner wall surface of the second trench via the insulating film; and a second control electrode provided on the region and the body region.
Electrodes.

In a semiconductor device according to another aspect of the present invention, a plurality of sets of a first drift region of a first conductivity type and a second drift region of a second conductivity type are formed on a substrate of a high-resistance wide gap semiconductor. A set with a second drift region, the plurality of sets,
And a first buried region of a first conductivity type formed on the inner wall surface of the first trench reaching the substrate through the second drift region, and a first buried region formed in contact with the first buried region. A second buried region of the second conductivity type, a first electrode formed in the second buried region, and a second electrode formed in the uppermost drift region of the plurality of sets of the first and second drift regions. A second contact region formed at a predetermined distance from the first trench and reaching the substrate through the plurality of sets of the first and second drift regions and the contact portion. A second conductive type base region formed on the inner wall surface of the trench; a second electrode provided on the base region in the second trench; and a third electrode provided on the contact portion.

In a semiconductor device according to another aspect of the present invention, there are provided a plurality of sets of a first conductive type first drift region and a second conductive type first drift region formed on a high-resistance wide gap semiconductor substrate. Two drift regions, the plurality of sets,
And a first buried region of a first conductivity type formed on the inner wall surface of the first trench reaching the substrate through the second drift region, and a first buried region formed in contact with the first buried region. 2 buried region of a second conductivity type, a first electrode formed in the second buried region, and a position separated by a predetermined distance from the first trench. A base region of a second conductivity type formed on an inner wall surface of a second trench reaching the substrate through the second drift region, and a second electrode provided on the base region in the second trench And a third electrode facing the first buried region and the second buried region via an insulating film.

According to another aspect of the present invention, there is provided a semiconductor device comprising at least one set of a first conductive type semiconductor region and a second conductive type semiconductor region formed on a substrate; A second set of at least one set of the first conductivity type semiconductor region and the second conductivity type semiconductor region in contact with one end of the set of semiconductor regions, and the other of the first set of semiconductor regions. At least one set of a first conductive type semiconductor region and a second conductive type semiconductor region, which are in contact with an end portion, and a control electrode for applying an electric field to the third set of semiconductor regions; When a voltage is applied between the second set of semiconductor regions so that the potential of the second set of semiconductor regions is higher than the potential of the third set of semiconductor regions, the entire first set of semiconductor regions is depleted, and the second set of semiconductor regions is depleted. A voltage is applied between the two sets of semiconductor regions so that the potential of the semiconductor regions is higher than the potential of the third set of semiconductor regions. And when a voltage equal to or higher than a threshold is applied to the control electrode, electrons flow out of the third set of semiconductor regions and flow into the second set of semiconductor regions through the first set of semiconductor regions. Then, holes flow out of the second set of semiconductor regions, flow into the third set of semiconductor regions via the first set of semiconductor regions, and electrons and holes are introduced into the first set of semiconductor regions. So that the first state is present.
The shape and thickness of the set of semiconductor regions are selected.

[0036]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to FIGS. In the semiconductor device of each embodiment, a number of segments are formed adjacent to each other in the left-right direction in the figure. In each of the drawings, each element of the central segment is denoted by a reference numeral and described in detail. << First Embodiment >> FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention. The first embodiment is a wide gap semiconductor device, which is a SiC field effect transistor with a withstand voltage of 6100V. FIG. 1 shows a sectional structure of the segment. The insulating substrate 1 in the figure is an extremely high-resistance wide-gap SiC (silicon carbide) substrate containing impurities that form a deep energy level such as vanadium, has a resistivity of 10 ⁹ Ωcm or more, and has a thickness (see FIG. The vertical dimension is about 350 μm. A semiconductor device using an SiC substrate is generally called a wide gap semiconductor device. First
N-type drift region 2 of the same conductivity type and p-type second drift region 3 of the second conductivity type formed thereon have substantially the same thickness (that is, substantially the same thickness). Impurity concentration, the thickness is about 0.8 μm, and the impurity concentration is about 8 × 10 ¹⁶ atm / cm ³ . In the configuration of the present embodiment, the breakdown voltage depends on the difference in thickness and the difference in impurity concentration between the p-type drift region and the n-type drift region, and the smaller the difference, the higher the breakdown voltage. In order to effectively achieve the object of the present invention, the difference in thickness between the p-type drift region and the n-type drift region is ± 20% or less, and the difference in impurity concentration is ± 250%.
% Is desirable. On the left side of the p-type drift region 3, a p-type body region 4 having an impurity concentration of about 5 × 10 ¹⁷ atm / cm ³ is formed, in which an impurity concentration of 1 × 10 ¹⁹ atm / cm ³ and a thickness of 1 × 10 ¹⁹ atm / cm ³ . About 0.2 μm n
A mold source region 5 is formed. On the right side, an n-type drain region 6 having a high impurity concentration of 1 × 10 ¹⁹ atm / cm ³ , which is a buried region, is formed so as to reach the substrate 1, the n-type drift region 2 and the p-type drift region 3. The length of drift region 2, that is, the distance between body region 4 and drain region 6 is about 52 μm. p-type body region 4
Is formed with a groove reaching the insulating substrate 1, that is, a trench 10A. Gate electrode 10 is provided in trench 10 </ b> A via an oxide film as gate insulating film 9. A source electrode 7 is provided in the body region 4 and the source region 5. A drain electrode 8 is provided in the drain region 6. On the surface of p-type drift region 3, a Si oxide film or Si nitride film 11 is formed for surface protection.

An example of a method for manufacturing the SiC field effect transistor of the present embodiment will be described below. First, SiC insulating substrate 1
And 5 × 10 ¹⁵ to 3 × 1 on one surface
At a predetermined low impurity concentration between 0 ^{1 7} atm / cm ^3,
An n-type drift layer 2 having a predetermined thickness between 0.1 and 2.0 μm is formed, and then a p-type drift layer 3 having substantially the same thickness and the same impurity concentration is formed by a vapor phase growth method or the like. Further, a p-type body region 4 of about 6 × 10 ¹⁷ atm / cm ³ and an n-type drain region 6 of about 1 × 10 ¹⁹ atm / cm ³ are formed by ion implantation of nitrogen or the like.
In the case of using ion implantation, it is preferable that the implantation energy is sequentially changed from high energy to low energy, and the implantation is performed a plurality of times to obtain a substantially uniform impurity concentration distribution in the depth direction. Subsequently, an n-type source region 5 having an impurity concentration of about 1 × 10 ¹⁹ atm / cm ^{3 is} formed by ion implantation of nitrogen or the like. Next, a trench 10A is formed, and a gate oxide film 9 is formed on the inner wall. Thereafter, a surface protective film 11 of an insulating film such as a Si oxide film or a Si nitride film is formed by a vapor phase chemical deposition method. Finally, the insulating film at the contact portions of the source region 5, the body region 4, and the drain region 6 is removed, a metal film such as Al is formed in a predetermined region, and the source electrode 7, the gate electrode 10, and the drain electrode 8 are formed. .

Next, the operation of this embodiment will be described. In the SiC field effect transistor of this embodiment, when a high voltage is applied so that the potential of the drain electrode 8 is higher than the potential of the source electrode 7, the junction formed by the drift regions 2 and 3 is reverse-biased. As a result, a depletion layer spreads to both drift regions 2 and 3, and almost all drift regions 2 and 3 are completely depleted. From the junction formed by the drift region 3 and the drain region 6 to the junction formed by the drift region 2 and the body region 4, the potential distribution in the drift regions 2 and 3 becomes substantially equipotential. That is, the electric field is in the drift region 2
And 3 are almost uniform over the entire region, and this electric field is
The applied voltage can be increased until the breakdown electric field reaches about 3 MV / cm. As a result, the withstand voltage of the SiC field effect transistor can be increased. In the case of this embodiment, 620
A high withstand voltage of 0 V was realized.

When a high voltage is applied, electric field concentration may occur near the surface of the junction formed by the drift region 3 and the drain region 6, and the breakdown voltage may be regulated. Taking measures to alleviate this electric field concentration is effective in increasing the breakdown voltage. In the present embodiment, in order to reduce the electric field concentration, an electric field relaxation technique called a field plate, in which the drain electrode 8 extends over the drift region 3 via the thick surface protection film 11, is applied. In addition, since electric field concentration may occur at the corners of the trench 10A and the withstand voltage may be regulated, it is effective to take measures to alleviate the electric field also in this part.
In this embodiment, the trench 10A is deepened until it enters the insulating substrate 1, and the gate insulating film 9 and the insulating substrate 1 are connected.
The insulating film at the corners is substantially thickened to reduce the electric field. In the case of a structure in which the trench 10A is shallow and does not reach the insulating substrate 1, it is effective to provide a p-type region in the trench 10A to alleviate the electric field and the like, thereby achieving the same object as in the present embodiment.

When a voltage higher than the threshold voltage (6 V in this embodiment), for example, 10 V, is applied to the gate electrode 10, a channel is formed on the surface of the body region 4 by the electric field effect via the gate insulating film 9. You. As a result, a state where a current flows from the source region 5 to the drain region 6 through this channel, that is, an ON state is established. This current flows through the drift region 2 to the drain region 6. In the case of this embodiment, even if the impurity concentration of the drift regions 2 and 3 is increased, both the drift regions 2 and 3 can be completely depleted, so that a high breakdown voltage can be obtained. As described above, since the impurity concentration of both the drift regions 2 and 3 is high, the resistance becomes low at the time of ON. In principle, the impurity concentration can be increased by about two orders of magnitude without deteriorating the breakdown voltage, so that a great effect of reducing the on-resistance by about two orders can be obtained. In the case of this example, a low value of 140 mΩcm ² was obtained.

In this embodiment, the thickness of the n-type drift region 2 and the p-type drift region 3 formed thereon is 0.8 μm.
m and the impurity concentration were about 8 × 10 ¹⁶ atm / cm ³ , but as shown in the experimental data of the inventor in FIGS. 2 and 3,
When the thickness is 0.1 μm to 1.2 μm, the impurity concentration is about 5 × 10 ¹⁵ atm / cm ³ to 3 × 10 ¹⁷ atm /
If the value is between cm ³ , a SiC field effect transistor having a high withstand voltage and a low loss can be obtained. The thickness is 1.4 μm
As described above, the sudden decrease in the breakdown voltage when the impurity concentration is 3 × 10 ¹⁷ atm / cm ³ or more is because the junction formed between the drift region 2 and the body region 4 before the two drift regions 2 and 3 are completely depleted. This is because yielding occurred in the part.

In FIG. 1 of this embodiment, the shape of each segment is a stripe shape in a direction perpendicular to the plane of the paper, but may be, for example, a circle or a square. Although the body region 4 has the same thickness as the drift region 3 in this embodiment, the same effect can be obtained regardless of whether the body region 4 is made thicker or thinner. Even if the body region 4 is thinned and the drift region 3 is interposed between the body region 4 and the drift region 2, the same effect can be obtained. Further, although the drain region 6 is formed deeply so as to be in contact with the insulating substrate 1, it may be made shallower so as to be in contact only with the drift region 2. In this case, the production is easy because of the shallow depth, but electric field concentration occurs at the corner of the drift region 2 and the withstand voltage may decrease.

<< Second Embodiment >> FIG. 4 is a sectional view of a segment of a SiC field effect transistor according to a second embodiment of the present invention. The second embodiment is almost the same as the first embodiment except for the following three points. (1) A p-type drift region 12 thinner than the drift region 3 is provided between the drift region 2 and the insulating substrate 1. (2) The n-type drain region 6 is formed along the inner wall of the trench 6A reaching the insulating substrate 1, the drain region 6 is connected to the drift regions 2, 3 and 12, and the drain electrode 8 is provided on the surface of the drain region 6. Was it. (3) The trench 9A for the gate electrode 10 is formed so as to extend to reach the drift region 12, and the oxide film 9 and the gate electrode 10 are formed along the inner wall of the trench.

The thickness of the n-type drift region 2 is 1.3 μm,
The thickness of the p-type drift regions 3 and 12 is 0.8 μm, and the impurity concentration of each is approximately 7 × 10 ¹⁶ atm / cm ^3.
It is almost the same. The depth of the trench 6A is about 3.5
μm and the width is about 8 μm. The trench 9A has a depth of about 2.5 μm and a width of about 6 μm. In the field-effect transistor of this embodiment, the n-type drift region 2 is sandwiched between two p-type drift regions 3 and 12. As a result, when a high voltage is applied so that the potential of the drain electrode 8 is higher than the potential of the source electrode 7, the drift regions 2 and 3
And the junction formed by the drift regions 12 and 2 are simultaneously reverse-biased, and the depletion layer expands into the drift region 2 from both the drift regions 3 and 12. Since the thickness of the drift region 2 is more than twice the thickness of the drift region 3,
When the drift layers 3 and 12 are depleted at a predetermined high voltage, the drift layer 2 is also almost completely depleted. As a result, from the drain electrode 8 toward the gate electrode 10, the potential distributions of the drift regions 2, 3, and 12 become substantially equal potential distributions. That is, the electric field is substantially uniform over the entire drift regions 2, 3, and 12. Since the applied voltage can be increased until this electric field reaches about 3 MV / cm of the dielectric breakdown electric field of SiC, the withstand voltage can be increased, and in the case of the present embodiment, a high withstand voltage of 6100 V can be realized.

In the ON state in which a high voltage equal to or higher than the threshold voltage is applied to gate electrode 10, a current flows from region 5 to drain region 6 through a channel formed in body region 4 and drift region 2. Since the thickness of the drift region 2 is about 1.6 times the thickness of the drift region 3,
Considering that the thickness of the drift region is slightly reduced due to the depletion layer due to the build-in voltage of the upper and lower junctions of the drift region 2, the resistance of the drift regions 2, 3, and 12 is equal to the case where the thickness of the drift regions 2 and 3 is the same. Is about 1 / 1.6 or less. Since the resistance can be reduced in this way, in the case of the present embodiment, the ON resistance can be realized as low as 90 mΩcm ² . As described above, in this embodiment, there is an effect that the on-resistance can be further reduced while maintaining the high withstand voltage. In this embodiment, the width and depth of the trench 9A of the gate electrode 10 are different from those of the trench 6A of the drain region 6.
The above depth may be substantially the same as the depth of the trench 6A so as to reach the insulating substrate. In this case, the electric field concentration at the corners of trench 9A is further alleviated, and the withstand voltage and reliability are improved.

<< Third Embodiment >> FIG. 5 is a sectional view of a segment of an SiC field effect transistor according to a third embodiment of the present invention. On the SiC insulating substrate 1 having a thickness of 320 μm, p-type drift regions 23, 23A, 23B, 23 are provided between the n-type drift regions 22, 22A, 22B, 22C.
Five sets of an n-type drift region and a p-type drift region formed sandwiching each of C are sequentially laminated. The trenches 6 </ b> A, 9 are provided at both ends of each of the stacked drift regions 22, 23.
A is provided so as to reach the insulating substrate 1. The trench 9A is for a gate portion, and a gate electrode 10 is provided via a gate oxide film 9. The trench 6A is for a drain portion, and a drain region 16 and a drain electrode 8 are provided on an inner wall. A p-type body region 34, an n-type source region 5, and a source electrode 37 connected to these regions are provided on the gate portion side of the uppermost p-type drift region 33. On the surface of the p-type drift region 33, a surface protective film 11 such as a Si oxide film or a Si nitride film is provided for protection. N-type and p-type drift regions 22, 23
Have a thickness of about 0.8 μm and an impurity concentration of about 8 × 10
¹⁶ atm / cm ³ , and both lengths are about 75 μm. p
The impurity concentration of the mold body region 34 is about 5 × 10 ¹⁷ atm.
/ Cm ³ and a thickness of about 0.8 μm, and the n-type source region 5 formed therein has an impurity concentration of 1 × 10 ¹⁹ atm.
/ Cm ³ and a thickness of about 0.2 μm. Drain region 16
Is 1 × 10 ¹⁹ atm / cm ³ , and the depth of the trench 6A is about 10 μm.

In the field effect transistor of this embodiment, n
The drift region 22 is sandwiched between two p-type drift regions 23. Similarly, the p-type drift region 23 is sandwiched between two n-type drift regions 22. With this configuration, when a high voltage is applied so that the potential of the drain electrode 8 is higher than the potential of the source electrode 37, the depletion layers spread from both sides to the respective drift regions 22 and 23 and are almost completely depleted. . As a result, the potential distribution of the drift regions 22 and 23 from the drain electrode 8 toward the gate electrode 10 becomes substantially equal potential distribution, and
23 becomes almost uniform over the entire area. This electric field is SiC
Since the applied voltage can be increased until the breakdown electric field reaches about 3 MV / cm, the breakdown voltage can be increased. In this embodiment, a high withstand voltage of 8300 V was realized.

On the other hand, when a voltage is applied so that the drain electrode 8 has a higher potential than the source electrode 7 and a voltage higher than the threshold is applied to the gate, the gate electrode 10 is turned on.
Electrons gather on the surfaces of the body region 4 and each of the drift regions 2 and 3 opposing to each other to form an inversion layer. Also, electrons accumulate on the surface of each of the drift regions 2 and 3 facing the gate electrode 10 to form an accumulation layer. Body area 4
Functions as a channel, and a current flows from the source region 5 to the drain region 16 through the channel and the second n-type drift region 22D from the top. Part of the current is n
Through the storage layer of the drift layer 22D and the inversion layer of the p-type drift region 23C of the third layer from the top, the current flows to the fourth n-type drift region 22C and flows to the drain region 6. Similarly, a part of the current is shunted to the n-type drift region 22A close to the substrate 1 via the accumulation layer of the n-type drift region 22C and the inversion layer of the p-type drift region 23B, and flows to the drain 6. As the n-type drift layer becomes closer to the substrate 1, the n-type drift region 2
2 and the resistance of the inversion layer of the p-type drift region 23 are added. Therefore, the resistance slightly increases and the shunt current tends to decrease. However, in the case of the present embodiment, this was not at a level that would cause any particular problem. n-type drift regions 2, 2A, 2B,
The combined resistance of 2C and 2D is reduced to about ５ of that of the configuration of FIG. 1, and the on-resistance of the field effect transistor can be greatly reduced. In the case of the present example, the on-resistance per unit area of the drift region was significantly reduced to 47 mΩcm ² , despite the increase in the withstand voltage to 8300 V.

As described above, the present embodiment has the effect that the on-resistance can be reduced further without impairing the breakdown voltage. This on-resistance can be reduced as the number of stacked pairs of the n-type drain regions 22, 22A,... and the p-type drain regions 23, 23A,. However, if the number of stacked layers is excessively increased, the resistance of each of the inversion layers described above is added, so that the resistance of the underlying n-type and p-type drift regions increases. Therefore, it is necessary to devise a method for equalizing the resistances of the upper and lower n-type and p-type drift regions. For example, as shown in FIG. 6, a configuration in which the lower n-type and p-type drift regions are thicker is extremely effective. The rate of increase in the thickness of the lowermost drift region 22 with respect to the uppermost drift region 33 is as follows:
Although it depends on the length of each drift region in the left-right direction in the figure and the number of pairs of the n-type drift region 22 and the p-type drift region 23,
For example, when the number of pairs is 15, for example, about 1.3 times is preferable. In FIG. 6, both p-type and n-type drift regions 2
Although the lower layers 2 and 23 are successively thicker, the same effect can be obtained by sequentially increasing only the thickness of the n-type drift region while keeping the thickness of the p-type drift region constant. Also in this case, the thickness of the lowermost n-type drift region 22 is preferably about 1.3 times the thickness of the uppermost n-type drift region.

Fourth Embodiment FIG. 7 is a sectional view of a segment of a SiC field effect transistor according to a fourth embodiment of the present invention. In this embodiment, the gate portion including the gate electrode 10 has a planar structure, the drift region 3 in contact with the insulating substrate 1 is p-type, and the drift region 2 thereover is n-type. Except that the polarity has been changed in this way, and that the n-type drain region 6 and the p-type body region 4 reach the insulating substrate 1, the other structure is almost the same as that of the first embodiment. The thickness, length and impurity concentration of the drift regions 2 and 3 are the first
This is almost the same as the embodiment. The impurity concentrations of the n-type source region 5 and the p-type body region 4 are the same as in the first embodiment.

The functions of both drift regions 2 and 3 when a high voltage is applied are basically the same as those of the first embodiment, and a high breakdown voltage can be realized by this configuration. The ON operation is basically the same. When a voltage equal to or higher than the threshold is applied to the gate electrode 10 with the voltage applied to the source electrode 7 and the drain electrode 8, the body region 4 immediately below the gate electrode 10 is applied.
The channel is formed by reversing the polarity of the surface electric field of 0.
As a result, a current flows from the source electrode 7 to the n-type drift region 2 through the channel, and flows into the drain 8. In this embodiment, the withstand voltage is 6100 V and the on-resistance is 130 mΩcm.
² SiC field-effect transistors were realized. In this embodiment, the p body region 40 is formed only by ion implantation of boron or the like, and the n-type source region 5 is formed by ion implantation of nitrogen or the like without forming the trenches 6A and 10A as shown in FIG. And therefore it is very easy to manufacture.

<< Fifth Embodiment >> FIG. 8 is a sectional view of a segment of a SiC field effect transistor according to a fifth embodiment of the present invention. In the present embodiment, the gate structure including the gate electrode 10 has a planar structure, and the other structures are the same as those of the first embodiment except that the n-type drift region 2 extends to the surface immediately below the gate electrode 10. Almost the same. The thickness, length, and impurity concentration of the drift regions 2 and 3 are substantially the same as in the first embodiment. The impurity concentrations of the n source region 5 and the p body region 4 are almost the same as in the first embodiment.

The functions of both drift regions 2 and 3 when a high voltage is applied are basically the same as in the first embodiment, and a similar high breakdown voltage can be realized. The ON operation is basically the same. When a voltage equal to or higher than the threshold is applied to the gate electrode 10 while a voltage is applied to the source electrode 7 and the drain electrode 8, the electric field on the surface of the p-type body region 4 immediately below the gate electrode 10 is inverted to form a channel. A current flows from the source electrode 7 to the drain electrode 8. This current is applied to the gate electrode 1
It passes through the n-type drift region 2 immediately below 0 and then reaches the drain region 6 through the n-drift region 2 existing below the p-type drift region 3. In the SiC field-effect transistor of this embodiment, the withstand voltage is 6200 V, and the on-resistance is 150 mΩcm ^2.
Met. In this embodiment, without forming a trench,
The p-type body region 4 can be formed only by ion implantation of boron or the like, and the n-type source region 5 can be formed by ion implantation of nitrogen or the like.
Can be formed, so that it is very easy to manufacture.

Sixth Embodiment FIG. 9 is a sectional view of a segment of a gallium nitride (hereinafter referred to as GaN) field effect transistor according to a sixth embodiment of the present invention. The insulating substrate 1 is a SiC substrate containing impurities such as vanadium, and has a resistivity of 10 ⁹ Ωcm or more and a thickness of about 350 μm. G
The n-type drift region 2 of aN and the p-type drift region 3 formed thereon have substantially the same thickness and impurity concentration, the thickness is about 0.8 μm, and the impurity concentration is about 8 × 10
^{It is 16} atm / cm ³ . At the left end of the p-type drift region 3, a p-type body region 4 having an impurity concentration of about 5 × 10 ¹⁷ atm / cm ³ is formed. Body area 4
An n-type source region 5 having an impurity concentration of 1 × 10 ¹⁹ atm / cm ³ and a thickness of about 0.2 μm is formed therein. At the right end, n having a high impurity concentration of 1 × 10 ¹⁹ atm / cm ³
The drain region 6 is formed so as to be in contact with the n-type drift region 2. The length of drift region 3, that is, the distance between body region 4 and drain region 6 is about 50 μm. A trench 9A is formed to penetrate p-type body region 4 and reach drift region 2, and a gate electrode 10 is formed on the inner wall of trench 9A via oxide film 9. A source electrode 7 is provided in the body region 4 and the source region 5, and a drain electrode 8 is provided in the drain region 6. On the surface of p-type drift region 3, a Si nitride film 11 is formed for surface protection.

The operation of this embodiment is almost the same as that of the first embodiment. However, GaN has better physical and electrical characteristics than SiC, and is therefore suitable for a power semiconductor device. In this embodiment, a G with a withstand voltage of 6600 V and an on-resistance of 80 mΩcm ² is used.
An aN field effect transistor was obtained. GaN is SiC
Compared with the above, the compatibility of the surface protective film 11 with the Si nitride film is good, and the reliability is further improved. GaN has a higher electron saturation speed than SiC and is suitable for high-speed operation. In this embodiment, a cutoff frequency of 6 GHz was realized.

<< Seventh Embodiment >> FIG. 10 is a sectional view of a semiconductor device according to a seventh embodiment of the present invention. Show. The semiconductor device of the seventh embodiment is manufactured using SiC. A wide gap semiconductor material represented by SiC is silicon (S
Since the breakdown electric field strength is higher than in i), a higher breakdown voltage can be realized with the same impurity concentration as that using Si.
That is, there is an advantage that high withstand voltage can be maintained while maintaining low loss, operation can be performed at a high temperature of 250 ° C. or higher, and thermal conductivity is good. In FIG. 10, an insulating substrate 1 is made of SiC containing impurities for forming a deep energy level such as vanadium.
It is a substrate. Its resistivity is 10 ⁹ Ωcm or more and its thickness is about 350 μm. An n-type first drift region 2 formed on an insulating substrate 1 and a p-type drift region 2 formed thereon
The second drift region 3 of the mold has substantially the same thickness and impurity concentration, a thickness of about 0.8 μm, and an impurity concentration of about 8 × 10 ¹⁶ cm ³ .

In contact with one end of drift region 3, p-type body region 4 having an impurity concentration of about 5 × 10 ¹⁷ cm ³ is formed, and impurity concentration of 1 × 10 ¹⁹ cm 3 is formed therein.
^3. An n-type emitter region 55 having a thickness of about 0.2 μm is formed. A first trench 6 </ b> A, which is a groove reaching the insulating substrate 1, is formed at the other end of the drift region 3. The inner wall of the trench 6A is in contact with the drift regions 2 and 3,
An n-type buffer region 66 as a first buried region having an impurity concentration of 1 × 10 ¹⁸ cm ³ is formed. A p-type collector region 77 as a second buried region having an impurity concentration of 1 × 10 ²⁰ cm ³ is formed on a surface of n-type buffer region 66, and collector electrode 39 reaches insulating substrate 1 in collector region 77. It is formed to the depth. Length of drift region 3, ie, body region 4 and buffer region 6
The distance between 6 is about 52 μm.

In the vicinity of p type body region 4, a second trench 9A reaching insulating substrate 1 is formed. A gate electrode 40 is provided on the inner wall surface of the trench 9A via a gate insulating film 38. An emitter electrode 88 is provided in contact with body region 4 and emitter region 55. A protective film 45 made of a Si oxide film or a Si nitride film is provided on the surface of the drift region 3 for surface protection.

One example of a method of manufacturing the transistor of this embodiment is as follows. First, an SiC insulating substrate 1 is prepared, and 5 × 10 ¹⁵ to 3 × 10 ¹⁷ at
0.1 to 2.0 μm at a predetermined low impurity concentration between m / cm ³
An n-type drift region 2 having a predetermined thickness between m is formed by a vapor phase growth method or the like. Next, a p-type drift region 3 having substantially the same thickness and impurity concentration is formed by a vapor deposition method or the like. An SiO ₂ insulating oxide film is formed on the p-type drift region 3 to form a surface protection film 45. Next, the first trench 6A is formed by etching or the like. Then, an n-type buffer region 66 and a p-type collector region 77 are sequentially formed on the inner wall surface of the trench 6A by ion implantation or diffusion. Further, a p-type body region 4 is formed so as to be in contact with drift regions 2 and 3, and n-type body region 4 is partially formed in n-type body region 4.
The mold emitter region 55 is formed by ion implantation or the like. When the ion implantation method is used, it is preferable that the implantation energy is sequentially changed from a high energy to a low energy, and the implantation is performed a plurality of times to obtain a substantially uniform impurity concentration distribution in the depth direction. Next, a second trench 9A is formed,
A gate insulating film 38 is formed on the upper surface including the inner wall surface, and a gate electrode 40 is formed thereon. In order to form the emitter electrode 88 and the collector electrode 39, the portions of SiO ₂ are formed.
The insulating oxide film is removed, a metal film such as Al is formed, and the emitter electrode 88 and the collector electrode 39 are formed to complete the process.

Next, the operation of this embodiment will be described. In the SiC-IGBT of this embodiment, when a high voltage is applied such that the potential of the collector electrode 39 is higher than the potential of the emitter electrode 88, the junction formed by the drift regions 2 and 3 is reverse-biased and both drifts occur. The depletion layer extends to the regions 2 and 3, and almost the entire region is completely depleted. Therefore, the potential distributions of drift regions 2 and 3 from buffer region 66 toward body region 4 are substantially equal potential distributions. That is,
The electric field becomes substantially uniform over the entire drift regions 2 and 3. This electric field is about 3 MV / which is the dielectric breakdown electric field of SiC.
cm, so that the applied voltage can be increased until the voltage reaches a maximum value. In the case of the present embodiment, a high withstand voltage of 6100 V was realized.

When a high voltage is applied, electric field concentration occurs near the surface of the junction formed by the drift region 3 and the buffer region 66, and the breakdown voltage may be limited. It is effective to take measures to alleviate the electric field concentration to increase the breakdown voltage. In the present embodiment, in order to reduce the electric field concentration, an electric field relaxation technique called a field plate, in which the collector electrode 39 extends over the drift region 3 via the thick surface protection film 45, is applied. ing.
Further, the corner portion 21 of the trench 9A of the gate electrode 40
Since electric field concentration occurs at A and the withstand voltage may be regulated,
It is effective to take an electric field relaxation measure also in this part. In this embodiment, the trench 9A is deepened to the position reaching the insulating substrate 1, the gate insulating film 38 and the insulating substrate 1 are connected, and the gate insulating film 38 at the corner 21A is made substantially thicker to reduce the electric field. I'm trying. In the case of a structure in which the trench 9A is shallow and does not reach the insulating substrate 1, p is formed at the bottom of the trench 9A.
It is effective to provide a mold region to alleviate the electric field (not shown) and the like, whereby the same effect as in the present embodiment can be obtained. The same applies to the corner 21B of the trench 6A.

Next, when a voltage higher than the threshold voltage (4 V in this embodiment), for example, 10 V, is applied to the gate electrode 40, a channel effect is applied to the surface of the body region 4 by the electric field effect applied through the gate insulating film 38. Is formed. As a result, a state where electrons flow from emitter region 55 through this channel, that is, an ON state is established. When the electrons reach the buffer region 66 through the drift region 2, holes flow from the collector region 77 to the drift region 2 and reach the emitter electrode 88 via the body region 4. In this manner, both electrons and holes are present in the drift region 2, and conductivity modulation occurs to drastically reduce the resistance of the drift region 2. In the case of this embodiment, the drift regions 2 and 3 can be completely depleted by increasing the impurity concentration in order to reduce the resistance, so that the breakdown voltage can be increased. Further, since conductivity modulation is caused in the drift region 2 and the impurity concentration of the drift region 2 can be made higher than that of the conventional one, the on-resistance can be greatly reduced. In principle, the impurity concentration can be increased by about two orders of magnitude without impairing the breakdown voltage, so that the on-resistance can be reduced by about two orders. In the case of the specific example of this embodiment, the ON resistance in a voltage range higher than the built-in voltage (2.7 V) of SiC is 56 mΩ.
cm ² , which is a low value that cannot be obtained with the conventional device.

In this embodiment, the n-type drift region 2
And the p-type drift region 3 formed thereon has a thickness of 0.8 μm and an impurity concentration of about 8 × 10 ¹⁶ cm ³ , as apparent from the data of the graphs shown in FIGS. 2 and 3. The thickness of the drift regions 2 and 3 is 0.1 μm to 2 μm.
During μm, the impurity concentration is about 1 × 10 ¹⁵ cm ³ to 3 ×
If the value is between 10 ¹⁷ cm ³ , a semiconductor device with high withstand voltage and low loss can be obtained. 2 and 3, the thickness is 2 μm.
As described above, the rapid decrease in the breakdown voltage when the impurity concentration is 3 × 10 ¹⁷ cm ³ or more is caused by the junction between the drift region 2 and the body region 4 before the two drift regions 2 and 3 are completely depleted. This is because a breakdown similar to the structure has occurred.

In the present embodiment, the shape of the segment is a stripe shape, but it may be, for example, a circle or a square. In this embodiment, the p-type body region 4 has the same thickness as the p-type drift region 3. However, even if the p-type body region 4 is made thicker than the n-type draft region 3, or vice versa, the same effect can be realized. The same effect can be obtained when another p-type drift layer is interposed between the p-type body region 4 and the n-type drift region 2 (not shown). Furthermore,
Although the n-type buffer region 66 is formed deeply so as to be in contact with the insulating substrate 1, the n-type buffer region 66 may be made so shallow as to be in contact with only the n-type drift region 2. In this case, the shallowness facilitates the fabrication, but care must be taken because the electric field concentration may occur at the corner 21B of the n-type drift region 2 and the withstand voltage may decrease.

<< Eighth Embodiment >> FIG. 11 is a sectional view of a segment of an SiC-IGBT according to an eighth embodiment of the semiconductor device of the present invention. In the figure, a p-type drift region 3 is formed on the uppermost layer on a SiC insulating substrate 1 having a thickness of about 320 μm, with p-type drift regions 33A to 33D interposed between n-type drift regions 32A to 32E, respectively. Five pairs of n-type drift regions and p-type drift regions are stacked.
Both drift regions 32A-32E, 33A-3 laminated
The first trench 6A and the second trench 6A are provided at both ends of the 3D, respectively.
Are provided so as to reach the insulating substrate 1. The second trench 9A is a gate portion, and a gate electrode 40 is provided on an inner wall of the second trench 9A via a gate insulating film 38. The first trench 6A has an n-type buffer region 66, a p-type collector region 77 and a collector electrode 39.
Are sequentially provided. A p-type body region 4 and an n-type emitter region 55 are provided in a portion of the uppermost p-type drift region 3 close to the gate electrode 40, and an emitter electrode 88 connected to these regions is provided. A protective film 45 such as a Si oxide film or a Si nitride film is provided on the surface of the p-type drift region 3 for protection. Drift area 3
The thickness of each of the drift regions 2A to 32E and the drift regions 33A to 33D is about 0.8 μm, the impurity concentration is about 8 × 10 ¹⁶ cm ³ ,
The length is about 75 μm. The impurity concentration of the p-type body region 4 is about 5 × 10 ¹⁷ cm ³ and the thickness is about 0.8 μm. The impurity concentration of the n-type emitter region 55 formed therein is 1 × 10 ¹⁹ cm ³ and the thickness is The length is about 0.2 μm. The impurity concentration of the n-type buffer region 66 in the trench 6A is 1 × 10 ¹⁸ cm ³ , and the impurity concentration of the p-type collector region 77 is 1 × 10 ²⁰ cm ³ . Trench 6A,
The depth of each 9A is about 10 μm.

In the SiC-IGBT of this embodiment, each of the n-type drift regions 32B to 32E except for the lowermost n-type drift region 32A is a p-type drift region 3 and 33A to 33D.
It is sandwiched between adjacent objects. With this configuration, when a high voltage is applied so that the potential of the collector electrode 39 is higher than the potential of the emitter electrode 88, the p-type drift regions 33A to 33D have n-type drift regions 32A to From 32E, the depletion layer is effectively expanded and completely depleted. Also, each of the n-type drift regions 32A to 32A
P type drift regions 33A to 33D vertically adjacent to E
The depletion layer is effectively expanded from the above, and is completely depleted. As a result, the potential distribution of all the drift regions 32A to 32E and 33A to 33D between the buffer region 66 and the gate electrode 40 becomes substantially equal potential distribution, and the electric field becomes substantially uniform over the entire drift region. Since the applied voltage can be increased until the electric field reaches about 3 MV / cm, which is the dielectric breakdown electric field of SiC, the withstand voltage can be increased. In the case of the present embodiment, a high withstand voltage of 5800 V can be realized.

On the other hand, when a high voltage is applied so that the potential of the collector electrode 39 becomes higher than the potential of the emitter electrode 88 and a high voltage equal to or higher than the threshold is applied to the gate electrode 40 to turn on the gate electrode 40, the vicinity of the gate electrode 40 Electrons are collected on the surface of the p-type body region 4 and the respective p-type drift regions 33A to 33D to form an inversion layer. On the other hand, electrons are also collected on the surface of each of the n-type drift regions 32A to 32E near the gate electrode 40 to form a storage layer. The inversion layer of the p-type body region 4 functions as a channel, and the p-type body region 4
Then, electrons flow into the buffer region 66 through the n-type drift region 32E of the second layer from the top. Some of the electrons flow through the storage layer of the n-type drift region 32E and the inversion layer of the third p-type drift region 33D from the top to the fourth n-type drift region 32D and flow into the buffer region 66. Similarly, a part of the electrons is stored in the storage layer of the n-type drift region 32D and p
6, 8, 1 from above through the inversion layer of the drift region 33C.
The current is diverted to the n-type drift regions 32C, 32B, and 32A of the 0th layer and flows to the buffer region 66. When the electrons reach the buffer region 66, holes flow from the p-type collector region 77 into the n-type drift regions 32A to 32E, and the inversion layers of the p-type drift regions 33A to 33D and the n-type drift regions 32A to 32E.
After reaching the emitter electrode 88 through the p-type body region 4 through the accumulation layer of 32E. Thereby, n-type drift region 32A
Since electrons and holes are present in .about.32E, conductivity modulation occurs, and the resistance of the n-type drift regions 32A to 32E sharply decreases. In this process, each p-type drift region 33A
Since electrons are injected from the adjacent n-type drift region also to .about.33D, conductivity modulation occurs and the resistance of the p-type drift region decreases. Since the resistances of the storage layers of the n-type drift regions 32A to 32E and the inversion layers of the p-type drift regions 33A to 33D are added closer to the lower n-type drift region 32A, the resistance value slightly increases and the shunt current tends to decrease. However, in the case of the present embodiment, the problem was not particularly problematic. Thereby, the n-type drift regions 32A to 32E and p
The resistance of the mold drift regions 33A to 33E is reduced to about ３ of the case where the conductivity modulation does not occur, and the ON resistance of the SiC-IGBT can be significantly reduced. In the case of the present embodiment, the on-resistance per unit area could be significantly reduced to 18 mΩcm ² despite the high withstand voltage of 5800 V.

As described above, according to the present embodiment, the effect that the on-resistance can be greatly reduced while maintaining a high withstand voltage can be obtained. As the number of stacked pairs of the n-type drift regions 32A to 32E and the p-type drift regions 33A to 33D increases, the on-resistance can be reduced. However, if the number of layers is excessively increased, as described above, the lower n-type drift region 32A is formed.
Since the resistance increases as the distance between the upper and lower n-type drift regions 32E and 32A increases, it is necessary to take measures to make the resistances of the upper and lower n-type drift regions 32E and 32A uniform. For example, the lower the layer, the more the n-type drift region 32
It was extremely effective to gradually increase the thicknesses of A to 32E and p-type drift regions 33A to 33E.
The rate of increase in the thickness of the lowermost drift region 33A depends on the length of each drift region and the number of stacked pairs of an n-type drift region and a p-type drift region. It is preferable to increase the thickness of the lowermost p-type drift region 33A to about 1.3 times that of the uppermost p-type drift region 3. Although the withstand voltage is reduced to 5200 V, the same effect can be obtained on the on-resistance even if the thicknesses of the p-type drift regions 33A to 33D are kept constant and only the thicknesses of the n-type drift regions 32A to 32E are sequentially increased. Can be Also in this case, the thickness of the lowermost n-type drift region 32A is preferably approximately 1.3 times the thickness of the uppermost n-type drift region 32E. The power capacity can be increased by forming a plurality of the present semiconductor devices on one substrate and connecting the same kind of electrodes of each of these semiconductor devices in common by connecting them in parallel. For example, in the case of the present embodiment, a current capacity of 40 A per 1 cm ² of chip area can be obtained by parallel connection, and a current capacity of 1000 A can be obtained by making the chip area 25 cm ² .

<< Ninth Embodiment >> FIG. 12 shows a silicon IGBT (hereinafter referred to as Si-IGB) according to a ninth embodiment of the semiconductor device of the present invention.
FIG. 4 is a cross-sectional view of a segment denoted by T). About 400 thick
An insulating film 13 of SiO ₂ is formed on a μm Si substrate 41, and three sets of each of n-type drift regions 42A to 42C and p-type drift regions 43A to 43C are sequentially laminated. Drift region 42A stacked
~ 42C, 43A ~ 43C in the vicinity of both ends
The first and second trenches 6A and 9A having a thickness of .mu.m
It is provided to reach. The second trench 9A is for the gate electrode 40, and the gate electrode 40 is provided on the inner wall of the trench 9A via the gate insulating film 38.
Further, the n-type buffer region 6 is provided in the first trench 6A.
6, a p-type collector region 77, and a collector electrode 39 are sequentially provided. A p-type body region 4 and an n-type emitter region 55 are provided on the side of the uppermost p-type drift region 43C near the gate electrode 40, and an emitter electrode 88 is provided so as to be connected to these regions. On the surface of the p-type drift region 43C, a protective film 45 such as a Si oxide film or a Si nitride film is provided for protection. Each of the n-type and p-type drift regions 42A to 42C and 43A to 43C has a thickness of about 1.5 μm and an impurity concentration of about 2.8 × 10 ¹⁵ cm.
^{3. The} length is about 320 μm. The impurity concentration of the p-type body region 4 is about 5 × 10 ¹⁷ cm ³ and the thickness is about 0.5 μm
The n-type emitter region 55 formed therein has an impurity concentration of 1 × 10 ¹⁹ cm ³ and a thickness of about 0.2 μm. The impurity concentration of the n-type buffer region 66 in the trench 6A is 1 × 10 ¹⁸ cm ³ , and the impurity concentration of the p-type collector region 77 is 1 × 10 ²⁰ cm ³ .

In the Si-IGBT of this embodiment, each of n-type drift regions 42B and 42C is formed with p-type drift regions 43A to 43A.
43C are sandwiched between adjacent ones. Also, the p-type drift region 43A has two n-type drift regions 4
2A and 42B. In this state, when a high voltage is applied so that the potential of the collector electrode 39 is higher than the potential of the emitter electrode 88, each of the drift regions 42A to
In 42C, 43A to 43C, a depletion layer is effectively spread from both upper and lower sides, and is completely depleted. As a result, the drift region 4 moves from the buffer region 66 toward the gate electrode 40.
The potential distributions of 2A to 42C and 43A to 43C become substantially equipotential distributions, and the electric field becomes substantially uniform over the entire drift region. This electric field is about 0.3 M of the dielectric breakdown electric field of Si.
Since the applied voltage can be increased until the voltage reaches V / cm, the withstand voltage can be increased. In the case of this embodiment, 4100
High withstand voltage of V was realized.

On the other hand, when a high voltage is applied so that the potential of the collector electrode 39 becomes higher than the potential of the emitter electrode 88 and a voltage equal to or higher than the threshold is applied to the gate electrode 40, the p-type near the gate electrode 40 is turned off. Body area 4
Electrons are collected on the surface of each of the p-type drift regions 43A to 43C to form an inversion layer. Electrons are also collected on the surface of each of the n-type drift regions 42A to 42C near the gate electrode 40 to form a storage layer. p-type drift region 4
The inversion layers 3A to 43C function as channels, and electrons flow from the emitter region 55 into the buffer region 66 through the channel and the n-type drift region 42C in the second layer from the top. Some of the electrons flow into the buffer region 66 through the storage layer of the n-type drift region 42C and the inversion layer of the third p-type drift region 43B from the top through the fourth n-type drift region 42B. Similarly, a part of the electrons is accumulated in the storage layer of the n-type drift region 42B and the p-type drift region 43B.
Flows through the n-type drift region 42A of the sixth layer into the buffer region 66 through the inversion layer. When the electrons reach the buffer region 66, holes flow from the p-type emitter region 77 into the n-type drift regions 42A to 42C and pass through the accumulation layers of the p-type drift regions 43A to 43C and the n-type drift regions 42A to 42C. The emitter electrode 88 passes through the body region 4
Reach Thus, n-type drift regions 42A-4A
Since both electrons and holes are present in 2C, conductivity modulation occurs, and the resistance of the n-type drift regions 42A to 42C sharply decreases. In this process, each p-type drift region 33A-
Electrons are injected from the adjacent n-type drift region to 33D, so that conductivity modulation occurs and the resistance of the p-type drift region is reduced. The closer to the lower n-type drift region 42A, the more the resistance of the storage layers of the n-type drift regions 42A to 42C and the resistance of the inversion layer of the p-type drift regions 43A to 43C are added. However, in the case of this embodiment, it was not so much as to cause a problem.
In the present embodiment, the resistance of the n-type drift regions 42A to 42C is reduced to about １ ／ of the case where there is no conductivity modulation, and the on-resistance of the field effect transistor can be greatly reduced. In the case of this example, the on-resistance in a voltage range higher than the built-in voltage per unit area could be significantly reduced to 710 mΩcm ² while keeping the breakdown voltage high at 4100 V.

As described above, in this embodiment, the on-resistance can be greatly reduced without deteriorating the breakdown voltage. This on-resistance can be reduced by increasing the number of stacked pairs of the n-type drift regions 42A to 42C and the p-type drift regions 43A to 43C. However, if the number of stacked layers is excessively increased, as described above, the resistance increases as the layer is closer to the lower n-type drift region 42A.
It is necessary to take measures to make the resistances of the upper and lower n-type and p-type drift regions uniform. For example, n-type and p
It was extremely effective to gradually increase the mold drift region. The rate of increase in the thickness of the lowermost drift region 42A depends on the length of the drift region and the n-type drift regions 42A to 42A.
Although it depends on the number of laminations of the set of 42C and the p-type drift regions 43A to 43C, for example, when the number of laminations is 15, for example, the lowermost p-type drift region 43A with respect to the uppermost p-type drift region 43C. Is preferably about 1.3 times. In addition, although the withstand voltage is slightly lowered, the same effect can be obtained with respect to the on-resistance even if the thickness of the p-type drift region is made constant and only the thickness of the n-type drift region is sequentially increased. The thickness of the drift region 42A is preferably about 1.3 times the thickness of the uppermost n-type drift region 42C.

<< Tenth Embodiment >> FIG. 13 shows a tenth embodiment of the present invention.
Example SiC turn-off thyristor (hereinafter referred to as SiC-thyristor)
FIG. 4 is a cross-sectional view of a segment (referred to as GTO). About 3 thickness
Each of n-type drift regions 52A to 52C and p-type drift region 5 are sequentially formed on 20 μm SiC insulating substrate 51.
Three sets of each of 3A to 53C are stacked. Trench 6A is provided near both ends of stacked n-type drift regions 52A to 52C and p-type drift regions 53A to 53C.
9A is provided so as to reach the insulating substrate 51. A p-type base region 94, an n-type emitter region 95, and a cathode electrode 58 are sequentially provided on the inner wall of the trench 9A.
Further, an n-type base region 86,
A p-type emitter region 87 and a collector electrode 69 are sequentially provided. A p-type contact portion 14 connected to a p-type base region 94 is provided in a portion of the uppermost p-type drift region 53C near the n-type emitter region 95. The contact portion 14 is connected to the gate electrode 40. On the surface of the p-type drift region 53C, a protective film 45 such as a Si oxide film or a Si nitride film is provided for protection. N-type and p-type drift regions 52A to 52C, 53A to 53C
Have a thickness of about 0.8 μm and an impurity concentration of about 8 × 10
¹⁶ cm ³ , and the length is about 75 μm. The impurity concentration of the p-type and n-type base regions 94 and 86 is about 7 × 10 ¹⁷ cm.
^{3. The} thickness is about 1.2 μm. The n-type and p-type emitter regions 95 and 87 have an impurity concentration of 1 × 10 ²⁰ cm ³ and a thickness of about 0.4 μm. The depth of each of the trenches 6A and 9A is about 6 μm.

In the SiC-GTO of this embodiment, n-type drift regions 52B and 52C are replaced by p-type drift regions 53A to 53A.
3C, it is sandwiched between adjacent ones. Further, p-type drift region 53A is adjacent to n-type drift region 5A.
It is sandwiched between 2A and 52B. In this state, when a high voltage is applied so that the potential of the anode electrode 69 is higher than the potential of the cathode electrode 58, the n-type drift region 52
In A to 52C, a depletion layer effectively spreads from the p-type base region 94 and the adjacent p-type drift regions 53A to 53C, and is completely depleted. At the same time, p-type drift regions 53A-
In 53C, the depletion layer effectively spreads from the n-type base region 86 and the adjacent n-type drift regions 52A to 53C, and is completely depleted. As a result, drift regions 52A to 52C, 5D between p-type base region 94 and n-type base region 86 are formed.
The potential distributions of 3A to 53C are substantially equal potential distributions, and the electric field is substantially uniform over the entire drift regions 52A to 52C and 53A to 53C. Since the applied voltage can be increased until the electric field reaches about 3 MV / cm of the dielectric breakdown electric field of SiC, the withstand voltage can be increased. In the case of this embodiment, a high withstand voltage of 4500 V can be realized.

In controlling the supplied current, a high voltage is applied so that the potential of the anode electrode 69 becomes higher than the potential of the cathode electrode 58, and the gate current can be turned on by flowing a gate current from the gate electrode 40. It can be turned off by pulling it out. The resistance of the p-type base region 94 tends to slightly increase as the position is closer to the insulating substrate 51, and the shunt gate current tends to decrease. As a result, the anode electrode 6
9 and the cathode electrode 58 are about 1/1 of the conventional GTO.
5 can be reduced. In the case of this embodiment, the withstand voltage is 4500 V
Despite this, the on-resistance per unit area in the voltage range higher than the built-in voltage was 17 mΩcm ² , which was significantly reduced.

As described above, this embodiment has an effect that the on-resistance can be further greatly reduced while maintaining the breakdown voltage. This on-resistance can be further reduced as the number of stacked pairs of the n-type drift region and the p-type drift region is increased. However, if the number of layers is excessively increased, as described above,
, The current flowing through the drift region 52A on the substrate 51 side may not be effectively extracted at the time of turn-off. In such a case, p
The impurity concentration in the portion of the mold base region 94 near the substrate 51 may be slightly increased.

<< Eleventh Embodiment >> FIG. 14 is a sectional view of a segment of a SiC-MOS field effect thyristor of an eleventh embodiment of the semiconductor device of the present invention. On an SiC insulating substrate 61 having a thickness of about 320 μm, n-type drift regions
62E, the p-type drift regions 63A-63
Five pairs of an n-type drift region and a p-type drift region formed sandwiching E are stacked. The trenches 6A and 9A are provided at both ends of the drift regions 62A to 62E and 63A to 63E which are stacked so as to reach the insulating substrate 61. On the inner wall of one trench 9A, a p-type base region 94, an n-type emitter region 95, and a cathode electrode 58 are sequentially provided. An n-type base region 86, a p-type emitter region 87, and an anode electrode 69 are sequentially provided on the inner wall of the other trench 6A. A gate electrode 70 is formed on the surface of the uppermost p-type drift region 63E and on the ends of the n-type base region 86 and the end of the p-type emitter region 87 via the gate oxide film 11A. A protection film 45 such as a Si oxide film or a Si nitride film is provided for protection. Drift regions 62A to 63
In the case where the conductivity types of the E, emitter regions 87 and 95, and base regions 86 and 94 are reversed from those described above, the gate electrode 70 includes the p-type base region 94 and the n-type emitter region 9.
5 may be formed so as to face the end portion via the gate oxide film 11A. N-type and p-type drift regions 62A-6
2E and 63A to 63E have a thickness of about 0.8 μm, an impurity concentration of about 8 × 10 ¹⁶ cm ³ , and a length of about 75 μm.
Both the p-type and n-type base regions 94 and 86 have an impurity concentration of about 7 × 10 ¹⁷ cm ³ and a thickness of about 1.2 μm. n
And p-type emitter regions 95 and 87 have an impurity concentration of 1 ×
It is 10 ²⁰ cm ³ and the thickness is about 0.4 μm. The depth of each of the trenches 6A and 9A is about 10 μm.

In the SiC-MOS field effect thyristor of this embodiment, the n-type drift regions 62B to 62E are sandwiched between adjacent ones of the p-type drift regions 63A to 63E. The p-type drift region 63A is sandwiched between the n-type drift regions 62A and 62B. Thus, when a high voltage is applied so that the potential of the anode electrode 69 is higher than the potential of the cathode electrode 58, the p-type base regions 94 and p
The depletion layer effectively spreads from the mold drift regions 63A to 63E, and is completely depleted. Also, the p-type drift region 63
In A to 63E, the depletion layer effectively spreads from the n-type base region 86 and the n-type drift regions 62A to 62E, and is completely depleted. As a result, drift regions 62A to 62E and 63A to 63A to 62D between p-type base region 94 and n-type base region 86 are formed.
The potential distribution of 63E is substantially equal potential distribution, and the electric field is substantially uniform over the entire drift region. This electric field is S
Since the applied voltage can be increased until the breakdown electric field of iC reaches about 3 MV / cm, the withstand voltage can be increased.
In the case of the present embodiment, a high withstand voltage of 4700 V was realized.

In controlling the supplied current, a high voltage is applied so that the anode electrode 69 has a higher potential than the cathode electrode 58. In addition, a voltage is applied to the gate electrode 70 so that the potential is lower than the potential of the anode electrode 69. This voltage is applied to the n-type base region 8 under the gate electrode 70.
When the threshold voltage is equal to or higher than the threshold voltage of the surface of No. 6, a channel is formed on the surface of n-type base region 86 and holes flow from p-type emitter region 87 into p-type drift region 63E. When the holes reach the p-type base region 94, the n-type emitter region 9
Injection of electrons from No. 5 is promoted, and electrons flow first into the uppermost p-type drift region 63E. These electrons are supplied to an np-type emitter region 95, a p-type base region 94, an uppermost p-type drift region 63E and an n-type base region 86.
Turn on the n-transistor to promote the injection of holes from p-type emitter region 87 into n-type base region 86. This injection of holes turns on a pnp transistor composed of a p-type emitter region 87, an n-type base region 86, and a p-type drift region 63E, and finally turns on a pnpn thyristor including the uppermost p-type drift region 63E. I do. In this process, since the potential of the n-type drift region 62E below the uppermost p-type drift region 63E is higher than that of the uppermost p-type drift region 63E, the potential is injected from the n-type emitter region 95 into the p-type drift region 63E. Some of the electrons that have flowed into the n-type drift region 62E reach the n-type base region 86, where p
The injection of holes from the type emitter region 87 to the n-type base region 86 and the n-type drift region 62E is promoted. This gives p
Pnp composed of an n-type emitter region 87, an n-type base region 86, an n-type drift region 62E, and a p-type base region 94
When the transistor is turned on, a large amount of holes flow through the pnp transistor to promote injection of a large amount of electrons from the n-type emitter region 95. As a result, the npn transistor composed of the n-type emitter region 95, the p-type base region 94, the n-type drift region 62E, and the n-type base region 86 is turned on, and more holes are injected into the n-type base region 86. Will be promoted. This is because the pnp transistor and n
This causes a positive feedback amplification operation by the pn transistor, and finally the pnpn thyristor is turned on. In this process, since the potential of the third layer p-type drift region 63D is lower than that of the second layer n-type drift region 62E, the potential of holes injected from the p-type emitter region 87 into the n-type drift region 62E is reduced. A part flows through the p-type drift region 63D and reaches the p-type base region 94. This promotes the injection of electrons from the n-type emitter region 95 into the p-type base region 94 and the p-type drift region 63D, turning on the third-layer npn transistor, and then turning on the third-layer pnp transistor.
As a result, the third-layer pnppn thyristor composed of the third-layer npn transistor and the pnp transistor is turned on. Thus, the thyristors of the fourth, fifth, sixth, seventh, eighth, ninth, and tenth layers including the n-type and p-type drift regions 62D, 63C, 62C, 63B, 62B, 63A, and 62A are sequentially turned on. Eventually, the entire SiC-MOS field effect thyristor is turned on.

In the case of this embodiment, the on-resistance per unit area in a high voltage range equal to or higher than the built-in voltage is 11 mΩcm ² even though the withstand voltage can be increased to 4700 V.
And could be greatly reduced. Further, since the semiconductor device is a MOS gate type semiconductor device, the power consumption of the gate circuit including the gate electrode 70 can be significantly reduced as compared with the SiC-GTO of the tenth embodiment. As described above, the present embodiment has an effect that the on-resistance can be greatly reduced while keeping the breakdown voltage high, and the power consumption of the semiconductor device can be significantly reduced, and the power consumption of the gate drive circuit connected to the gate electrode 70 is also reduced. it can. The on-resistance can be reduced by increasing the number of stacked pairs of the n-type drift regions 62A to 62E and the p-type drift regions 63A to 63E.

As described above, the first to eleventh embodiments have been described in detail. However, the present invention covers a wider range of applications or derivative structures. For example, by connecting a large number of basic elements formed on the same substrate in parallel, a large current and a large capacity can be realized. Further, the SiC insulating substrate is not limited to the SiC substrate containing vanadium, but may be a sapphire insulating substrate, a gallium arsenide insulating substrate containing chromium, or the like. In each of the embodiments described above, the case of the device using Si and SiC has been described. However, the present invention is also effective for devices using other semiconductor materials such as diamond, gallium nitride, aluminum nitride, and zinc sulfide. . Although the inner walls of the trenches 6A and 9A in the above embodiments are nearly vertical, the inner wall may be formed in a mortar-like gently sloped groove. This facilitates the formation of the buried region and the electrode when the number of sets of the n-type and p-type drift layers is as large as 10 or more, which is advantageous for cost reduction and improvement in yield. In each of the above embodiments, the n-type region is defined as p
The configuration of the present invention can be applied to the case where the p-type region is replaced with the n-type region in the mold region.

The breakdown voltage of the semiconductor device of the present invention is affected by the difference in thickness between the p-type drift region and the n-type drift region and the difference in impurity concentration. Therefore, in order to effectively achieve the object of the present invention, the difference in thickness between the p-type drift region and the n-type drift region is ± 20% or less, and the difference in impurity concentration is ± 250%.
It is preferred that:

[0083]

As described in detail in each embodiment of the present invention, a semiconductor device is formed on an insulating wide gap semiconductor substrate, and a high voltage near a rated voltage is applied between a body region and a drain region. Thin p-type and n-type drifts that are completely depleted when applied are stacked. Thereby, even when the impurity concentration is increased, the p-type and n-type
The drift region can be completely depleted by the depletion layer extending from the junction formed by both the drift regions of the mold. As a result, the drift region has an equipotential distribution, that is, a constant electric field, and a high breakdown voltage can be realized. Since the impurity concentration is increased, the on-resistance can be reduced at the same time, and the local concentration of the electric field when a high voltage is applied is small and the maximum electric field is low, so that the reliability is improved.

Further, between the body region and the buffer region,
Alternatively, between the n-type base region and the p-type base region, a thin p-type and n-type bipolar drift region having a thickness such that when a high voltage near the rated voltage is applied, the two are completely depleted. Are laminated and provided. Thereby, even when the impurity concentration of both drift regions is high, the p-type and
Both drift regions can be completely depleted by a depletion layer extending from the junction formed by both n-type drift regions. As a result, an equipotential distribution, that is, a constant electric field is generated between the two, and a high breakdown voltage can be realized. Since the impurity concentration is high, the on-resistance is also low.
Furthermore, when a high voltage is applied, the local concentration of the electric field is reduced and the maximum electric field is low, so that the reliability is improved.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a first embodiment of a field effect transistor according to the present invention.

FIG. 2 is a graph showing the relationship between the breakdown voltage of the field effect transistor according to the first embodiment of the present invention and the impurity concentration of the drift region.

FIG. 3 is a graph showing the relationship between the withstand voltage and the thickness of the drift region of the field effect transistor according to the first embodiment of the present invention.

FIG. 4 is a sectional view showing a second embodiment of the field-effect transistor of the present invention.

FIG. 5 is a sectional view showing a third embodiment of the field-effect transistor of the present invention.

FIG. 6 is a sectional view showing another example of the third embodiment of the field effect transistor of the present invention.

FIG. 7 is a sectional view showing a fourth embodiment of the field-effect transistor of the present invention.

FIG. 8 is a sectional view showing a fifth embodiment of the field effect transistor of the present invention.

FIG. 9 is a sectional view showing a sixth embodiment of the field-effect transistor of the present invention.

FIG. 10 is a sectional view of a SiC-IGBT according to a seventh embodiment of the present invention.

FIG. 11 is a sectional view of an SiC-IGBT according to an eighth embodiment of the present invention.

FIG. 12 is a sectional view of a Si-IGBT according to a ninth embodiment of the present invention.

FIG. 13 is a sectional view of a SiC-GTO according to a tenth embodiment of the present invention.

FIG. 14 is a sectional view of an SiC-MOS thyristor according to an eleventh embodiment of the present invention.

FIG. 15 is a cross-sectional view of a conventional trench-type field-effect semiconductor device.

FIG. 16 is a sectional view of a conventional high breakdown voltage semiconductor device.

[Explanation of symbols]

Reference Signs List 1 insulating substrate 2 n-type drift region 3 p-type drift region 4 p-type body region 5 source region 6, 16 drain region 6A trench 7 source electrode 8 drain electrode 9, 19 oxide film 9A trench 10 gate electrode 11 surface protective film 12 p Drift region 14 p-type contact portion 22, 22A, 22B, 22C, 22D n-type drift region 23, 23A, 23B, 22C p-type drift region 32A to 32E n-type drift region 33 p-type drift region 33A to 33D p-type drift Region 34 body region 37 source electrode 39 collector electrode 40 gate electrode 41 Si substrate 42A to 42C n-type drift region 43A to 43C p-type drift region 51 insulating substrate 52A to 52C n-type drift region 53A to 53C p-type drift region 55 emitter region 58 Sword electrodes 62A to 62E n-type drift region 63A to 63E p-type drift region 66 buffer region 68 gate electrode 69 anode electrode 70 gate electrode 77 collector region 86 n-type base region 87 p-type emitter region 88 emitter electrode 94 p-type base region 95 n-type emitter region 101 drain region 102 drift region 103 body region 104 source region 105 gate insulating film 106 gate electrode 107 source electrode 108 drain electrode 110 recess

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/78 652G 653A 655A

Claims (39)

[Claims] 1. A first drift region of at least one first conductivity type formed on a high-resistance wide-gap semiconductor substrate; and a first drift region formed on the first drift region. At least one second conductivity type second drift region having substantially the same thickness and the same impurity concentration as the first conductivity type formed so as to be in contact with both the first and second drift regions; A buried region, a first electrode formed in the buried region, at least one first electrode formed to be separated from the buried region by a predetermined distance and to be in contact with at least one of the first and second drift regions A second conductivity type body region, a first conductivity type region formed in a part of the body region, a second electrode provided in the body region and the first conductivity type region, and the first conductivity type body region. Drift area and And a control electrode formed in the body region, wherein a thickness of the first and second drift regions is lower than a rated voltage when applied between the first electrode and the second electrode. A wide-gap semiconductor device, wherein the first and second drift regions are selected to be substantially complete depletion layers. 2. The method according to claim 1, wherein the control electrode is connected to the first electrode via an insulating film.
2. The wide-gap semiconductor device according to claim 1, wherein said wide-gap semiconductor device is provided so as to contact said drift region, said body region, and said first conductivity type region. 3. The wide gap semiconductor device according to claim 1, further comprising a third drift region provided between said substrate and said first drift region and in contact with said buried region. 4. The wide gap semiconductor device according to claim 3, wherein the thickness of the first drift region is larger than the thicknesses of the second drift region and the third drift region. 5. The wide gap semiconductor device according to claim 1, wherein the buried region is in contact with a substrate. 6. A first drift region of at least one first conductivity type formed on a substrate of a high-resistance wide gap semiconductor, and the first drift region formed on the first drift region. A second drift region of at least one second conductivity type having substantially the same thickness and the same impurity concentration as the first, the substrate, and the first drift region formed so as to be in contact with the first and second drift regions; A buried region of conductivity type, a first electrode formed in the buried region, at least a predetermined distance from the buried region and at least one formed to be in contact with at least one of the first and second drift regions. One second conductivity type body region, a first conductivity type region formed in a part of the body region, a second electrode provided in the body region and the first conductivity type region, and Substrate, 1st A control electrode formed in the drift region and the body region via an insulating film, wherein a thickness of the first and second drift regions is lower than a rated voltage between the first electrode and the second electrode. Wherein the first and second drift regions are selected so as to become a substantially complete depletion layer when voltage is applied. 7. The control electrode according to claim 1, wherein the control electrode is formed on an inner wall of a trench reaching the substrate through the first and second drift regions via an insulating film.
Or the wide gap semiconductor device according to 6. 8. The wide gap semiconductor device according to claim 1, wherein said body region is formed so as to be in contact with said first and second drift regions. 9. A plurality of sets of a first drift region of a first conductivity type and a second drift region of a second conductivity type formed on a substrate of a high-resistance wide gap semiconductor; A first conductivity type buried region formed on an inner wall surface of a first trench reaching the substrate through the plurality of sets of the first and second drift regions; formed in the buried region; A first electrode, a second conductivity type body region formed in an uppermost drift region of the plurality of sets of first and second drift regions, and a first conductivity formed in a part of the body region. The plurality of sets of the first and second drift regions, the body region, and the first conductivity type region provided at a position separated by a predetermined distance from the first trench. An insulating film formed on an inner wall surface of the second trench reaching the substrate, A control electrode provided on the inner wall surface of the second trench via the insulating film; and a second control electrode provided on the region and the body region.
Wide-gap semiconductor device provided with the electrodes of FIG. 10. The first and second drift regions when a thickness of the first and second drift regions is lower than a rated voltage between the first and second electrodes. 10. The wide-gap semiconductor device according to claim 9, wherein is selected so as to completely form a depletion layer. 11. In the plurality of pairs of the first drift region and the second drift region, a thickness of each drift region gradually decreases as a portion closer to the substrate becomes thicker and further away from the substrate. The wide gap semiconductor device according to claim 9, wherein 12. A first drift region of a second conductivity type formed on a substrate of a high-resistance wide gap semiconductor, substantially the same as the first drift region formed on the first drift region. A second drift region of the first conductivity type having the same thickness and the same impurity concentration as above, a buried region of the first conductivity type formed in contact with the substrate, and the first and second drift regions, A first electrode formed in the buried region; a second conductivity type body region formed to be separated from the buried region by a predetermined distance and to be in contact with the substrate and the first and second drift regions; A first conductivity type region formed in a part of the body region, a second electrode provided in the region and the body region, and a control electrode provided in the body region via an insulating film; And the second drift region Is selected such that when a voltage lower than the rated voltage is applied between the first electrode and the second electrode, the first and second drift regions become substantially complete depletion layers. A wide gap semiconductor device characterized by the following. 13. A first drift region of at least one first conductivity type formed on a high-resistance wide-gap semiconductor substrate, wherein the first drift region is formed on the first drift region. At least one second drift region of the second conductivity type having substantially the same thickness and the same impurity concentration as the first, and the first conductivity type buried formed in contact with the first and second drift regions. A first electrode formed in the buried region, at least one electrode formed in the first drift region so as to be separated from the buried region by a predetermined distance and to be in contact with the first and second drift regions Two second conductivity type body regions, a first conductivity type region formed in a part of the body region, a second electrode provided in the region, and a second body region of the first drift region And the territory A control electrode provided on the region with an insulating film interposed therebetween, wherein the thickness of the first and second drift regions is reduced by applying a voltage lower than a rated voltage between the first electrode and the second electrode. A wide-gap semiconductor device, wherein the first and second drift regions are selected to be substantially complete depletion layers. 14. A low-resistance second semiconductor formed on a wide-gap semiconductor substrate using a high-resistance first-type material.
At least one first drift region of the first conductivity type using a material of the type described above, and formed on the first drift region and having substantially the same thickness and the same impurity concentration as the first drift region. At least one second drift region of a second conductivity type using a second type of material having: a buried region of a first conductivity type formed in contact with the first and second drift regions; A first electrode formed in the buried region, at least one electrode formed at a predetermined distance from the buried region and in contact with the first and second drift regions;
Two second conductivity type body regions, a first conductivity type region formed in a part of the body region, a second electrode provided in the region, and the first drift through the body region A control electrode provided on an inner wall surface of the trench reaching the region via an insulating film, wherein a thickness of the first and second drift regions is lower than a rated voltage between the first electrode and the second electrode. A wide-gap semiconductor device, wherein the first and second drift regions are selected to be substantially complete depletion layers when a voltage is applied. 15. The material of the first type is one material selected from SiC containing vanadium, sapphire, and gallium arsenide containing chromium, and the second type of material is SiC, diamond. 15. The wide-gap semiconductor device according to claim 14, wherein the wide-gap semiconductor device is a material selected from the group consisting of gallium nitride, aluminum nitride, and zinc sulfide. 16. The material of the wide gap semiconductor substrate is one material selected from SiC containing vanadium, sapphire and gallium arsenide containing chromium, and the first and second drift regions and the body region are provided. Is selected from SiC, diamond, gallium nitride, aluminum nitride and zinc sulfide.
The wide gap semiconductor device according to claim 1, 6, 9, 12, or 13, which is a kind of material. 17. A first drift region of at least one first conductivity type formed on a high-resistance wide-gap semiconductor substrate, and the first drift region formed on the first drift region. At least one second conductivity type second drift region having substantially the same thickness and the same impurity concentration as the first conductivity type formed so as to be in contact with both the first and second drift regions; A buried region, a first electrode formed in the buried region, at least one first electrode formed to be separated from the buried region by a predetermined distance and to be in contact with at least one of the first and second drift regions A second conductivity type body region, a first conductivity type region formed in a part of the body region, a second electrode provided in the body region and the first conductivity type region, and the first conductivity type body region. Drift area And a control electrode formed in the body region, wherein a thickness of the first and second drift regions is applied when a voltage lower than a rated voltage is applied between the first electrode and the second electrode. A semiconductor device, wherein the first and second drift regions are selected so as to be substantially complete depletion layers. 18. The semiconductor device according to claim 17, wherein the control electrode is provided so as to contact the first drift region, the body region, and the first conductivity type region via an insulating film. Semiconductor device. 19. The semiconductor device according to claim 17, further comprising a third drift region provided between said substrate and said first drift region and in contact with said buried region. 20. The semiconductor device according to claim 19, wherein the thickness of the first drift region is larger than the thicknesses of the second drift region and the third drift region. 21. The semiconductor device according to claim 17, wherein said buried region is in contact with a substrate. 22. A first drift region of at least one first conductivity type formed on a substrate of a high-resistance wide gap semiconductor, formed on the first drift region.
At least one second conductivity type second drift region having substantially the same thickness and the same impurity concentration as the first drift region, in contact with the substrate, and the first and second drift regions; A first conductivity type buried region formed as described above, a first electrode formed in the buried region, a predetermined distance from the buried region and at least one of the first and second drift regions. At least one second conductive type body region formed so as to be in contact with the first conductive type region formed in a part of the body region; And a control electrode formed on the substrate, the first drift region and the body region via an insulating film, wherein the thicknesses of the first and second drift regions are equal to the first electrode and the second drift region. Rated voltage between two electrodes Upon application of a low voltage Ri, semiconductor device, wherein the first and second drift regions is selected such that substantially complete depletion. 23. The control electrode according to claim 17, wherein the control electrode is formed on an inner wall of a trench reaching the substrate through the first and second drift regions via an insulating film. Semiconductor device. 24. The method according to claim 24, wherein the body region is formed by the first and second bodies.
18. The semiconductor device according to claim 17, wherein said semiconductor device is formed so as to be in contact with said drift region. 25. A plurality of sets of a first drift region of a first conductivity type and a second drift region of a second conductivity type, formed on a substrate of a high-resistance wide-gap semiconductor; A first conductivity type buried region formed on an inner wall surface of a first trench reaching the substrate through the plurality of sets of the first and second drift regions; formed in the buried region; A first electrode, a second conductivity type body region formed in an uppermost drift region of the plurality of sets of first and second drift regions, and a first conductivity formed in a part of the body region. The plurality of sets of the first and second drift regions, the body region, and the first conductivity type region provided at a position separated by a predetermined distance from the first trench. An insulating film formed on the inner wall surface of the second trench reaching the substrate; A control electrode provided on the inner wall surface of the second trench via the insulating film, and a second electrode provided on the region and the body region.
A semiconductor device provided with the electrodes described above. 26. The first and second drift regions when a thickness of the first and second drift regions is lower than a rated voltage between the first electrode and the second electrode. 26. The semiconductor device according to claim 25, wherein is selected to be a complete depletion layer. 27. In the plurality of pairs of the first drift region and the second drift region, a thickness of each drift region gradually decreases as a portion closer to the substrate becomes thicker and further away from the substrate. 26. The semiconductor device according to claim 25, wherein: 28. A first drift region of at least one second conductivity type formed on a high-resistance wide-gap semiconductor substrate, and the first drift region formed on the first drift region. At least one second drift region of the first conductivity type having substantially the same thickness and the same impurity concentration as the first conductive type formed in contact with the substrate, and the first and second drift regions; A buried region of a mold, a first electrode formed in the buried region, at least one formed at a predetermined distance from the buried region and in contact with the substrate and the first and second drift regions A second conductivity type body region, a first conductivity type region formed in part of the body region, a second electrode provided in the region and the body region, and a second electrode provided in the body region via an insulating film System A control electrode, wherein when a voltage lower than a rated voltage is applied between the first electrode and the second electrode, the first and second drift regions have thicknesses of the first and second drift regions. Is selected to be a substantially complete depletion layer. 29. at least one first drift region of a first conductivity type formed on a high-resistance wide-gap semiconductor substrate; and the first drift region formed on the first drift region. At least one second conductivity type second drift region having substantially the same thickness and the same impurity concentration as the first conductivity type buried formed in contact with the first and second drift regions A first electrode formed in the buried region, at least one electrode formed in the first drift region so as to be separated from the buried region by a predetermined distance and to be in contact with the first and second drift regions Two second conductivity type body regions, a first conductivity type region formed in a portion of the body region, a second electrode provided in the region, and a second body region of the first drift region And the territory A control electrode provided on the region via an insulating film, wherein the thickness of the first and second drift regions is reduced by applying a voltage lower than the rated voltage between the first electrode and the second electrode. A semiconductor device wherein the first and second drift regions are selected to be substantially complete depletion layers. 30. A low-resistance second semiconductor formed on a wide-gap semiconductor substrate using a high-resistance first-type material.
At least one first drift region of the first conductivity type using a material of the type described above, and formed on the first drift region and having substantially the same thickness and the same impurity concentration as the first drift region. At least one second drift region of a second conductivity type using a second type of material having: a buried region of a first conductivity type formed in contact with the first and second drift regions; A first electrode formed in the buried region, at least one electrode formed at a predetermined distance from the buried region and in contact with the first and second drift regions;
Two second conductivity type body regions, a first conductivity type region formed in a part of the body region, a second electrode provided in the region, and the first drift through the body region A control electrode provided on an inner wall surface of the trench reaching the region via an insulating film, wherein a thickness of the first and second drift regions is lower than a rated voltage between the first electrode and the second electrode. A semiconductor device, wherein the first and second drift regions are selected so as to become a substantially complete depletion layer when a voltage is applied. 31. The first type of material is one selected from SiC containing vanadium, sapphire, and gallium arsenide containing chromium, and the second type of material is SiC, diamond. 31. The semiconductor device according to claim 30, wherein the semiconductor device is one material selected from the group consisting of gallium nitride, aluminum nitride, and zinc sulfide. 32. The material of the wide gap semiconductor substrate is one material selected from SiC containing vanadium, sapphire and gallium arsenide containing chromium, and the first and second drift regions and the body region Is selected from SiC, diamond, gallium nitride, aluminum nitride and zinc sulfide.
30. A material of claim 17, 22, 25, 28 or 29.
13. The semiconductor device according to claim 1. 33. at least one first conductivity type first drift region formed on a high resistance wide gap semiconductor substrate; at least one second drift region formed on a portion of the first drift region; A second drift region having a conductivity type of: a second drift region formed in a portion above the first drift region;
At least one body region of the second conductivity type having an impurity concentration equal to or higher than the impurity concentration of the second drift region of the conductivity type, and a region of the first conductivity type having a high impurity concentration formed in the body region. At least one first conductive type first formed in contact with the first drift region and the second drift region and having a higher impurity concentration than the first drift region and the second drift region; A buried region, formed in contact with the first buried region of the first conductivity type;
At least one second buried region of a second conductivity type having a high impurity concentration, a first electrode formed in the region of the first conductivity type, a second buried region of the second conductivity type And a control electrode facing the first drift region, the body region, and the first region via an insulating film, wherein the first drift region And the thickness of the second drift region are substantially equal, each thickness is smaller than the respective length, and when a voltage close to the rated voltage is applied between the first electrode and the second electrode, A wide-gap semiconductor device, wherein the thicknesses of the first and second drift regions are selected such that the first and second drift regions are substantially depletion layers. 34. A plurality of sets of a first drift region of a first conductivity type and a second drift region of a second conductivity type formed on a substrate of a high-resistance wide gap semiconductor. A plurality of sets of at least one first buried region of a first conductivity type formed on an inner wall surface of a first trench reaching the substrate through the first and second drift regions; At least one second conductivity type second buried region formed in contact with the buried region, a first electrode formed in the second buried region, the plurality of sets of first and second sets At least one body region of the second conductivity type formed in contact with the uppermost drift region of the drift region; a region of the first conductivity type formed in a part of the body region; a predetermined distance from the first trench , The plurality of sets of the first and An insulating film formed on an inner wall surface of a second trench reaching the substrate through the drift region, the body region, and the first conductivity type region; and an insulating film formed on an inner wall surface of the second trench. And a second control electrode provided in the region and the body region.
A semiconductor device provided with the electrodes described above. 35. A plurality of sets of a first drift region of a first conductivity type and a second drift region of a second conductivity type formed on a substrate via an insulating film. At least one first buried region of a first conductivity type formed on an inner wall surface of a first trench reaching the substrate through the first and second drift regions; At least one second buried region of the second conductivity type formed in contact with the buried region; a first electrode formed in the second buried region; the plurality of sets of first and second drift regions At least one second conductivity type body region formed in contact with the uppermost drift region, a first conductivity type region formed in a part of the body region, and a predetermined distance from the first trench The plurality of sets of the first and second drift regions provided at different positions An insulating film formed on an inner wall surface of a second trench reaching the substrate through the body region and the first conductivity type region; and an insulating film provided on an inner wall surface of the second trench via the insulating film. A control electrode, and a second electrode provided in the region and the body region.
A semiconductor device provided with the electrodes described above. 36. A plurality of sets of a first drift region of a first conductivity type and a second drift region of a second conductivity type formed on a substrate of a high-resistance wide gap semiconductor; The plurality of sets of at least one first conductivity type first buried region formed on an inner wall surface of a first trench reaching the substrate through the first and second drift regions; At least one second buried region of the second conductivity type formed in contact with one buried region; a first electrode formed in the second buried region; a plurality of first and second sets of the plurality of sets. A second conductivity type contact portion formed in the uppermost drift region of the drift region, formed at a position separated by a predetermined distance from the first trench, and the plurality of sets of the first and second drift regions. ,
At least one base region of the second conductivity type formed on the inner wall surface of the second trench reaching the substrate through the contact portion; at least one emitter region of the first conductivity type provided in the base region A semiconductor device comprising: a second electrode provided in the emitter region; and a third electrode provided in the contact portion. 37. A plurality of sets of a first drift region of a first conductivity type and a second drift region of a second conductivity type formed on a substrate of a high-resistance wide-gap semiconductor; The plurality of sets of at least one first conductivity type first buried region formed on an inner wall surface of a first trench reaching the substrate through the first and second drift regions; At least one second buried region of the second conductivity type formed in contact with one buried region, a first electrode formed in the second buried region, a predetermined distance from the first trench At least one base region of the second conductivity type formed at a remote position and formed on an inner wall surface of a second trench reaching the substrate through the plurality of sets of the first and second drift regions; At least one first conductive layer provided in the base region An emitter region, a second electrode provided in the base region in the second trench, and a third electrode opposed to the first buried region and the second buried region via an insulating film; A semiconductor device comprising: 38. at least one set formed on a substrate,
A first set of a semiconductor region of a first conductivity type and a semiconductor region of a second conductivity type; at least one set of semiconductor regions of the first conductivity type in contact with one end of the first set of semiconductor regions; And a second set of semiconductor regions of the second conductivity type, at least one set of semiconductor regions of the first conductivity type and the second conductivity type which are in contact with the other end of the first set of semiconductor regions. A third set of semiconductor regions, and a control electrode for applying an electric field to the third set of semiconductor regions, such that a potential of the second set of semiconductor regions is higher than a potential of the third set of semiconductor regions. When a voltage is applied between them,
A voltage is applied between the first set of semiconductor regions so that the entire region is depleted, and the potential of the second set of semiconductor regions is higher than the potential of the third set of semiconductor regions. When a voltage equal to or higher than the threshold value is applied, electrons flow out of the third set of semiconductor regions, flow into the second set of semiconductor regions through the first set of semiconductor regions, and Holes flow out of the semiconductor region, flow into the third set of semiconductor regions via the first set of semiconductor regions, and
The semiconductor device according to claim 1, wherein the shape and thickness of the first set of semiconductor regions are selected so that both electrons and holes are present in the set of semiconductor regions. 39. The semiconductor device according to claim 1, wherein a plurality of the semiconductor devices are formed on one substrate, and the same type of electrodes of each semiconductor device are connected in common.
13, 14, 17, 22, 25, 28, 29, 30, 3
39. The semiconductor device according to 3, 34, 35, 36, 37 or 38.