JP2001044420A - Field-effect transistor and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a field-effect transistor with a gate insulating film thickness equal to or below a specific value in terms of Si oxide film-converted film thickness by forming a laminated film of a silicon nitride film and tungsten- titanium mixed oxide or tungsten-zirconium mixed oxide as a gate insulating film on a single crystal silicon substrate. SOLUTION: An element isolation region 210 of STI structure is formed on a n-type single crystal silicon substrate 201. A silicon nitride film 204, 1 nm or so in film thickness, is formed on a channel region 203, and a WTO film (Ti/(W+Ti)=0.2) 205, 12 nm or so in film thickness, is formed thereon. A gate electrode 206 is formed on the metal oxide insulating film 205 through self alignment to source-drain regions 202. Source-drain electrodes 207, electrically connected with the respective source-drain regions 202 through contact holes formed in a layer insulating film 208, are formed. The silicon film- converted film thickness of the gate insulating film is not larger than 1.0 nm.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a field effect transistor and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, in order to realize a higher integration of a semiconductor transistor, an equivalent silicon oxide film thickness is 1 nm or less, and a gate leakage current is reduced to a gate voltage of 1 V.
Sometimes a gate insulating film having a current of 1 mA / cm ² or less is required. At present, a silicon oxide film is used as a gate insulating film.
When V is applied, the direct tunnel current alone is 10 A / c.
can not be used because more than m ^2. In addition, a silicon oxide film having a thickness of 1 nm or less is formed on a silicon wafer with good controllability.
Moreover, it is extremely difficult to form a uniform film.

Therefore, attempts have been made to reduce the equivalent oxide thickness of the gate insulating film by using a high dielectric thin film such as a metal oxide instead of the silicon oxide film as the gate insulating film. In attempts to date, the metal oxide insulating film has been formed immediately above the channel (Si), through a silicon oxide film, or through a silicon nitride film.

An MDS (Metal-Dielectric) in which a metal oxide insulating film is formed immediately above a channel (Si)
-Semiconductor-FET-Field (Field)
In (Effect-Transistor), during the formation of the metal oxide insulating film or during the heat treatment after the formation of the metal oxide insulating film (anneal in oxygen or source-drain activation for improving the metal oxide insulating film). Interdiffusion occurs at the interface of the silicon-metal oxide insulating film. That is, metal diffuses into the channel and silicon diffuses into the metal oxide. The former causes deterioration of device characteristics of the transistor. The latter causes a decrease in the crystallinity of the metal oxide and lowers its dielectric constant. Furthermore, after the heat treatment, a silicon oxide film is formed between the metal oxide insulating film and the channel (Si), and a low dielectric constant layer is inserted at the interface between the channel and the gate insulator. For the above reasons, it is difficult to form a transistor having a gate insulating film thickness of 1 nm or less in terms of a silicon oxide film with this structure.

An MDIS (Metal-Die) having a metal oxide insulating film formed on a channel via a silicon oxide film.
Electric-Insulator-Semicon
duct) -FET, the above-mentioned channel (Si)
Interdiffusion is suppressed as compared with an MDS-FET in which a metal oxide insulating film is formed directly above. However, during the formation of the metal oxide insulating film or after the heat treatment after the formation of the metal oxide insulating film (annealing in oxygen or source-drain activation for improving the metal oxide insulating film), the metal oxide insulating film Then, the thickness of the silicon oxide film at the channel (Si) interface increases. It is difficult to control the thickness of the silicon oxide film after the heat treatment to 1 nm or less with good controllability. For the above reasons, it is difficult to form a transistor having a gate insulating film thickness of 1 nm or less with this structure.

An MDIS-FET in which a metal oxide insulating film is formed directly above a channel (Si) via a silicon nitride film
In the above, due to the dense structure of the silicon nitride film, the above-mentioned interdiffusion is suppressed. Further, due to the oxidation resistance of the silicon nitride film, formation of the silicon oxide film at the interface between the channel and the gate insulating film is suppressed. For this reason, the MD capable of operating well
It is considered that an IS-FET can be realized.

When a metal oxide is formed as a gate insulator, the substrate is not damaged, low-temperature film formation is possible,
In view of the good step coverage, a vapor phase growth method using an organometallic material gas is considered promising. Furthermore, the film thickness-
Considering the compositional uniformity, low-pressure metalorganic vapor phase epitaxy (LP-MOCVD) is considered the most promising.

When the source-drain activation or the oxygen annealing of the metal oxide is performed after the formation of the metal oxide,
Depending on the heat treatment conditions, there is a problem that the above-mentioned interdiffusion-oxide of silicon nitride film-silicon oxide film is formed at the silicon nitride film / silicon interface.

In order to realize further higher integration of a semiconductor transistor, a gate insulating film having an equivalent Si oxide film thickness of 1 nm or less and a gate leak current of 1 mA / cm ² or less at a gate voltage of 1 V is required. . To realize this, it is promising to use a stacked film of a silicon nitride film and a metal oxide insulating film as a gate insulating film, but there are the following problems.

The first problem is a leak characteristic of the metal oxide insulating film. In order to satisfy the above leak characteristics, the leak current density when 1 V is applied to a high dielectric thin film having a silicon oxide equivalent film thickness of 1 nm needs to be 1 mA / cm ² or less. However, Al ₂ O ₃ , Zr
All of the metal oxide insulating films such as O ₂ , Bi ₂ O ₃ , Ta ₂ O ₅ , and TiO ₂ do not satisfy the leak characteristics.

The second problem is that the silicon nitride film is
Is oxidized during film formation, and the dielectric constant of the silicon nitride film decreases.
Is Rukoto. Barrier to silicon nitride metal
In order to ensure performance, a film thickness of at least 0.8 nm is required.
Yes, assuming that the silicon nitride film is not oxidized at all
The equivalent silicon oxide film thickness is 0.45 nm.
You. Therefore, the equivalent silicon oxide film thickness of the gate insulating film is
1 nm or less, and silicon of the metal oxide insulating film
In order to secure the equivalent oxide thickness of 0.5 nm or more,
Oxidation of recon nitride film must be kept within 10% oxygen concentration
There is. At this time, a silicon nitride film having a thickness of 0.8 nm is induced.
The electric conductivity is about 6, and the silicon equivalent film thickness is 0.5 nm.
Gold deposited by LP-MOCVD method to date
Group oxides include tantalum pentoxide and titanium oxide
However, in order to ensure the insulating properties of metal oxide,
The temperature must be raised to 500 ° C. or higher. At this time, Silico
The oxygen concentration in the nitrided film becomes 10% or more. 500 ° C or less
The substrate temperature above is required only for the organometallic material used.
Since the decomposition temperature is 200 ° C or higher, the raw material gas is completely
Decomposition requires a temperature of 500 ° C or higher.
is there. If the substrate temperature is below 500 ° C, the deposited metal
Carbon, nitrogen, etc. contained in organometallic materials remain in oxides
I do. For example, Journal-of-Materials-Chem
Stream 8 Volume 1773 (Journal of
Materials Chemistry Vol. 8
(1998) P.A. According to 1773), titanium oxide is
Ti (OPr ⁱ)₃(OCH₂CH₂(NMe₂))so
When depositing, if the substrate temperature is 450 ° C., the deposited film
2.9% of carbon is detected in it. Also, Japani
Home-Journal-of-Applied-Physics 3
0 volume L1974 page (Japanese Journal
al of Applied Physics Vo
l. 30 (1991) p. According to L1974), oxidation
Tantalum is replaced with pentadimethylamino tantalum (Ta (N
(CH₃)₂)₅), The substrate temperature is 450 ° C.
Then, 4.0% of carbon is detected in the deposited film.
ing. On the other hand, electro-chemical and solid
State Letter 1 Volume 178 Pages (Electroc
chemical and Solid-State L
letters Vol. 1 (1998) p. 178)
Is a silicon oxynitride having a thickness of 0.8 nm and an oxygen concentration of 9.6%.
Film (Si₃N_4-xO_x x = 0.67)
Tantalum pentoxide using dimethylamino tantalum and oxygen
Deposited at a substrate temperature of 520 ° C.
The amount of oxygen in the silicon oxynitride film after stacking was determined by SIMS.
The number has increased to about 40%. 10% increase in oxygen concentration
It is much better. Therefore, conventional organic source gas and
And substrate temperature, the thickness of the gate insulating film is
It is very difficult to make the equivalent film thickness 1 nm.

The third problem is that after the metal oxide film is formed on the silicon nitride film, there are heat treatments for source-drain activation and metal oxide oxygen annealing. The point is that formation of a silicon oxide film at the oxide-silicon nitride film / silicon interface of the nitride film occurs. Accordingly, a heat treatment condition capable of suppressing the formation of the interdiffusion-oxidation of the silicon nitride film-silicon oxide film, activating the source-drain, compensating for oxygen deficiency of the metal oxide and removing impurities in the metal oxide is found. There is a need.

[0013]

SUMMARY OF THE INVENTION An object of the present invention is to improve the above-mentioned disadvantages of the prior art, and in particular, a novel field effect transistor having a gate insulating film thickness of 1 nm or less in terms of Si oxide film and a method of manufacturing the same. Is provided.

[0014]

SUMMARY OF THE INVENTION The present invention basically employs the following technical configuration to achieve the above object.

That is, in a first embodiment of the field effect transistor according to the present invention, a laminated film of a silicon nitride film and a tungsten-titanium mixed oxide or a tungsten-zirconium mixed oxide is formed as a gate insulating film on a single crystal silicon substrate. It is characterized by being provided,
In a second aspect, the gate electrode provided on the laminated film is formed of a noble metal Ir, Pt, Au, Ag, Ru, Os, a high melting point metal Co, a conductive oxide RuO ₂ , RhO ₂ , OsO.
₂ , IrO ₂ , ReO ₂ , ReO ₃ , MoO ₂ , SrR
Any one of uO ₃ , an alloy of each of these materials, or a structure in which each of the above materials is formed in a plurality of layers.

A first aspect of the method for manufacturing a field effect transistor according to the present invention is a first step of forming a silicon nitride film on a single crystal silicon substrate, and a step of forming a hexagonal gas as a tungsten source gas on the silicon nitride film. Second Step of Forming Tungsten-Titanium Mixed Oxide or Tungsten-Zirconium Mixed Metal Oxide Using Organometallic Material Gas Containing Dimethylaminoditungsten (W ₂ (N (CH ₃ ) ₂ ) ₆ ) and Oxidizing Gas A third step of forming a conductive film on the metal oxide, a fourth step of patterning the metal oxide and the conductive film to form a gate insulating film and a gate electrode, Using the film and the gate electrode as an ion implantation mask, impurity ions are implanted into the diffusion layer in a self-aligned manner with respect to the gate insulating film and the gate electrode. A fifth step, a sixth step of activating the impurities by heat treatment to form a source-drain region, and a seventh step of oxygen annealing. Means that the substrate temperature in the second step is 350 ° C. or more and 400 ° C. or less;
The oxygen annealing temperature in the step is characterized by being 350 ° C. or more and 400 ° C. or less, and the third aspect is that the gate electrode is made of a noble metal Ir, Pt, Au, A
g, Ru, Os, refractory metal Co, conductive oxide RuO
₂ , RhO ₂ , OsO ₂ , IrO ₂ , ReO ₂ , ReO
₃ , MoO ₂ , SrRuO ₃ , or an alloy of each of these materials, or a material in which each of the above materials is formed in a plurality of layers. In an embodiment, the oxidizing gas includes a nitrogen dioxide gas.

The WO ₃ crystal has a high dielectric constant (about 2000 in bulk value), but has a very large leakage current (resistivity in bulk is 1 kΩcm) and the conduction band bottom is lower than the silicon conduction band bottom. And cannot be used as it is as a gate insulating film. WO ₃ has a high dielectric constant because
This is because having a structure in which disconnect the A site of a perovskite structure ABO _3. The large leak current is due to the formation of a large amount of oxygen defects when crystallized.

The present inventor has proposed that WO ₃ be made of titanium oxide (TiO 2).
₂ ) or the addition of zircon oxide (ZrO ₂ ) reduces the leakage current density while keeping the dielectric constant high, and reduces the energy band so that the top of its valence band is lower than the top of the valence band of silicon and its conduction band is lower. Can be improved to be higher than the top of the conduction band of silicon. This is for the following reason.

[0019] The addition of titanium oxide WO ₃ (TiO ₂₎ or zirconium oxide (ZrO _2), the addition amount is below a certain value, ^{W 6+} ions in WO ₃ is replaced by ^{Ti 4+} ions, ^{Zr 4+} ions Will be. This is because the 6-coordinate ionic radius of the substituted ion is close to the 6-coordinate W ^{6 +} ionic radius of 0.060 nm. The six-coordinate Ti ⁴⁺ ion radius in titanium oxide is 0.061 nm, and the six-coordinate Zr ⁴⁺ ion radius in zircon oxide is 0.072 nm.
nm.

The reason why the dielectric constant is maintained high even when the substitution occurs is that the ionic radius of the substituted ion is close to the ionic radius of W ⁶ +, so that the crystallinity of WO ₃ is not significantly affected.

The reason that the substitution reduces the leakage is that holes are introduced because both Ti ⁴⁺ ions and Zr ⁴⁺ ions are tetravalent ions, and this results in WO.
_This is for canceling out the charge carrier electrons in ₃ .

With this substitution, the energy band is improved so that the top of its valence band is lower than the top of the valence band of silicon and the bottom of the conduction band is higher than the bottom of the conduction band of silicon. The reason is that the energy band approaches that of the substituted ion when the crystallinity is hardly affected by the substitution.

When forming a semiconductor transistor by the method described in the manufacturing method according to the first aspect, the present inventor uses hexadimethylaminoditungsten (W ₂ (N (CH ₃ ) ₂ )) as a source gas for tungsten. ₆ ), carbon remaining in the film even when the substrate temperature is set to 350 ° C.,
It has been found that the amount of nitrogen can be greatly reduced as compared with metal oxides such as tantalum pentoxide and titanium oxide formed by LP-MOCVD. This is due to the fact that the decomposition temperature of hexadimethylaminoditungsten is 170 ° C., which is 30 ° C. or more lower than the organometallic gas used for depositing a conventional metal oxide. When a metal oxide having a tungsten-titanium ratio of 4: 1 is formed, the carbon concentration in the film at a substrate temperature of 350 ° C. is 1.9%. Further, nitrogen was not detected. Japanese-Journal of Applied-Physics, Vol. 30, p. 1974 (Japanese Journal of Ap)
Plied Physics Vol. 30 (199
1) P.I. According to 1974), tantalum pentoxide is converted to pentadimethylamino tantalum (Ta (N
When deposited using (CH ₃ ) ₂ ) ₅ ), the amount of carbon is 7.5%, the amount of nitrogen is 2.0%, and Journal of Materials Chemistry, Vol. 8, p. 1773 (Journal of Japan) Materials Ch
emistryVol. 8 (1998) p. 1773)
According to the above, at a substrate temperature of 350 ° C., titanium oxide is converted to Ti (OP
^{_{r i) 3 (OCH 2 CH}} 2 (NMe 2)) 7.7% of carbon in deposited films in is detected. Therefore, when hexadimethylaminoditungsten is used, the carbon concentration in the film is reduced to about one-fourth as compared with the conventional case.

The inventor of the present invention used hexadimethylaminoditungsten as a tungsten raw material when depositing a metal oxide containing tungsten as a main component on a silicon nitride film having a thickness of 1 nm or less and performing oxygen annealing. It has been found that, when both the substrate temperature and the oxygen annealing temperature are 350 ° C. or more and 400 ° C. or less, the oxidation of the interdiffusion-silicon nitride film can be significantly suppressed without deteriorating the insulating properties of the metal oxide. When the above substrate temperature-oxygen annealing temperature is used, the oxygen concentration in the silicon nitride film is 10% or less, and the dielectric constant of the nitride film can be 6 or more.
This is because by using hexadimethylaminoditungsten as a tungsten raw material, it was possible to lower the substrate temperature during deposition-oxygen annealing temperature without deteriorating the insulating properties of the metal oxide. Therefore, according to the above method, it is possible to realize a field effect transistor having a good MDIS structure, characterized in that the equivalent thickness of the gate insulating film in terms of Si oxide film is 1 nm or less.

The conductive film used for the gate electrode is formed in an oxygen atmosphere.
Is the metal resistant to oxidation because it is annealed in
It must be a conductive metal oxide. The inventor
Are noble metals Ir, Pt, Au, Ag, Ru,
Os, refractory metal Co, conductive oxide RuO₂, RhO
₂, OsO₂, IrO₂, ReO₂, ReO₃, MoO
₂, SrRuO₃Of any of these or a combination of each of these
Gold or a structure in which the above materials are formed in multiple layers
When the conductive film is used, the transistor operation is particularly good.
It was confirmed.

When depositing a metal oxide, it is necessary to suppress the oxidation of the silicon nitride film and to sufficiently oxidize the organometallic material gas. Although nitrogen dioxide has a strong oxidizing power, it hardly oxidizes a silicon nitride film. Therefore, it is desirable to use nitrogen dioxide as the oxidizing gas.

[0027]

BEST MODE FOR CARRYING OUT THE INVENTION A field effect transistor according to the present invention is formed as a gate insulating film on a single crystal silicon substrate.
A stacked film of a silicon nitride film and a tungsten-titanium mixed oxide or a tungsten-zirconium mixed oxide is provided.

The field effect transistor according to the present invention comprises a first step of forming a silicon nitride film on a single crystal silicon substrate, and a step of forming hexadimethylaminoditungsten (W) as a tungsten source gas on the silicon nitride film.
_{2 (N (CH 3) 2} ) 6) using organic metal material gas and the oxidizing gas tungsten containing - first forming zirconium mixed metal oxide below 400 ° C. substrate temperature of 350 ° C. or higher - titanium mixed oxide or tungsten A second step, a third step of forming a conductive film on the metal oxide, a fourth step of patterning the metal oxide and the conductive film to form a gate insulating film and a gate electrode, A fifth step of implanting impurity ions into the diffusion layer in a self-aligned manner with respect to the gate insulating film and the gate electrode by using the gate insulating film and the gate electrode as an ion implantation mask; A sixth step of forming a drain region; and a seventh step of performing oxygen annealing at a processing temperature of 350 ° C. or more and 400 ° C. or less. .

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic diagram showing an example of a thin film vapor phase growth apparatus used in the present invention. This apparatus includes a sample processing chamber 101 and an exchange chamber 102, and a plurality of wafers 107 can be stored in the exchange chamber 102. Sample processing chamber 101 and exchange chamber 102
Between them, a gate valve 104 is provided, and each room has an exhaust system 13 composed of a plurality of pumps.
It is exhausted by 2, 133, 134. Further, a wafer transfer mechanism 105 is provided for moving the wafer between the sample processing chamber 101 and the exchange chamber 102. During film formation, the sample processing chamber 101 is separated into two parts by a wafer. Below the wafer is a heater 106 for heating the wafer to a predetermined temperature. During film formation, an organic metal material gas and an oxidizing gas are introduced into a portion above the wafer by the gas supply systems 111 to 130, and a metal oxide is formed on the upper surface of the wafer. The gas supply systems 111 to 130 include gas supply systems 111 to 118, 119 to 124, and 125 to 130 for independently introducing three kinds of source gases into the sample processing chamber. Each gas supply system has basically the same configuration,
113, 122, 128 raw material cylinders and 111-
112-115-117, 119-121-123, 1
25-127-129 stop valve and 114, 1
20, 126 mass flow controllers and 118,
It comprises 124 and 130 exhaust systems. Gas supply system 111-
Reference numeral 118 denotes a supply system for the W material hexadimethylaminoditungsten (W ₂ (N (CH ₃ ) ₂ ) ₆ , and a mass flow controller 114 for introducing a carrier gas into the raw material cylinder 113, and a stop valve 11.
5. The carrier gas cylinder 116 is connected. The raw material cylinder 113 has a raw material cylinder 122 at a sublimation temperature of 120 ° C. of hexadimethylaminoditungsten.
128 is heated so that a vapor pressure sufficient for operating the mass flow controller is obtained. When each gas supply system has such a configuration, the source gas can be supplied quantitatively and stably. That is, 119-1
Taking the gas supply system consisting of 24 as an example, when gas is introduced, first, the stop valve 119 is closed, the stop valves 121 and 123 are opened, and the mass flow controller 120 allows the gas to flow at a desired flow rate. Wait for stability. Next, the stop valve 12
By closing the stop valve 119 and opening the stop valve 119, the source gas can be supplied quantitatively and stably. Also, 1
When hexadimethylaminoditungsten is supplied by the gas supply system including 11 to 118, first, the stop valve 111 is closed, and the stop valves 112, 1
15, 117 are opened and the mass flow controller 114 is opened.
Waits for the gas flow rate to stabilize while flowing the gas at the desired flow rate.

In the present apparatus, since each gas supply system is independent, the organic metal material gas and the oxidizing gas do not come into contact with each other, which prevents not only clogging of the piping and the mass flow controller, but also quantitative and raw material gas. Stable supply can be achieved.

[0032] The heater is set at a temperature not lower than the boiling point-sublimation point of the organometallic material gas and not higher than the decomposition temperature by a heater in all portions where the source gas comes into contact. This not only prevents clogging of the piping-mass flow controller, but also enables quantitative and stable supply of the source gas. In particular, the heating of the sample processing chamber also has an effect of suppressing particles.

The piping for exhausting the portion above the wafer is as follows:
It splits into two parts on the way and joins in front of the exhaust system 133. One of the divided pipes is provided with a gate valve 108, and the other is provided with a gate valve 109 and a water-cooled trap 110. During film formation, the gate valve 108 is closed, and the gate valve 109 is opened. With such a configuration, solidification and liquefaction of the organometallic material gas in the exhaust system 133 can be prevented, and the effect of extending the life of the exhaust system 133 can be obtained. When the film is not formed, the gate valves 108 and 109 during film formation are open. With such a configuration, the pumping speed increases and a higher vacuum can be obtained. Note that a vacuum gauge 131 is provided in the sample processing chamber to monitor the internal pressure of the sample processing chamber.

An embodiment of the film forming method of the present invention will be described by taking as an example a metal oxide in which a part of the W ⁶⁺ site of WO ₃ has been replaced by Ti ⁴⁺ (hereinafter referred to as WTO).

The raw material, the raw material temperature, and the mass flow controller temperature at the time of forming the WTO are hexadimethylaminoditungsten (W ₂ (N (CH ₃ ) ₂ )) as the W raw material.
₆ Sublimation temperature 120 ° C, decomposition temperature 170 ° C), Raw material temperature 1
20 ° C, mass flow controller temperature is 150 ° C, T
Ti (OPr ⁱ ) ₃ (OCH ₂ CH ₂ (N
Me ₂ )), the raw material temperature is 75 ° C., the mass flow controller temperature is 145 ° C., the mass flow controller temperature of the oxidizing gas NO ₂ is 145 ° C., and the inner wall temperature of the sample processing chamber is 150 ° C.

FIG. 2 shows the dependency of the film composition on the flow rate of the source gas when the substrate temperature is 400 ° C. and the partial pressure of NO ₂ is 3.5 × 10 ⁻³ Torr. As shown in this figure, the film composition changes continuously with respect to the source gas flow ratio, and a film having a desired composition can be formed by adjusting the source gas flow ratio.

Under the above conditions, WTO is increased to Ir (200 nm) /
A film is formed on a SiO ₂ (500 nm) / Si substrate, and is annealed at 1 atm at 800 ° C. for 10 minutes, at 1 atm at 400 ° C.
FIGS. 3 and 4 show the composition dependence of the leak current density and the dielectric constant of a sample on which gold was deposited as an upper electrode after oxygen annealing for 0 minutes. However, the WTO in each composition
The film is formed so as to have a thickness of 1 nm in terms of a silicon oxide film, and has a leak current density at an applied voltage of 1 V. If the W ⁶⁺ site of WO ₃ is replaced by more than 40%, the crystal system of the WTO film will not be a perovskite type, and a high dielectric constant will not be obtained. Therefore, the replacement exceeding 40% is not performed. From FIG. 3, the W of WO ₃
Replacing 15-25% of the ⁶⁺ sites with Ti ⁴⁺ gives
The leakage current is suppressed to 10 ⁻³ A / cm ² or less when the equivalent silicon oxide film thickness is 1 nm and 1 V is applied. The reason why the substitution reduces the leakage is that the Ti ⁴⁺ ion is a tetravalent ion, so that a hole is introduced, which cancels out the electron, which is a charge carrier in WO ₃ . According to FIG. 4, when the substitution amount is 15 to 25%, the dielectric constant takes a value of 120 to 240. The dielectric constant is maintained high even if the substitution, the ionic radius of ^{Ti 4+} ions, and 0.061Nm, since close to the six-coordinate ^{W 6+} ion radius 0.060nm in WO _3, of WO ₃ This is because crystallinity is not significantly affected.

FIG. 5 shows a W ⁶⁺ site formed on a p-type silicon substrate with a thickness of 10 nm, and Ti ⁴⁺ ions at 15, 20, 25.
It is a capacity-voltage characteristic of WTO with% substitution. When the applied voltage is negative, the capacity-voltage curve shows a rise in all cases. Further, the present inventor has found that the rise of the capacity-voltage curve indicates that the substitution amount of Ti ⁴⁺ is 15 to 25%.
It was confirmed when it was within the range. Therefore W
^{When 6+} is replaced with 15 to 25% of Ti ⁴⁺ ions, W
The energy band of TO has been improved such that the top of its valence band is lower than the top of the valence band of silicon and the bottom of its conduction band is higher than the bottom of the conduction band of silicon.

FIG. 6 shows that hexadimethylaminoditungsten is used as a W raw material, and Ti (OPr ⁱ ) _{3 is used} as a Ti raw material.
(OCH ₂ CH ₂ (NMe ₂ )), NO as oxidizing gas
Formed using _2, ^{Ti 4+} substitution amount of ions 20%
4 shows the results of measuring the substrate temperature dependence of the carbon concentration in WTO by Auger emission spectroscopy. The nitrogen concentration was below the lower limit of detection at a substrate temperature of 300 ° C. or higher. The carbon concentration in the film is 0.33% at a substrate temperature of 350 ° C. This value is obtained by using a conventional source gas of tantalum oxide-titanium oxide, which is currently considered as a gate insulating film, and setting the substrate temperature to 35.
It is not more than 1/20 of the carbon concentration in the film when the film is formed at 0 ° C. This is due to the fact that the decomposition temperature of hexadimethylaminoditungsten is 170 ° C., which is 30 ° C. or more lower than the organometallic gas used for depositing a conventional metal oxide.

FIG. 7 shows the concentration of carbon in the film when the WTO with 20% Ti ⁴⁺ ion deposited at a substrate temperature of 300 ° C. to 450 ° C. is first heat-treated at 850 ° C. for 10 minutes in nitrogen and then annealed with oxygen. 4 shows the oxygen annealing temperature dependency.
When the deposition temperature is 300 ° C., when the annealing temperature is 450 ° C. or less, both carbon and nitrogen remain in the film. On the other hand, when the deposition temperature is 350 ° C., the oxygen annealing temperature is 350 ° C.
As described above, impurities are almost completely removed from the film.
FIG. 8 shows that the tungsten-titanium oxide deposited at a substrate temperature of 300 ° C. to 450 ° C. is heat-treated in nitrogen at 850 ° C. for 10 minutes, then annealed with oxygen for 10 minutes, and oxygen in the silicon nitride film measured by Auger emission analysis 4 shows the oxygen annealing temperature dependence of the concentration. When the deposition substrate temperature is 450 ° C., when the oxygen annealing temperature is 300 ° C. or higher, the oxygen concentration in the silicon nitrogen film exceeds 10%. On the other hand, when the deposition substrate temperature is 400 ° C. or less, the oxygen annealing temperature 400
Below the temperature, the oxygen concentration in the silicon nitride film is suppressed to 10% or less. SIMS measurement was performed at an oxygen annealing temperature of 450 ° C. or lower, but no interdiffusion was observed. Therefore, a metal oxide containing tungsten as a main component is formed on a silicon nitride film having a thickness of 1 nm or less. When performing oxygen annealing, hexadimethylaminoditungsten is used as a tungsten raw material, and a substrate temperature during deposition is reduced.
When the oxygen annealing temperature is set to 350 ° C. or more and 400 ° C. or less, the insulating properties of the metal oxide are not deteriorated.
Interdiffusion-The oxidation of the silicon nitride film can be greatly suppressed.
This is because by using hexadimethylaminoditungsten as a tungsten raw material, it was possible to lower the substrate temperature during deposition and the oxygen annealing temperature while reducing the amount of impurities remaining in the metal oxide film. If the oxygen concentration in the nitride film is 10% or less, the dielectric constant of the nitride film can be 6 or more. Therefore, when hexadimethylaminoditungsten is used as the tungsten raw material and the above-mentioned substrate temperature-oxygen annealing temperature is used, the equivalent thickness of the gate insulating film in terms of the Si oxide film is 1 nm or less, and the MDIS structure is excellent. A simple field-effect transistor can be realized.

FIG. 9 shows a WTO film (Ti) formed at a substrate temperature of 400 ° C. and a partial pressure of NO ₂ of 3.5 × 10 ⁻³ Torr.
/(W+Ti)=0.2) with n-type M as gate insulating film
1 shows a cross-sectional structure of a DIS-FET. Impurity concentration 5 × 10
An element isolation region 210 having an STI structure is formed on an n-type single crystal silicon substrate 201 of about ¹⁵ cm ⁻³ . A p-well (not shown) is formed in the n-type transistor formation region. This element isolation region 21
In the transistor region separated by 0, a p-type channel impurity layer having an impurity concentration of about 5 × 10 ¹⁶ cm ⁻³ for controlling a threshold is formed (not shown), and the impurity concentration is 5 × 10 ¹⁹ cm. ^A source-drain region 202 composed of about ^-3 n-type diffusion layers is formed. A silicon nitride film 204 having a thickness of about 1 nm is formed on the channel region 203, and a WTO film (Ti / (W + Ti) = 0.2) 2 having a thickness of about 12 nm is further formed thereon.
05 is formed. A gate electrode 206 is formed on the metal oxide insulating film 205 in a self-aligned manner with respect to the source-drain region 202. Each source-drain region 202 is formed through a contact hole provided in the interlayer insulating film 208.
Each source-drain electrode 207 electrically connected to this is formed. Further, the whole is covered with the passivation film 209.

Next, a method of manufacturing the n-type MDIS-FET will be sequentially described with reference to FIG.

The surface of n-type single crystal silicon substrate 201 is cleaned by a cleaning method using a mixed aqueous solution of hydrogen peroxide, ammonia and hydrochloric acid. Since the purpose is to clean the surface of the single crystal silicon substrate 201, it goes without saying that a cleaning method other than the above may be used. Next, a p-well is formed on the silicon substrate 201. Next, a trench is dug on the substrate 201 by RIE, and an insulating film is buried in the trench to form a trench-type element isolation region 210. Next, after a silicon oxide film 211 having a thickness of about 5 nm is formed, channel ion implantation is performed to form a p-type channel impurity layer (not shown). Next, the p-type channel impurity layer is activated by RTA at 800 ° C. for about 10 seconds (FIG. 10A). Next, the silicon oxide film is peeled off with hydrofluoric acid, and is subjected to RTN using ammonia at 1000 ° C.
To form a silicon nitride film 204 (0.8 nm thick). Next, a 12.5 nm-thick metal oxide insulating film 205 WTO is formed on the silicon nitride film 204 by MOCVD.
(Ti / (W + Ti) = 0.2) at a substrate temperature of 400 ° C.
Formed. Next, a gate electrode 206 made of Ir is formed on the metal oxide insulating film 205 (FIG. 10B).

Next, a photoresist pattern (not shown) is formed on the gate electrode 206, and anisotropic etching is performed using the photoresist pattern as an etching mask to form a gate electrode 20.
6. Pattern the metal oxide insulating film 205. Next, using the photoresist pattern, the gate electrode 206, and the metal oxide insulating film 205 as a mask for ion implantation,
By implanting impurity ions (arsenic) into the substrate 201, the source-drain region 202 is formed in a self-aligned manner with respect to the gate electrode 206 and the metal oxide insulating film 205 (FIG. 10C). Next, the photoresist pattern is removed, and a heat treatment (a nitrogen atmosphere, 800 ° C., 10 minutes) for source-drain activation is performed. This step also serves as crystallization of the metal oxide insulating film 205. Next, oxygen annealing in an oxygen atmosphere at 400 ° C. for 10 minutes is performed to compensate for oxygen vacancies in the metal oxide insulating film and remove impurities. Next, the silicon nitride film on the source-drain region 202 is removed, and an interlayer insulating film 208 is formed. Next, the source-
After forming a contact hole reaching the drain region 202 and the gate electrode 206 and depositing Al, this is patterned to form a gate electrode 206 and a wiring 207. Further, a passivation film 209 is formed on the entire surface,
The transistor shown in FIG. 9 is obtained.

The gate capacitance per unit area of the transistor formed by the above-described steps is 3.8 μFrad.
/ Cm ² , and when the silicon equivalent film thickness of the gate insulating film was 1.0 nm, the expected gate capacitance per unit area exceeded 3.6 μFrad / cm ² . That is, the equivalent silicon thickness of the gate insulating film of the formed transistor is 1.0 nm or less. This is because the metal oxide 205 formed in the above process has a high dielectric constant (about 150) even in a thin film of about 10 nm, and when forming the metal oxide 205, 170 ° C.
By using hexadimethylaminoditungsten having a decomposition temperature of, the impurities in the metal oxide 205 could be completely removed even when both the formation temperature of the metal oxide 205 and the oxygen annealing temperature were set to 400 degrees or less. as well as,
When both the formation temperature of the metal oxide 205 and the oxygen annealing temperature are 400 ° C. or less, the oxygen concentration in the silicon nitride film 204 can be suppressed to 10% or less, and the Ir oxide has electric conductivity. .

FIG. 11 shows the gate voltage dependence of the gate leakage current density of the transistor manufactured in the above process.
The gate leakage current density at a gate voltage of 1 V is 10 ⁻³ A
/ Cm ² . This is because even if the metal oxide 205 formed in the above step is a thin film having a thickness of about
This is because it has a feature of a leak current density of 10 ⁻³ A / cm ² or less when V / cm is applied.

Further, when the operation of the transistor prepared in the above process was confirmed, a normal operation was shown. This is because when forming the metal oxide 205, 17 W
By using hexadimethylaminoditungsten having a decomposition temperature of 0 ° C., the insulation characteristics of the metal oxide 205 did not deteriorate, and both the formation temperature and the oxygen annealing temperature could be reduced to 400 ° C. or less. This is because mutual diffusion with the silicon substrate could be suppressed.

As described above, the MDIS is characterized in that the gate insulating film has a thickness equivalent to a Si oxide film of 1 nm or less and a gate leak current at a gate voltage of 1 V is 10 ⁻³ A / cm ² or less. A thin-film field-effect transistor having a structure can be realized.

The gate electrode 206 is not limited to Ir.
Any material that is not oxidized by oxygen annealing or an oxide having electrical conductivity may be used. The inventor has determined that the precious metal P
t, Au, Ag, Ru, Os, refractory metal Co, conductive oxides RuO ₂ , RhO ₂ , OsO ₂ , IrO ₂ , Re
It has been confirmed that the transistor of the above-described embodiment can obtain the same effect even when O ₂ , ReO ₃ , MoO ₂ , SrRuO ₃ or an alloy of these materials is used.

The gate electrode 206 may have a structure in which each of the above-mentioned materials is formed in a plurality of layers. For example, the same effect and action can be obtained even in a two-layer structure in which a platinum layer is formed on a titanium layer. Confirmed that you get.

The present inventor has found that the material of the metal oxide 205 is
WO₃W⁶⁺Part of the site is Zr ⁴⁺Metal substituted with
Even if the oxide is WZO, the above transistor is the same.
It was confirmed that the effects and effects of the above were obtained. Zr⁴⁺including
When producing metal oxides, for example,
For example, tetrakisdiethylaminozirconium (Zr (N
(CH₃)₂)₄Boiling point 120 ° C, decomposition temperature 200 ° C or less
Above) can be used. Raw material heating temperature, mass flow control
Roller temperature is tetrakisdiethylaminozirconium
In this case, the temperature is preferably 70 ° C. and 110 ° C., respectively. Ma
In this case, the inner wall temperature of the sample processing chamber is 150
℃ is good. WZO is Zr⁴⁺Of 12-27%
In the case, a dielectric constant of 100 or more and a thin film of about 10 nm
, The leakage current density when applying an electric field strength of 1 MV / cm
10^-3A / cm²It has the following features. Therefore,
The thickness of the gate insulating film is 1 nm or less in terms of Si oxide film.
And the gate leakage current is 10 when the gate voltage is 1 V.
^-3A / cm²MDIS structure characterized by the following
The field effect transistor of the structure can be provided.

[0052]

As described above, according to the present invention,
When the thickness of the gate insulating film is 1 nm or less in terms of Si oxide film, and the gate leakage current is 1 V when the gate voltage is 1 V,
MDIS characterized by being at most 0 ^-3 A / cm ^2.
A field effect transistor having a structure can be provided.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a thin film vapor deposition apparatus of the present invention.

FIG. 2 is a graph showing the dependency of the film composition of the present invention on the flow rate of source gas.

FIG. 3 is a graph showing the composition dependency of the leak current of the metal oxide dielectric film of the present invention.

FIG. 4 is a graph showing the composition dependency of the dielectric constant of the metal oxide dielectric film of the present invention.

[5] capacity of Ti-Doped tungsten oxide WO ₃ on p-type silicon - is a graph showing the voltage characteristic.

FIG. 6 is a graph showing the substrate temperature dependence of the carbon concentration in Ti-doped tungsten oxide deposited by MOCVD.

FIG. 7 is a graph showing the oxygen annealing temperature dependence of the carbon concentration in Ti-doped tungsten oxide.

FIG. 8 is a graph showing the oxygen annealing temperature dependency of the oxygen concentration in the silicon nitride film immediately below Ti-doped tungsten oxide.

FIG. 9 is a cross-sectional view illustrating a structure of a semiconductor device of the present invention.

FIG. 10 is a cross-sectional view showing a manufacturing step of the semiconductor device of the present invention.

FIG. 11 is a graph showing gate leakage characteristics of the semiconductor device of the present invention.

[Explanation of symbols]

 101 Sample processing chamber 102 Sample exchange chamber 103 Wafer in sample processing chamber 104 Gate valve 105 Wafer transport mechanism 106 Heater 107 Wafer in sample exchange chamber 108 Gate valve 109 Gate valve 110 Water cooling trap 111 Stop valve 112 Stop valve 113 Raw material cylinder 114 Mass flow controller 115 Stop valve 116 Carrier gas cylinder 117 Stop valve 118 Exhaust system 119 Stop valve 120 Mass flow controller 121 Stop valve 122 Material cylinder 123 Stop valve 124 Exhaust system 125 Stop valve 126 Mass flow controller 127 Stop valve 128 Material cylinder 129 Stop valve 130 Exhaust system 131 Vacuum gauge 13 Exhaust system 133 Exhaust system 134 Exhaust system 201 Si (100) substrate 202 Source-drain region 203 Channel region 204 Silicon nitride film 205 Impurity-doped tungsten oxide 206 Gate electrode 207 Source-drain electrode 208 Interlayer insulating film 209 Passivation film 211 Silicon Oxide film

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/318 H01L 21/318 CF term (Reference) 5F040 DA14 DA19 DB01 EC01 EC04 EC08 ED01 ED03 ED04 EH02 EH05 EK05 FC21 5F045 AA04 AB31 AB33 AB40 AC07 AC08 AC11 AD07 AD08 AF01 AF03 BB16 CA05 DC51 DC55 DP01 DP02 DP03 EK05 EK07 HA16 5F058 BA01 BA06 BD01 BD03 BD05 BD09 BD10 BF01 BF02 BF06 BF22 BF29 BF30 B01B03 BF51 B52H55

Claims (6)

[Claims] 1. A field-effect transistor in which a silicon nitride film and a stacked film of a mixed oxide of tungsten and titanium or a mixed oxide of tungsten and zirconium are provided as a gate insulating film over a single crystal silicon substrate. 2. The gate electrode provided on the laminated film is made of a noble metal Ir, Pt, Au, Ag, Ru, Os, a refractory metal Co, a conductive oxide RuO ₂ , RhO ₂ , OsO.
₂ , IrO ₂ , ReO ₂ , ReO ₃ , MoO ₂ , SrR
2. The field-effect transistor according to claim 1, wherein one of uO ₃ , an alloy of each of these materials, or a structure in which each of the materials is formed in a plurality of layers. 3. A first step of forming a silicon nitride film on a single crystal silicon substrate, and hexadimethylaminoditungsten (W ₂ (N (CH ₃ ) ₂ ) ₆ as a tungsten source gas on the silicon nitride film. A) forming a tungsten-titanium mixed oxide or a tungsten-zirconium mixed metal oxide using an organometallic material gas containing) and an oxidizing gas; and 3) forming a conductive film on the metal oxide. Forming a gate insulating film and a gate electrode by patterning the metal oxide and the conductive film; forming a gate insulating film and a gate using the gate insulating film and the gate electrode as an ion implantation mask; A fifth step of implanting impurity ions into the diffusion layer in a self-aligned manner with respect to the electrode; The a sixth step, a seventh step in the method of manufacturing the field effect transistor, characterized in that it comprises a for oxygen annealing to form regions. 4. The substrate temperature in the second step is 350 ° C.
4. The method according to claim 3, wherein the oxygen annealing temperature in the seventh step is 350 ° C. or more and 400 ° C. or less. 5. The method according to claim 1, wherein the gate electrode is made of a noble metal Ir, Pt,
Au, Ag, Ru, Os, high melting point metal Co, conductive oxides RuO ₂ , RhO ₂ , OsO ₂ , IrO ₂ , Re
4. It is any one of O ₂ , ReO ₃ , MoO ₂ , SrRuO ₃ , an alloy of each of these materials, or formed by forming each of the materials in a plurality of layers. 5. The method for manufacturing a field-effect transistor according to 4. 6. The method according to claim 3, wherein the oxidizing gas includes a nitrogen dioxide gas.