JP2001043109A - Logic verifying system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a logic verifying system for improving and making uniform quality of logic verification for pointing out a fault by automatically executing optimized test menus hierarchically arranged on the basis of analysis of error contents when that error is detected. SOLUTION: Tests selected out of a test group 100 are prepared as test menus 201a-203a optimized corresponding to respective hierarchies. According to these prepared test menus 201a-203a, the tests classified into groups are executed. When any error is detected, the test menus 201c and 202c hierarchically arranged on the basis of the analysis of these error contents and optimized as tests by hierarchies are automatically executed. Thus, the optimal test can be executed for pointing out the logic fault without human intervention. Therefore, at the time point when the test is finished, a fault logic spot can be inferred.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for automatically selecting and executing a test having a hierarchical structure, which is optimal for extracting a logical fault, and inferring a fault logic based on accumulated error information. The present invention relates to a logic verification method capable of specifying a logic fault location.

[0002]

2. Description of the Related Art Conventionally, logical fault diagnosis employs a method of executing an effective test to extract a logical fault and analyzing the result. However, when an error is detected by a specific test, Further tests may be performed to further isolate the fault. in this case,
The means of executing a test menu and collecting and analyzing error information of test results have been manually performed.

[0003] For these reasons, the quality of the work and test of information collection and analysis for specifying the failure logic largely depends on the qualities of the individual, and the time required for indicating the logical failure also differs depending on the individual difference.

Known techniques related to a logic verification method similar to the present invention include a random test method, a test pattern generation method, a test method not affected by a hardware configuration, and the like, for example, see JP-A-7-2866.
3, JP-A-7-110777 and JP-A-7-24893
5, JP-A-7-253898, JP-A-7-25390
2. There are JP-A-7-262038 and the like, but these do not automatically execute sorting by hierarchical test as shown in the present invention and accumulate error information for comprehensive analysis. The logic verification method is not found in the known art.

[0005]

As described above, in the above-mentioned prior art, the work of collecting and analyzing information for specifying the fault logic largely depends on the qualities of the individual, and the time required for indicating the logical fault differs depending on the individual difference. There was a problem.

It is an object of the present invention to improve the quality of logic verification for fault indication by improving the quality of logic verification for fault indication by automating test selection and error analysis instead of relying on individual qualifications for logic fault indication. An object of the present invention is to provide a logic verification method for realizing the generalization.

[0007]

According to the present invention, a test menu necessary for indicating a fault logic is prepared in advance, and a hierarchical test to be executed next is automatically selected from the execution result of the test menu. By executing and performing comprehensive analysis from the accumulated error information, it is possible to perform a homogeneous test and indicate a logical failure. This means that according to the menu prepared as a test menu, the tests classified into groups are executed, and if an error is detected, the hierarchical test menu is automatically executed next based on the analysis of the error content. The test menu to be executed is executed sequentially, and if an error is detected as a test result, the error information is sequentially saved and stored, and the saved and saved error information is comprehensively analyzed when all the tests are completed. Achieved.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described.
This will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an example of a logic verification method, and shows a test at three levels.
In FIG. 1, the logic verification includes a test group 100 for diagnosing a logic / logic fault, a hierarchical test procedure 200 for sequentially executing tests, an information storage process 300, a logic fault inference table 400, and a logic fault indication process 500. Is done.

The test group 100 is configured for each purpose of fault diagnosis, and has the execution order of these in the hierarchical test procedure 200 as a test menu. Hierarchical test procedure 2
00 is composed of test execution procedures 201, 202, and 203 having a test procedure at each level. If an error is detected as a result of the test, an error information storage process 301 for accumulating and storing related information, an information storage process 300 including an error information storage table 302,
After all tests in the hierarchical structure are completed, a logical fault is inferred based on the data of the logical fault inference table 400 for inferring the fault location from the accumulated information, the error information storage table 302, and the logical fault inference table 400. Logical reasoning process 501 to perform, indicating a logical fault 50
2 is a logical fault indication process 500 comprising:

A method of executing a test by this hierarchical method is as follows.
This is specifically shown with reference to FIGS. Test group 1
00 are selected as test menus 201a, 202a, and 20 as test menus optimized for each layer.
3a, and the test of the first layer 201 is executed first. Test menu 2 on the first level 201
The tests indicated by 01a are sequentially executed, and when an error is detected as a result, the error information is stored in the error information storage table 302 through the error information storage processing 301. Analyze the details of the error, and
A test menu 201c for executing the next second hierarchical test is called from the execution correspondence matrix 201b,
Transition is made to test execution on the second hierarchy 202.

A test menu called as a test result of the first hierarchy 201 is a test menu 202 a for executing a test optimized as a test of the second hierarchy 202.
The tests shown in the test menu are sequentially executed. When an error is detected in the test execution of the second hierarchy, the error information is accumulated and stored in the error information storage table 302 through the error information storage processing 301 as in the case of the error detection in the first hierarchy. Analyze the details of the error, and
A test menu 202c for executing the next third hierarchical test is called from the execution correspondence matrix 202b,
The process proceeds to the test execution of the third hierarchy 203.

A test menu called as a test result of the second hierarchy 202 is a test menu 203 a for executing a test optimized as a test of the third hierarchy 203.
The tests shown in the test menu are sequentially executed. When an error is detected in the test execution of the third layer, the error information is accumulated and stored in the error information storage table 302 through the error information storage processing 301 as in the case of the error detection in the second layer. If no error is detected, the test menu of the next hierarchy from the result / execution correspondence matrix 203b is not called, and the execution of the hierarchical test is terminated. By sequentially executing such hierarchical tests, it is possible to perform all tests necessary to point out a logical failure without manual intervention, and the test results are stored in an error information storage table. become. When the execution of all the tests is completed, the error information is compared with the contents of the logical fault inference table and the logical fault inference processing 501, a logical fault is pointed out in the processing of 502, and a series of processing ends.

FIG. 2 is a flow chart showing one embodiment of the present invention, showing main processing in each hierarchy. Processing at each layer is a function for executing tests according to the test menu, checking for the presence or absence of error detection, storing error information when an error is detected, and checking the existence of the next test menu according to the hierarchical structure It is composed of

FIG. 3 is a diagram showing a configuration of a test menu.
It is a block diagram showing an example of a test group. The tests are classified into several groups according to their purpose, each having a classification identification such as Group 1, Group 2, etc., a test menu,
Used as unique identification information for the result / execution correspondence matrix.

FIG. 4 shows an embodiment of the menu structure showing the contents of the test menu. The optimal test combinations in each hierarchy are arranged in this test menu.

FIG. 5 is an embodiment showing the execution of a test in a certain hierarchy, showing the test execution procedure as a test menu, an error information storage table, a result / execution correspondence matrix, and a hierarchy test menu. The tests shown in the test menu are sequentially executed, and when an error is detected, the content of the error is stored in the error information storage table as error information, and a matrix corresponding to the error is selected from the result / execution correspondence matrix. The selected matrix shows a test menu for a test in the next hierarchy, and the displayed test menu is executed as a test in the next hierarchy.

FIG. 6 shows an example of information stored in an error information storage table for storing error information when an error is detected as a result of the test. When an error is detected in the test execution result, the name of the test being executed at that time and the result of the error (for example, a logical operation error) are stored as a pair.

FIG. 7 shows an example of a logical fault inference table for inferring a logical fault state from an error type. The table stores inference information for inferring logical faults for each type of error, and stores a plurality of pieces of inference information when it is not possible to narrow down to one.

In the above embodiment, execution is performed at three levels and one test is performed at one level. However, depending on the depth of the test, the test may be performed at multiple levels and a large number of test menus. An execution method in which these are nested while having a relationship with each other may be used.

[0020]

As described above, according to the present invention, according to the menu prepared as the test menu, tests classified into groups are executed, and when an error is detected, the error is hierarchically arranged based on the analysis of the error content. By automatically executing the test menu that has been optimized as a hierarchical test, it is possible to execute the most appropriate test to point out a logical failure without human intervention. By sequentially saving the error information when an error is detected, it is possible to obtain an effect that the error information saved and stored can be comprehensively analyzed at the time when all the tests have been completed, and a faulty logic part can be inferred. .

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an example of a logic verification method.

FIG. 2 is a flowchart showing a main process in each layer, showing an embodiment of the present invention.

FIG. 3 is a block diagram showing an example of a test group for forming a test menu.

FIG. 4 is an example of a menu configuration showing the contents of a test menu.

FIG. 5 is an embodiment showing the execution of a test in a certain hierarchy in which the test execution procedure is shown as a test menu, an error information storage table, a result / execution correspondence matrix, and a hierarchy test menu.

FIG. 6 shows an example of information stored in an error information storage table for storing error information when an error is detected as a result of a test.

FIG. 7 shows an example of a logic failure inference table for inferring a logic failure state from an error type.

[Explanation of symbols]

Reference Signs List 100 Test group for diagnosing logical and logical failure 200 Hierarchical test procedure 201, 202, 203 Test execution procedure 201a, 202a, 203a Test menu 201b, 202b, 203b Result / execution correspondence matrix 201c, 202c Next hierarchy test menu 300 Information Storage processing 301 Error information storage processing 302 Error information storage table 400 Logical fault inference table 500 Logical failure indication processing 501 Logical reason inference processing

 ────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Hiroshi Kadota 1 Horiyamashita, Hadano-shi, Kanagawa F-term (reference) 2G032 AA01 AB20 AE12 AG01 5B048 AA01 CC17 DD15

Claims (2)

[Claims] In the logic verification, according to a menu prepared as a test menu, a test classified into groups is executed, and when an error is detected, an optimization is hierarchically arranged based on an analysis of the error content. A logic verification method that automatically executes a given test menu, thereby enabling an optimum test to be performed to indicate a logic failure without manual intervention. 2. The logic verification method according to claim 1, wherein when an error is detected as a test result, the error information is sequentially saved and stored, and the error information is saved when all the tests are completed. A logic verification method that has the function of comprehensively analyzing information and inferring the failure logic.