JP2001036041A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device, which can prevent a short circuit between lower electrodes of adjacent capacitive elements, even if a device is made fines. SOLUTION: A method for manufacturing a semiconductor device having a capacitive element. This method includes a step where a plurality of recesses having the shape of a lower electrode of the capacitive element are formed in line in a silicon oxide film 9, a step where a polysilicon film is deposited in the recesses and on the silicon oxide film 9 into such a thickness that the recesses are not be completely filled with the polysilicon film, a step where the polysilicon film is polished by a CMP method to the same level with the upper face of the silicon oxide film 9 to form the polysilicon film on the inner faces of the recesses, and a step where the silicon oxide film 9 existing between the polysilicon films is removed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a method for manufacturing a semiconductor device having a capacitance element. In particular, the present invention relates to a method for manufacturing a semiconductor device capable of preventing a short circuit between lower electrodes of adjacent capacitance elements even when elements are miniaturized.

[0002]

2. Description of the Related Art FIGS. 6 to 13 are sectional views showing a conventional method of manufacturing a semiconductor device. This method of manufacturing a semiconductor device is a method of manufacturing a dynamic random access memory (DRAM) in which a memory cell includes one transistor and one stacked capacitor (capacitance element).
In particular, it is a method of forming a lower electrode (storage node) of a stacked capacitor.

First, as shown in FIG. 6, element isolation films 3a and 3b made of a silicon oxide film are formed on the surface of a silicon substrate 1 by using the LOCOS method. Thereafter, a gate oxide film 6 is formed on the surface of the silicon substrate 1 by a thermal oxidation method. Next, a gate electrode 7 made of polysilicon doped with an impurity is selectively formed on the gate oxide film 6.
Thereafter, impurities are ion-implanted into the silicon substrate 1 using the gate electrode 7 as a mask, whereby diffusion layers 5a to 5d are formed in the silicon substrate 1 at both ends of the gate electrode 7 in a self-aligned manner. Next, the sidewall material 8 is selectively formed on the side surface of the gate electrode 7, and impurities are ion-implanted into the silicon substrate 1 using the sidewall material 8 and the gate electrode 7 as a mask (not shown). Thus, a MOS transistor is formed between the element isolation films 3a and 3b.

Next, a silicon oxide film 19 is deposited on the entire surface including the gate electrode 7, and contact holes reaching the diffusion layers 5a to 5d are formed in the silicon oxide film 19.

Thereafter, as shown in FIG. 7, a CVD (Chemical V) is formed in the contact hole and on the silicon oxide film 19.
The first doped with impurities by the apor deposition method
Is deposited. Next, as shown in FIG. 8, a Si ₃ N ₄ film 22 is formed on the first polysilicon film 21.
Is deposited.

Thereafter, as shown in FIG. 9, the Si ₃ N ₄ film 2
2 is coated with a resist, and the resist is exposed and developed to form a resist pattern 23 on the Si ₃ N ₄ film 22. This resist pattern 23
The pattern is such that the bottom of the lower electrode remains after the first polysilicon film 21 described later is etched.

Next, by etching the Si ₃ N ₄ film 22 using the resist pattern 23 as a mask, FIG.
As shown in FIG. ₃ , Si ₃ N _{4 is formed} on the first polysilicon film 21.
The columnar members 22a to 22d made of a film are formed. Subsequently, the first pattern is formed using the resist pattern 23 as a mask.
After etching the polysilicon film 21, the resist pattern 23 is removed. Thereby, as shown in FIG. 10, bottom portions 21 a to 21 d of the lower electrode made of the polysilicon film are formed on silicon oxide film 19. Each of these bottoms is connected to a diffusion layer 5a-5 through a contact hole.
d.

[0008] Thereafter, as shown in FIG.
A second polysilicon film 24 doped with impurities is deposited by a CVD method on the upper surface and the side surfaces of the silicon oxide film 19 (that is, on the entire surface).

Next, as shown in FIG. 12, the second polysilicon film 24 is anisotropically etched back,
The cylinder portions 24a to 24f are formed on the side surfaces of the members 22a to 22d and the bottom portions 21a to 21d. After this, FIG.
As shown in FIG. 3, the members 22a to 22d are removed by etching. Thus, the lower electrode (storage node) of the cylinder capacitor is formed. The lower electrode includes cylinder parts 24a to 24f and bottom parts 21a to 21d.

[0010]

In the above-mentioned conventional method for manufacturing a semiconductor device, the cylinder portions 24a to 24f of the lower electrode are formed by anisotropic etch back in the step shown in FIG. For this reason, when the MOS transistor and the capacitor are miniaturized and the interval between the lower electrodes is narrowed, an etching residue is likely to occur during anisotropic etchback. As a result, the adjacent lower electrodes may be short-circuited.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a method of manufacturing a semiconductor device capable of preventing a short circuit between lower electrodes of adjacent capacitance elements even when elements are miniaturized. Is to provide.

[0012]

In order to solve the above problems, a method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device having a capacitance element. Forming a plurality of concave portions having the outer shape of the lower electrode, and forming a conductive film having a thickness such that the concave portions are not completely filled on the inner surface of the concave portions,
It is characterized by having.

A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device having a capacitance element, wherein a plurality of concave portions having the outer shape of a lower electrode of the capacitance element are formed in an insulating film. And a step of depositing a conductive film having a thickness that does not completely fill the concave portion in the concave portion and on the insulating film, and polishing the conductive film to a depth of an upper surface of the insulating film by a CMP method. The method includes a step of forming the conductive film on the inner surface of the concave portion, and a step of removing an insulating film existing between the conductive films.

In the method of manufacturing a semiconductor device, a plurality of concave portions having the outer shape of the lower electrode of the capacitive element are formed in the insulating film so as to be formed, and the inner surface of the concave portion has a thickness such that the concave portion is not completely filled. The lower electrode is formed by forming a conductive film. That is, the lower electrode is not formed by anisotropically etching back the conductive film. Therefore, even if the miniaturization of the element progresses and the distance between the lower electrodes of the adjacent capacitance elements is reduced, it is possible to prevent the short circuit between the adjacent lower electrodes.

In the method of manufacturing a semiconductor device according to the present invention, it is preferable that the conductive film is a polysilicon film or a metal film. Further, the semiconductor device has a D
It can be RAM or FRAM.

In the method of manufacturing a semiconductor device according to the present invention, the dielectric film of the capacitor has a relative dielectric constant of 20.
It is also possible to use the above nitride.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

1 to 5 are sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. This method of manufacturing a semiconductor device is a method of manufacturing a dynamic random access memory (DRAM) in which a memory cell includes one transistor and one stacked capacitor (capacitance element). In particular, a stacked capacitor is manufactured using a damascene method. This is a method for forming a lower electrode (storage node).

First, as shown in FIG. 1, element isolation films 3a and 3b made of a silicon oxide film are formed on the surface of a silicon substrate 1 by using the LOCOS method. Thereafter, a gate oxide film 6 is formed on the surface of the silicon substrate 1 by a thermal oxidation method. Next, a gate electrode 7 made of polysilicon doped with an impurity is selectively formed on the gate oxide film 6.
Thereafter, impurities are ion-implanted into the silicon substrate 1 using the gate electrode 7 as a mask, whereby diffusion layers 5a to 5d are formed in the silicon substrate 1 at both ends of the gate electrode 7 in a self-aligned manner. Next, the sidewall material 8 is selectively formed on the side surface of the gate electrode 7, and impurities are ion-implanted into the silicon substrate 1 using the sidewall material 8 and the gate electrode 7 as a mask (not shown). Thus, a MOS transistor is formed between the element isolation films 3a and 3b. Next, the gate electrode 7
(Chemical Vapor Deposition) on the entire surface including
A silicon oxide film 9 is deposited by the method.

Thereafter, a lower electrode (storage node) is formed on the silicon oxide film 9 by a damascene method. Note that the damascene method is a method for forming an electrode, a wiring, or the like by forming a depression having a shape of an object such as an electrode or a wiring in an insulating film and embedding a conductive film or the like in the depression.

That is, a first resist pattern (not shown) is formed on the silicon oxide film 9, and the silicon oxide film 9 is etched using the first resist pattern as a mask. As a result, as shown in FIG. 2, the contact holes 9a reaching the diffusion layers 5a to 5d are formed in the silicon oxide film 9.
To 9d are formed.

Next, after removing the first resist pattern, a second resist pattern (not shown) is formed on the silicon oxide film 9, and the silicon oxide film 9 is formed using the second resist pattern as a mask. Etch to a predetermined depth. Thereby, as shown in FIG. 2, recesses 9 e to 9 h having the shape of the lower electrode connected to contact holes 9 a to 9 d are formed in silicon oxide film 9.

Thereafter, as shown in FIG. 3, an impurity-doped polysilicon film 11 is deposited in the contact holes 9a to 9d, the recesses 9e to 9h, and on the silicon oxide film 9. At this time, the polysilicon film 11 has the concave portions 9e to 9h.
Is so thick that it cannot be buried.

Thereafter, as shown in FIG. 4, the polysilicon film 11 is removed by CMP (Chemical Mechanical Polishing).
The upper surface of the silicon oxide film 9 is polished by the method g). As a result, the polysilicon film is left on the inner surfaces of the recesses 9e to 9h of the silicon oxide film 9, and a plurality of lower electrodes 11a to 11d are formed side by side.

Next, as shown in FIG. 5, the lower electrode 11a
The silicon oxide film 9 existing between .about.11d is removed by etching. The amount of etching at this time is controlled, for example, by the etching time. In this manner, the lower electrodes (storage nodes) 11a to 11d of the cylindrical stacked capacitor having a cylindrical appearance are formed, and the lower electrodes 11a to 11d are electrically connected to the diffusion layers 5a to 5d via the contact holes. Connected. Thereafter, a dielectric film (not shown) is formed on the lower electrode by using a known technique, and an upper electrode (not shown) is formed on the dielectric film.

According to the above embodiment, the contact holes 9a to 9d are formed in the silicon oxide film 9 by using the damascene method.
And a recess 9e having the shape of a lower electrode connected thereto.
To 9h are formed by etching. That is, the method does not include the step of forming the cylinder portion of the lower electrode by anisotropically etching back the polysilicon film as in the conventional method of manufacturing a semiconductor device. Accordingly, even if the distance between the lower electrodes is reduced due to the miniaturization of the MOS transistor and the capacitor, it is possible to prevent a short circuit between the storage nodes as the adjacent lower electrodes 11a to 11d. .

The present invention is not limited to the above embodiment, but can be implemented with various modifications. For example,
In the present embodiment, after the contact holes 9a to 9d are formed in the silicon oxide film 9, the concave portions 9e to 9h having the shape of the storage node are formed in the silicon oxide film 9, but the storage nodes are formed in the silicon oxide film 9. It is also possible to form the contact holes 9a to 9d in the silicon oxide film 9 after forming the concave portions 9e to 9h having the shapes shown in FIGS.

In this embodiment, the polysilicon film 11 is formed on the inner surfaces of the recesses 9e to 9h of the silicon oxide film 9 by polishing the polysilicon film 11 to the upper surface of the silicon oxide film 9 by the CMP method. However, by etching back the polysilicon film 11, the polysilicon film 1 is formed on the inner surfaces of the recesses 9 e to 9 h of the silicon oxide film 9.
It is also possible to form 1.

In this embodiment, the lower electrode 11a
Although 11d is formed of a polysilicon film, the lower electrode may be formed of a metal. For example, the lower electrode may be formed of Al, W, Cu, Ti, TiN, or the like. Further, the upper electrode can be formed of a polysilicon film or a metal.

Further, in the present embodiment, the above-described method for manufacturing a semiconductor device is applied to the formation of the lower electrode of the capacitive element of the DRAM. However, the present invention is not limited to the DRAM. It is also possible to apply the present invention to the formation of electrodes, for example, FRAM (Ferro-electric Random A
The present invention can be applied to formation of a lower electrode of a capacitive element of a ccess memory.

The dielectric film formed on the lower electrodes 11a to 11d may be made of a ferroelectric nitride having a relative dielectric constant of 20 or more. As this nitride, for example, BaTiN ₂ is suitable, which
It can be formed by the R-MOCVD method. That is, a gas containing at least a nitride atom and an organometallic complex of barium and titanium are introduced into a processing chamber by a carrier gas and reacted on a heated lower electrode, whereby B
It is also possible to form a dielectric film made of aTiN ₂ . When nitrogen is used instead of oxygen during the formation of the dielectric film, the electrode surface in contact with the dielectric can be prevented from being exposed to a high-temperature oxygen atmosphere. Film can be prevented from being formed,
A high capacitance value can be obtained.

Further, as the dielectric film formed on the lower electrode 11 a to 11 d, it is preferable to use a ferroelectric film, a ferroelectric film, for example, M1 ₂ (M _{X 2,} T
It preferably has an a _1-X ) ₂ O ₇ structure. However, M1
Is at least one element of Sr, Ca, La, and Nd, M2 is at least one element of Nb and Ti, and 0.1 ≦ X ≦ 0.5. Also, the ferroelectric film is composed of a solid solution of M1 ₂ M2 ₂ O ₇ and M1 ₂ Ta ₂ O _7.

[0033]

As described above, according to the present invention, a plurality of concave portions having the outer shape of the lower electrode of the capacitive element are formed side by side on the insulating film, and the concave portion is completely formed on the inner surface of the concave portion. The lower electrode is formed by forming a conductive film having a thickness not to be buried. Therefore, it is possible to provide a method of manufacturing a semiconductor device capable of preventing a short circuit between lower electrodes of adjacent capacitance elements even when the element size is reduced.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the embodiment of the present invention, showing a step subsequent to FIG. 1;

FIG. 3 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the embodiment of the present invention, showing a step subsequent to FIG. 2;

FIG. 4 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the embodiment of the present invention, which shows the step subsequent to FIG. 3;

FIG. 5 is a cross-sectional view illustrating the method of manufacturing the semiconductor device according to the embodiment of the present invention, which shows the step subsequent to FIG. 4;

FIG. 6 is a cross-sectional view illustrating a method for manufacturing a conventional semiconductor device.

FIG. 7 is a cross-sectional view showing a step subsequent to that of FIG. 6, illustrating a method for manufacturing a conventional semiconductor device.

FIG. 8 is a cross-sectional view illustrating a step subsequent to that of FIG. 7, illustrating a method for manufacturing a conventional semiconductor device.

FIG. 9 is a cross-sectional view showing a step subsequent to that of FIG. 8, illustrating a method for manufacturing a conventional semiconductor device.

FIG. 10 is a cross-sectional view showing a step subsequent to that of FIG. 9, illustrating a method for manufacturing a conventional semiconductor device.

FIG. 11 is a cross-sectional view illustrating a step subsequent to that of FIG. 10, illustrating a conventional method of manufacturing a semiconductor device.

FIG. 12 is a cross-sectional view showing a step subsequent to FIG. 11, showing a conventional method of manufacturing a semiconductor device.

FIG. 13 is a cross-sectional view illustrating a step subsequent to FIG. 12, illustrating a method for manufacturing a conventional semiconductor device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Silicon substrate 3a, 3b Element isolation film 5a-5d Diffusion layer 6 Gate oxide film 7 Gate electrode 8 Side wall material 9 Silicon oxide film 9a-9d Contact hole 9e-9h Depression 11 Polysilicon film 11a-11d Lower electrode (storage node) Reference Signs List 19 silicon oxide film 21 first polysilicon film 21 a to 21 d bottom portion of lower electrode 22 Si ₃ N ₄
Films 22a to 22d Member 23 Resist pattern 24 Second polysilicon film 24a to 24f
Cylinder part

Claims (5)

[Claims] 1. A method of manufacturing a semiconductor device having a capacitor, comprising: forming a plurality of recesses having an outer shape of a lower electrode of the capacitor in an insulating film; Forming a conductive film having a thickness such that the concave portion is not completely buried. 2. A method for manufacturing a semiconductor device having a capacitor, comprising: forming a plurality of recesses having an outer shape of a lower electrode of the capacitor in an insulating film; Depositing a conductive film having a thickness that does not completely fill the concave portion on the insulating film; and polishing the conductive film to a depth of an upper surface of the insulating film by a CMP method, so that the conductive film is formed on the inner surface of the concave portion. A method for manufacturing a semiconductor device, comprising: a step of forming the conductive film; and a step of removing an insulating film existing between the conductive films. 3. The method according to claim 1, wherein the conductive film is a polysilicon film or a metal film. 4. The semiconductor device according to claim 1, wherein the semiconductor device is a DRAM or a FRA.
4. The method of manufacturing a semiconductor device according to claim 1, wherein M is M. 5. 5. The semiconductor device according to claim 1, wherein the dielectric film of the capacitor is made of a nitride having a relative dielectric constant of 20 or more. Method.