JP2001035160A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an internal potential generating circuit capable of reducing power consumption while maintaining high-speed operation. SOLUTION: First and second buffer circuits 2042 and 2052 generate first and second reference potentials Vref1B and Vref2B. While sense operation is not performed, the level of a reference potential VrefM is turned into potential Vref1B by a switching circuit 2100 and while sense operation is performed, that level is turned into lower potential Vref2B. The buffer circuits 2042 and 2052 are controlled by a signal PUM so as to increase a through current just for a prescribed period when starting and ending the sense operation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having an internal potential generating circuit for generating an internal power potential in response to an external power potential.

[0002]

2. Description of the Related Art In recent years, as portable information terminals and the like have become remarkably widespread, storage elements mounted on these devices are required to be able to operate for a long time on a battery.

[0003] Because of the low bit unit cost, a dynamic random access memory (hereinafter referred to as DRAM) is often mounted on a portable information terminal device as such a storage element. However, since the data written in the DRAM is gradually lost if left unattended, an operation for data retention called a refresh operation is required.

One of the methods for reducing the current Iccsr consumed in a DRAM during a refresh operation is to optimize the design of a circuit portion through which a constant current flows so as to reduce a constant current flowing through the circuit portion. Reducing the through current may be mentioned. Further, the so-called standby current Iccs is also preferably low. In this case as well, it is important to reduce the steady-state through current as described above. In the following, a description will be given of an internal potential generation circuit that generates an internal potential of a DRAM as an example of a circuit in which such a steady current flows in a DRAM.

The internal potential generation circuit supplies a constant potential lower than the external power supply voltage to the internal circuit of the DRAM.
This greatly contributes to a reduction in the operating current of the RAM. In particular, in order to reduce the current Iccsr consumed during the refresh operation, it is important to set the internal power supply potential Vdds output from the internal potential generation circuit lower.

FIG. 17 shows a sense amplifier circuit S of a DRAM.
/ A including internal voltage generator 8040 for supplying internal power supply potential Vdds to / A.
000 is a schematic block diagram for explaining the configuration of the 000.

Conventional internal potential generation circuit 8000 operates in response to external power supply potential Vcc and ground potential Vss, and generates bias potentials VBH and VBL for defining a through current value of internal potential generation circuit 8000. A constant current source 8010, a Vref generating circuit 8020 which operates in response to external power supply potential Vcc and ground potential Vss, generates reference potential Vref for generating internal power supply potential Vdds in accordance with bias potential VBH, and bias potential VBL
Receiving the internal power supply potential Vd
a buffer circuit 8030 that generates a reference potential VrefM for generating ds, and a buffer circuit 8030 that receives the reference potential VrefM,
A voltage conversion circuit 8040 which is activated by the signal QON and outputs the internal power supply potential Vdds.

In the example shown in FIG. 17, sense amplifier S / A supplies internal power supply potential Vdd via p-channel MOS transistor TP0 controlled by signal ZS0P.
s is supplied, and the ground potential Vss is supplied via an n-channel MOS transistor TN0 controlled by the signal S0N.

The sense amplifier S / A is connected to a plurality of memory cells MC via a pair of bit lines BL and / BL. In FIG. 17, as an example, the sense amplifier S /
Only the memory cell MC connected to A via the bit line BL is shown. Bit line pair BL and / B is provided between bit line pair BL and / BL according to signal BLEQ.
A precharge / equalize circuit 81 for equalizing the L potential level and attaining the precharge potential level
00 is provided.

Memory cell MC connected to bit line pair BL
Is a memory cell transistor TM that opens and closes according to the potential level of the word line WL, and a cell plate potential V
A memory cell capacitor Cs coupled to CP and having the other end coupled to bit line pair BL via transistor TM is included. Here, the cell plate potential is generally set to a value of １ ／ of the potential corresponding to “H” level data stored in the memory cell capacitor.

[0011]

In the configuration shown in FIG. 17, as described above, since the internal power supply potential Vdds lower than the external power supply potential is supplied to the sense amplifier S / A, the current during operation is reduced. Reduction is achieved.

However, the low level of the internal power supply potential Vdds at the start of the sensing operation reduces the potential Vgs between the gate and the source of the transistor constituting the sense amplifier S / A. This means
This causes a delay in the sensing operation by the sense amplifier S / A.

As the chip area becomes smaller,
The ratio Cpb / Cb of the decoupling capacitance Cpb existing on the wiring from the voltage conversion circuit 8040 to the sense amplifier S / A to the capacitance Cb charged and discharged in the bit lines BL and / BL when performing the sensing operation is reduced. There is a tendency. That is, before the start of the sensing operation, the potential level of the internal power supply potential Vdds is held in the capacitor Cpb. Under such a state, during the period from the start of the sensing operation to the time when the voltage conversion circuit 8040 actually starts to supply the internal power supply potential Vdds at a predetermined level,
Charge is supplied from the capacitance Cpb to the charge / discharge capacitance Cb. Therefore, a decrease in the capacitance ratio Cpb / Cb means that the ratio of the level of the internal power supply potential Vdds supplied to the sense amplifier S / A to the transient level from the desired level increases.

An increase in such a transient decrease in the level of the internal power supply potential Vdds means an increase in the delay of the sensing operation as described above. In order to suppress such a delay in the sensing operation, if the period during which the internal power supply potential Vdds is transiently reduced is to be shortened, the current supply capability of the internal potential generation circuit 8000 is reduced.
It is necessary to increase even in the above-mentioned transition period.
This leads to an increase in the standby current value of the internal internal potential generation circuit 8000.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to suppress the transient fluctuation of the internal power supply potential level output from the internal voltage down converter while suppressing the fluctuation. An object of the present invention is to provide an internal potential generating circuit capable of suppressing a standby current value.

[0016]

According to a first aspect of the present invention, a semiconductor device receives a power supply potential and selectively outputs any one of a plurality of reference potentials in accordance with an operation mode. A plurality of potential generation circuits, each of which generates a plurality of reference potentials and increases current driving capability for at least a predetermined period according to switching of an operation mode; and a plurality of potential generation circuits. A switching circuit for receiving an output of the circuit and switching the output according to an operation mode, and further comprising an internal circuit that operates based on an output of the reference potential generation circuit.

According to a second aspect of the present invention, in addition to the configuration of the semiconductor device of the first aspect, each of the potential generating circuits includes a reference potential generating circuit for generating a reference potential corresponding to the generated reference potential; A buffer circuit that outputs a reference potential according to the reference potential, wherein the buffer circuit receives the output node and the power supply potential, and drives the potential level of the output node to the reference potential level according to the reference potential A current control circuit for switching a current value flowing through the drive circuit in an active state for at least a predetermined period in accordance with the switching of the operation mode.

According to a third aspect of the present invention, in addition to the configuration of the semiconductor device of the second aspect, a path of a current flowing through the drive circuit includes first and second paths parallel to each other.
The current control circuit is provided on a second path for generating a pulse signal that is in an active state for a predetermined period in accordance with the switching of the operation mode, and is turned on in response to the activation of the pulse signal. Switch circuit.

According to a fourth aspect of the present invention, in addition to the configuration of the semiconductor device of the second aspect, a path of a current flowing through the drive circuit includes first and second paths parallel to each other.
The current control circuit includes a mode signal generation circuit that generates a mode designation signal according to an operation mode, and a switch circuit provided on the second path and that is turned on in response to activation of the mode designation signal.

According to a fifth aspect of the present invention, there is provided a semiconductor device driven by an internal potential, a wiring transmitting the internal potential to the internal circuit, and a first potential and a first potential received by a power supply potential.
An internal potential generating circuit that selectively outputs one of the second potentials higher than the internal potential to the wiring by selectively switching the potential to an internal potential according to the operation mode of the internal circuit. , The first and second reference potentials respectively corresponding to the first and second potentials are switched and output according to the operation mode, and the current drivability is increased for at least a predetermined period according to the switching of the operation mode. It includes a reference potential generation circuit and a voltage conversion circuit that receives an output of the reference potential generation circuit at an input node and generates an internal potential. The voltage conversion circuit has a MOS transistor whose gate is coupled to the input node.

According to a sixth aspect of the present invention, in addition to the configuration of the semiconductor device of the fifth aspect, the reference potential generating circuit further comprises:
A first reference potential generation circuit for generating a first reference potential corresponding to the first reference potential, a second reference potential generation circuit for generating a second reference potential corresponding to the second reference potential, A first output of a first reference potential according to the first reference potential;
And a second buffer circuit that outputs a second reference potential according to a second reference potential. Each of the first buffer circuit and the second buffer circuit includes an output node, In response to the power supply potential, the value of the current flowing in the active state in the active state is increased for at least a predetermined period after the transition of the operation mode, so that the output node is set in accordance with one of the first and second reference potentials. And a driving circuit for driving the potential level of one of the first and second reference potentials to a corresponding one of the first and second reference potentials. And a switching circuit for selectively outputting one of them.

According to a seventh aspect of the present invention, in addition to the configuration of the semiconductor device of the sixth aspect, a path of a current flowing through the drive circuit includes first and second paths parallel to each other.
The drive circuit includes a switch circuit provided on the second path, which is turned on in response to activation of a pulse signal that maintains an active state for a predetermined period after a transition of an operation mode.

In the semiconductor device according to the eighth aspect, in addition to the configuration of the semiconductor device according to the sixth aspect, a path of a current flowing through the drive circuit includes first and second paths parallel to each other,
The current control circuit includes a switch circuit that is provided on the second path and that is turned on in response to activation of a mode designation signal that designates an operation mode.

According to a ninth aspect of the present invention, in addition to the configuration of the semiconductor device of the fifth aspect, the voltage conversion circuit is changed from an inactive state to an active state before switching the operation mode.

According to a tenth aspect of the present invention, there is provided a semiconductor device according to the fifth aspect.
In addition to the configuration of the described semiconductor device, the internal circuit includes a control circuit that controls the operation of the internal circuit in accordance with a given control signal, and a memory cell array including a plurality of dynamic memory cells arranged in a matrix. A plurality of bit line pairs provided corresponding to the columns of the memory cells, a memory cell selection circuit for selecting a memory cell according to an address signal,
A plurality of sense amplifiers that amplify the potential of the bit line pair coupled to the selected memory cell in accordance with the data held in the selected memory cell; and a control circuit that controls the internal potential of the sense amplifier. And a sense amplifier driving circuit for controlling the supply. Switching of the operation mode corresponds to switching of the sensing operation by the sense amplifier between active and inactive.

The semiconductor device according to the eleventh aspect is the fifth aspect.
In addition to the configuration of the semiconductor device described above, the reference potential generation circuit includes a first reference potential generation circuit that generates a first reference potential corresponding to the first reference potential, and a first reference potential generation circuit that generates a first reference potential corresponding to the second reference potential. A second reference potential generating circuit for generating a second reference potential, a first buffer circuit for outputting a first reference potential in accordance with the first reference potential, and a second reference potential in response to a second reference potential. A second buffer circuit that outputs two reference potentials,
Each of the first buffer circuit and the second buffer circuit receives the output node and the power supply potential, and reduces the value of the current flowing through the first buffer circuit and the second buffer circuit according to the designation of the self-refresh mode. And a drive circuit for driving the potential level of the output node to the corresponding one of the first and second reference potentials according to the corresponding one of the second reference potentials. A switching circuit that receives the outputs of the first and second buffer circuits and selectively outputs one of them according to an operation mode, wherein the internal circuit controls the operation of the internal circuit in response to a given control signal; A control circuit for controlling, a memory cell array including a plurality of dynamic memory cells arranged in a matrix, a plurality of bit line pairs provided corresponding to the columns of the memory cells, and an address. And a plurality of sense amplifiers that amplify the potential of a bit line pair coupled to the selected memory cell in accordance with data held in the selected memory cell. When,
A sense amplifier driving circuit controlled by the control circuit to control supply of the internal potential to the sense amplifier.

[0027]

[First Embodiment] FIG. 1 is a schematic block diagram showing an entire configuration of a DRAM 1000 according to a first embodiment of the present invention.

As will be apparent from the following description,
The internal potential generating circuit according to the present invention is not limited to the case where the internal potential generating circuit is mounted on the DRAM 1000 as shown in FIG. 1, and more generally generates an internal power supply potential based on an external power supply voltage Vcc. The present invention can be applied to a semiconductor device including a generation circuit. Further, the internal potential generating circuit is not limited to the step-down circuit exemplified in the following description, but may be a booster circuit in general. For example, in an internal potential generation circuit having a level detection circuit such as a booster circuit, the present invention can be applied to a case where a reference potential is switched to give a hysteresis to a detection level and an output internal potential level is switched.

Referring to FIG. 1, DRAM 1000 has an external clock signal ext. CLK, row address strobe signal / RAS, column address strobe signal / CAS, write enable signal / WE, chip enable signal / C
S, a control signal input terminal group 11 for receiving control signals such as a clock enable signal CKE, and address signals A0 to Ai
(I: natural number), a data input / output terminal group 15 for inputting / outputting data, a Vcc terminal 18 for receiving an external power supply potential Vcc, and a ground potential Vs
and a Vss terminal 19 for receiving s.

Signal / CS applied to control signal input terminal group 11 is a signal for instructing that a control signal can be input to the chip. The signal CKE is an external clock signal ext. This signal indicates that input of CLK is enabled.

DRAM 1000 further includes a control circuit 26 for generating an internal control signal for controlling the entire operation of DRAM 1000 in accordance with the control signal, an internal control signal bus 72 for transmitting the internal control signal, and a group of address input terminals 13. An address buffer 30 that receives an external address signal and generates an internal address signal, and a memory cell array 1 having a plurality of memory cells MC arranged in a matrix
00.

Each memory cell MC includes a capacitor for holding data and an access transistor TM having a gate connected to a word line WL corresponding to each row (not shown).

In memory cell array 100, a word line WL is provided for each row of memory cells, and bit lines BL and / BL are provided for each column of memory cells.

Row and column of memory cells are selected by row decoder 40 and column decoder 50 according to an internal address signal transmitted by address bus 74.

According to the output of row decoder 40, corresponding word line WL is selectively activated by word line driver 45. The column selection signal is activated by the column decoder 50. The column selection signal is applied to the column selection line 5
2 to the column select gate 200. The column selection gate 200 responds to a column selection signal to
The sense amplifier 60 for amplifying L / BL data and I /
The O line 76 is selectively connected. I / O line 76 transmits stored data to and from data input / output terminal 15 via read amplifier / write driver 80 and input / output buffer 85. Thereby, storage data is transmitted and received between data input / output terminal 15 and memory cell MC.

When the self-refresh mode is designated by a combination of external control signals, control circuit provides signal ZSRM for instructing the internal circuit that the operation mode is the self-refresh mode, for example.
To generate an internal address for performing the cell refresh operation, etc., and control the self-refresh mode operation of the DRAM 1000.

DRAM 1000 further includes an internal potential generating circuit 2000 for generating an internal power supply potential Vdds supplied to sense amplifier 60, corresponding to the "H" level potential of the bit line pair.

As described above, the DR shown in FIG.
In the configuration of AM1000, internal potential generating circuit 200
In order to solve the problem that the internal power supply potential Vdds supplied from 0 drops transiently at the start of the sensing operation, the sensing operation is delayed. Decoupling capacitance Cp existing on the wiring for supplying the internal power supply potential to amplifier S / A
A configuration is considered in which b is precharged to a potential higher than the potential written as "H" data in the memory cell in advance.

FIG. 2 is a schematic block diagram showing a configuration of such a preboost type internal potential generating circuit 2000.

Conventional internal potential generating circuit 8 shown in FIG.
The difference from the configuration of 000 is that the level of the reference potential VrefM is not a fixed value, but is switched to one of two potential levels Vref1B and Vref2B according to the operation mode.

Referring to FIG. 2, internal potential generating circuit 200
0 is a constant current source 2010 which receives the external power supply potential Vcc and the ground potential Vss and generates two bias potentials VBH and VBL, and a first which generates the first reference potential Vref1 by receiving the bias potential VBH. Vref generation circuit 2020, a second Vref generation circuit 2030 that receives the bias potential VBH and generates a second reference potential Vref2, a bias potential VBL, and a first reference potential V
ref1 and a buffer circuit 2040 that generates a first reference potential Vref1B, and a bias potential VBL
And a buffer circuit 2050 that receives the second reference potential Vref2 and generates a second reference potential Vref2B.
First and second reference potentials Vref1B and Vref
2B in response to the mode selection signal CHG generated by the control circuit 26, the switching circuit 2100 outputs one of them as the reference potential VrefM, and receives the reference potential VrefM and supplies it to the sense amplifier S / A. Voltage conversion circuit 22 for generating internal power supply potential Vdds
00.

Switching circuit 2100 includes an inverter 2110 that receives signal CHG and generates an inverted signal, and a signal CHG.
And the output of the inverter 2110, the first
Receiving the reference potential Vref1B, the signal CHG becomes “H”.
At the level, and becomes conductive when the reference potential VrefM
A transmission gate 2120 that outputs as
Controlled by signal CHG and the output of inverter 2110, receiving second reference potential Vref2B and receiving signal CHG
Transmission gate 2 which is rendered conductive when G is at "L" level and outputs as reference potential VrefM
130.

Voltage conversion circuit 2200 is connected to internal node n1
P-channel MOS transistor TP11 and n-channel MOS
Transistor TN11, p-channel MOS transistor TP12 and n-channel MOS transistor TN12 connected in series between power supply potential Vcc and internal node n11, and n-channel MOS connected between internal node n11 and ground potential Vss Transistor TN13
And between the power supply potential Vcc and the gate of the transistor TN12, the transistors TP11 and TN11
P-channel MOS receiving at its gate the potential of the connection node of
And a transistor TP13.

The gates of the transistors TP11 and TP12 are connected to each other, and the gate of the transistor TP12 is connected to the drain of the transistor TP12.

The gate of transistor TN11 receives reference potential VrefM, and the potential level of the gate of transistor TN12 corresponds to internal power supply potential Vdds.

Transistor TN13 receives signal QON instructing the start of the operation of the voltage conversion circuit.

Here, it is assumed that transistor TN12 and transistor TN11 receiving reference potential VrefM have a gate width W0 and a gate length L0.

FIG. 3 is a circuit diagram for describing the configuration of constant current source 2010 shown in FIG.

Constant current source 2010 includes a p-channel MO connected in series between power supply potential Vcc and ground potential Vss.
S transistor TP21 and n-channel MOS transistor TN21, resistor R1 connected in series between power supply potential Vcc and ground potential Vss, p-channel MOS
A transistor TP22 and an n-channel MOS transistor TN22 are included.

Transistor TP21 and transistor TP
The gates 22 are commonly connected, and the potential levels of these gates are output as the bias potential VBH. On the other hand, the gates of the transistors TN21 and TN22 are also connected to each other, and the potential levels of these gates are output as the bias potential VBL.

Here, the transistors TN21 and TN
22 has a gate width W1 and a gate length L1. At this time, the through current I is supplied to the constant current source 2010.
c is always flowing.

FIG. 4 is a circuit diagram for describing a configuration of first Vref generation circuit 2020 shown in FIG.

The second Vref generation circuit 2030
Has the same configuration as the first Vref generation circuit 2020 except that the number of transistors connected in series is different in order to change the generated reference potential level.

The first Vref generating circuit 2020 includes p-channel MOS transistors TP31, TP32, T connected in series between the power supply potential Vcc and the ground potential Vss.
P33 and TP34.

The gate of transistor TP31 receives bias potential VBH, and the gate of transistor TP34 receives ground potential Vss.

The transistors TP32 and TP3
3 are connected to transistors TP33 and TP3
4 connection nodes.

Transistor TP31 and transistor TP
The potential level of the connection node 32 is the first reference potential Vr
Output as ef1.

As a result of the above connection relationship,
In the transistors TP32 and TP33, a voltage drop due to the channel resistance component occurs, and in the transistor TP34, a voltage drop corresponding to the threshold voltage of the transistor occurs.

When the bias potential VBH is applied to the gate of the transistor TP31, the transistor T
A through current Ic having the same value as the through current IC flowing to the constant current source 2010 flows through P31 to TP34.

As described above, in second Vref generation circuit 2030, for example, first reference potential Vre
In order to generate the second reference potential Vref2 smaller than f1, the first Vref generation circuit 2020 shown in FIG.
Is configured such that the number of transistors connected in series like the transistors TP32 to TP34 is further reduced.

FIG. 5 is a circuit diagram for describing a configuration of first buffer circuit 2040 shown in FIG.

The configuration of the second buffer circuit 2050 is basically the same as that of the second buffer circuit 2050, except that the potential levels of the input reference potential and the output reference potential are different.

Referring to FIG. 5, first buffer circuit 20
40 is a p-channel MOS transistor TP41 connected in series between the power supply potential Vcc and the internal node n41.
And n-channel MOS transistor TN41, p-channel MOS transistor TP42 and n-channel MOS transistor TN42 connected in series between power supply potential Vcc and internal node n41, and internal node n41
TN connected between the power supply and ground potential Vss
43.

The gates of transistors TP41 and TP42 are connected to each other, and these gates are connected to the connection node between transistors TP41 and TN41.

The gate of transistor TN41 receives first reference potential Vref1. The gate of the transistor TN42 is connected to the drain of the transistor TN42, and the potential level of the gate is set to the first reference potential Ver.
Output as fB1.

The gate of the transistor TN43 receives the second bias potential VBL. Here, the transistor T
N43 has a gate width W2 and a gate length L2. At this time, the through current Ib flows through the buffer circuit 2040.

That is, the current Ic having the same magnitude as the current generated by the constant current source 2010 is applied to the first and second Vr.
ef generation circuits 2020 and 2030. In the first and second Vref generation circuits 2020 and 2030, by changing the number of transistors connected in series, respectively, the value of the voltage drop corresponding to the channel resistance is changed, and the two reference potentials Vref1 and Vref2 are respectively changed. appear. These reference potentials Vref1 and Vref
2 respectively, in the first and second buffer circuits 2040 and 2050, the reference potential Vr
ef1B and Vref2B are generated.

Here, the value of the first reference potential Vref1B is equal to the value of the first reference potential Vref1, and the value of the second reference potential Vref2B is equal to the value of the second reference potential Vref2.
Is equal to the value of

The through current Ib of the buffer circuit 2040 is
It is given by the following equation (1). Ib = (W2 / L2) / (W1 / L1) × Ic (1) Therefore, in equation (1), (W2 / L2) / (W
By increasing the value of the ratio (1 / L1), the output of the buffer circuit can be kept stable.

Note that the first reference potential Vref1B and the second
Equation (2) below holds between the reference potential Vref2B and the reference potential Vref2B.

Vref1B> Vref2B (2) Here, the potential written as “H” data in the memory cell is assumed to be equal to the potential Vref2B.

FIG. 6 is a timing chart for explaining a sensing operation in DRAM 1000 using voltage down converter 2000 shown in FIG.

At time t1, the equalizing operation of the bit line pair is stopped, and signal BLEQ changes from "H" level to "L" level.

Subsequently, at time t2, word line WL is selected according to an externally applied address signal, and the potential level of the selected word line WL changes to an active state.

With the activation of word line WL, time t3
, A potential difference corresponding to the data held in the memory cell selected by bit line pair BL and / BL occurs.

At time t4, the start of the operation of the sense amplifier is instructed, and signal SON and signal QON are set to "H".
Change to level. On the other hand, signal ZS0P and signal C
HG changes from “H” level to “L” level.

With the change of the signal CHG, the reference potential Vr
The level of efM changes from the level of potential Vref1B to the level of potential Vref2B.

Therefore, during the period before the start of the sensing operation, signal SON is at "L" level,
The signal ZS0P is at "H" level, and the reference potential Vre
fM is the first reference potential Vref1B. In other words, more charge is stored in the decoupling capacitor Cpb by the amount represented by the following equation (3) than in the case where the reference potential VrefM is Vref2B, before the start of sensing.

Cpb × (Vref1B−Vref2B) (3) At time t4, the signal S0N becomes “H” level,
When the signal ZS0P becomes "L" level and the start of the sensing operation is instructed, the charge stored in the decoupling capacitance Cpb starts charging the charge / discharge capacitance Cb existing in the bit line pair.

After the start of the sensing operation at time t4, since more charge exists in the decoupling capacitance Cpb by the amount shown in the above equation (3), the level of the internal power supply potential Vdds level at the beginning of the sensing starts. The transitional drop is suppressed.

After time t4, the value of reference potential VrefM is the second reference potential Vref2B. Therefore, voltage conversion circuit 2200 supplies charges to sense amplifier S / A such that the level of internal power supply potential Vdds becomes the same as the level of potential Vref2B.

At time t5, the word line is deactivated, and thereafter, the sense amplifier drive signals S0N and / S0P are also deactivated. In response, signal CHG also returns to the “H” level, and the value of reference voltage VrefM becomes first reference potential Vref1B again.

At time t6, signal BLEQ is activated, and equalization of the bit line pair is started.

At time t7, the next cycle starts. In this case, the time from time t1 to time t7 is
The cycle time becomes tRC.

As described above, since the level of "H" data written in the memory cell is equal to potential Vref2B, the above operation allows the memory cell to operate even when the reference potential is switched in two stages. , "H" level data having a desired level is written.

Further, since the transient lowering of the internal power supply potential Vdds is reduced, the internal potential generating circuit 2
000 finally raises the level of the internal power supply potential Vdds until it becomes equal to the reference potential Vref2B.

Here, the through current Ipa flowing through the internal potential generating circuit 2000 shown in FIG. 2 is estimated as follows.

First, in the constant current source 2010, 2 × Ic
, A 2 × Ic through current is generated in the first and second Vref generating circuits 2020 and 2030, and a 2 × Ib through current is generated in the first and second buffer circuits 2040 and 2050. Occurs.

Therefore, a through current of only the following equation (4) is generated in total.

Ipa = 2 × Ib + 4 × Ic (4) In other words, the above equation (4) indicates that the internal potential while the signal QON is at the “L” level and the internal potential generating circuit 2000 is off is Current Ipa flowing through generation circuit 2000
Is represented.

As described above, in order to reduce the current Iccsr consumed during the refresh operation and the standby current Iccs, it is desirable that the through current Ipa is as small as possible.

As a result, the current Ib flowing through the buffer circuit
Is set to a value such that the parasitic capacitance Cd present at the output node of the buffer circuit can be charged within a predetermined time immediately after power-on. Here, specifically, for example, the value of the through current Ib in the buffer circuit is designed to be about several μA.

As described with reference to FIG. 2, reference potential Vref
Switching of M causes buffer circuits 2040 and 2050 to operate at reference potential Vre in voltage conversion circuit 2200.
The gate capacitance of the transistor receiving fM (transistor TN11) must be charged and discharged.

When the sensing operation is performed for a fixed cycle time tRC, the charge / discharge current Icd is calculated by the following equation (5).
Is represented by Icd = C0 × W0 × L0 × (Vref1B−Vref2B) / tRC (5) Here, C0 means a gate capacitance per unit area. Potential conversion circuit 2 generally receiving reference potential VrefM
The gate area W0 × L of the transistor TN11 in 200
0 is set to a large value. Furthermore, in a DRAM capable of high-speed operation represented by a synchronous DRAM (hereinafter, SDRAM), the charge / discharge current Icd is a value that cannot be ignored because the cycle time tRC is shorter than in the conventional DRAM.

FIG. 7 is a diagram for explaining a transient change in the reference potential VrefM caused by such a charge / discharge current Icd.

Referring to FIG. 7, first reference potential Vref
The levels of 1B and the second reference potential Vref2B gradually change until the charge / discharge current Icd and the current driving power of the buffer circuits 2040 and 2050 are balanced. Therefore, the first reference potential Vref1B becomes the desired value Vr
ef1 and a value smaller than the second reference potential V
ref2B becomes a value larger than the desired value Vref2.

If the cycle time tRC is sufficiently short,
As shown in FIG. 7, from the desired potential level to the reference potential V
ref2B becomes a steady state at a value shifted by the voltage deviation dV. The same applies to the reference potential Vref1B.

Such buffer circuits 2040 and 2
Reference potentials Vref1B and Vr output from 050
In order to prevent the level of ef2B from fluctuating, it is also possible to set the through current Ib generated in the buffer circuits 2040 and 2050 constantly to be large. However, such setting of the through current Ib is not preferable from the viewpoint of reducing the currents Iccsr and Iccs.

After all, the currents Iccsr and Ic
Based on the set value of cs, the value of the through current Ib must be set to the maximum allowable value.

Therefore, the structure shown in FIG. 2 alone is not sufficient to suppress a decrease in the potential level in the transient state of output potential Vdds from internal potential generating circuit 2000 and to reduce currents Iccsr and Iccs. Will be.

FIG. 8 shows an internal potential generating circuit 24 capable of reducing currents Iccsr and Iccs as described above.
FIG. 2 is a schematic block diagram for explaining a configuration of the 00.

The structure of internal potential generating circuit 2400 is similar to that of FIG.
Is different from the configuration of internal potential generating circuit 2000 shown in FIG.
This is a configuration controlled by The other points are the same as those in the configuration shown in FIG. 2, and therefore, the same portions are denoted by the same reference characters and description thereof will not be repeated.

FIG. 9 is a circuit diagram for describing a configuration of first buffer circuit 2042 shown in FIG.

The basic configuration of the second buffer circuit 2052 is also the same except that the input potential and the output potential are different.

First buffer circuit 2042 is connected between power supply potential Vcc and internal node n51 in series by p.
A channel MOS transistor TP51 and an n-channel MOS transistor TN51, and a p-channel MO connected in series between power supply potential Vcc and internal node n51.
S transistor TP52 and n channel MOS transistor TN52, internal node n51 and ground potential Vss
And an n-channel MOS transistor TN5 connected between internal node n51 and ground potential Vss and receiving signal PUM at its gate.
4 is included.

The gates of transistors TP51 and TP52 are connected to each other, and these gates are connected to a connection node between transistor TP51 and transistor TN51.

The gate of the transistor TN51 receives the first reference potential Vref1, and the gate of the transistor TN52 is connected to the drain of the transistor TP52. The gate potential of the transistor TN52 is output as the first reference potential VrefB1.

Here, it is assumed that the transistor TN53 has a gate width W2 and a gate length L2.

On the other hand, transistor TN54 has a gate width W3 and a gate length L3. With the configuration as shown in FIG. 9, the buffer circuit 2
040 can be controlled.

FIG. 10 is a schematic block diagram showing a configuration of PUM signal generation circuit 3000 for generating signal PUM shown in FIG. The PUM signal generation circuit 3000
For example, it is included in the control circuit 26 shown in FIG.

Referring to FIG. 10, PUM generating circuit 300
0 is a delay circuit 3010 receiving the signal SON, and an inverter 3020 receiving and inverting the output of the delay circuit 3010.
, NAND circuit 3030 receiving signal S0N and the output of inverter 3020, delay circuit 3050 receiving signal ZS0P, inverter 3060 receiving and inverting the output of delay circuit 3050, and NAND circuit receiving signal ZS0P and the output of inverter 3060 3070,
Upon receiving outputs of NAND circuits 3030 and 3070,
And a NAND circuit 3100 that outputs signal PUM.

PUM generation circuit 30 as shown in FIG.
With the configuration of 00, the signal PUM goes to the “H” level for a period determined by the delay circuits 3010 and 3050 based on the start and end of sensing. Accordingly, through current Ib of buffer circuit 2040 and buffer circuit 2050 shown in FIG. 9 increases, and the driving capability of the buffer increases. As a result, the reference potential Vref1
The charge / discharge current Icd generated by switching between B and Vref2B falls within the range of the driving capability of the buffer,
Level fluctuations of the reference potential Vref1B and the reference potential Vref2B can be suppressed.

FIG. 11 is a timing chart for describing the operation of generating the reference potential of internal potential generating circuit 2400 shown in FIG.

At time t1, signal BLEQ attains an inactive state, and at time t2, signal S0N and signal ZS0P each change to the active state. on the other hand,
The reference potential VrefM changes from the first reference potential Vref1B to the second reference potential Vref2B.

In response, signal PUM is also activated for a predetermined period, and the value of through current Ib in buffer circuits 2040 and 2050 from current amount Ibl to current amount Ibh only during a period in which signal PUM is active. To rise.

Further, at time t3, in response to signal S0N and signal ZS0P being inactivated, signal PUM is again activated for a predetermined time.

On the other hand, reference potential VrefM changes from second reference potential Vref2B to first reference potential Vref1B.

At this time, buffer circuits 2040 and 2050 are in the switching period of reference potential VrefM.
Through current Ib rises from level Ibl to level Ibh.

By reducing the through current Ib during the period when the signal PUM is at the “L” level to the minimum value Ibl necessary for charging the parasitic capacitance Cd at the time of power-on, the signal PUM is reduced.
The value of the through current Ib can be set lower than when the buffer circuit is not controlled by the UM. As a result, especially when cycle time tRC is long, buffer circuits 2040 and 2050 are almost always used.
Is at the level Ibl, the average value of the through current Ib is suppressed.

Therefore, with the configuration shown in FIG. 8, currents Iccsr and Iccs can be reduced.

In the above example, the signals for determining the period during which signal PUM is at the "H" level are activation signals S0N and ZS0P of the sense amplifier. However, other signals related to row-related operations are used. Various signals can be used.

For example, a bit line which is an internal signal directly corresponding to a control signal / command externally applied to activate a row-related circuit, or which is active while a sense amplifier is inactive. It is also possible to use an equalizing signal BLEQ or the like.

[Second Embodiment] The configuration of an internal potential generating circuit of the second embodiment is basically the same as the configuration of the internal potential generating circuit of the first embodiment shown in FIG.

However, the timing at which signal PUM becomes active is different. In the configuration of internal potential generating circuit 2000 of the first embodiment shown in FIGS. 8 to 10, the timing at which signal QON instructing activation of voltage conversion circuit 2200 attains “H” level, and activation of sense amplifiers Are activated in synchronization with the activation timing of the signal S0N instructing.

However, generally, the voltage conversion circuit 2
It takes a little time from the activation of 200 to the actual operation. Therefore, the signal QON may be activated ("H" level) before the start of sensing.

PUM Signal Generating Circuit 400 of Second Embodiment
At 0, the timing at which the signal PUM is generated is synchronized with the signal QON, so that the signal PUM is activated at a timing before the reference potential VrefM is switched.

FIG. 12 shows a PUM according to the second embodiment of the present invention.
FIG. 3 is a schematic block diagram illustrating a configuration of a signal generation circuit 4000. The difference from the configuration of the PUM signal generation circuit 3000 of the first embodiment shown in FIG.
Since other configurations are the same, the same portions are denoted by the same reference characters and description thereof will not be repeated.

FIG. 13 is a timing chart for explaining the operation of the internal potential generating circuit when PUM signal generating circuit 4000 as shown in FIG. 12 is used.

At time t1, signal BLEQ is inactivated, and at time t2, signal QON is activated and voltage conversion circuit 2200 is activated. At time t2, signal CHG transitions to the “L” level, and reference potential VrefM also switches from first reference potential Vrer1B to second reference potential Vref2B. In response, signal PUM is also activated for a predetermined period, and buffer circuit 20
The values of through current Ib at 40 and 2050 are also increased from level Ibl to level Ibh. Thereafter, at time t3, signal S0N and signal ZS0P are activated to activate the sensing operation.

With this configuration, in a circuit configuration in which a plurality of reference potentials are generated, it is possible to suppress potential fluctuation due to interference between the reference potentials.

Therefore, for example, when the internal potential generating circuit of the second embodiment is used for supplying a drive potential to a sense amplifier of a DRAM, the sense amplifier starts consumption of internal power supply potential Vdds in the sense operation. Since the voltage conversion circuit 2200 has already started normal operation, the time required for the voltage conversion circuit 2200 to start charge supply so that the internal power supply potential Vdds matches the second reference potential Vref2B is reduced. Is done. As a result, in addition to the effects described in the first embodiment, the transient fluctuation of the power supply potential Vdds level is further suppressed, and the sensing time can be reduced.

[Third Embodiment] In the structure shown in the first and second embodiments, when the internal potential generating circuit is used in a DRAM, the through current of the system is suppressed in both the standby state in the normal mode and the self-refresh mode. It is possible.

However, in the normal mode, there is a case where the through current Ipa is not important to the whole power consumption because of the current components consumed by other components. On the other hand, in the self-refresh mode, the cycle time tRC is sufficiently long and the charge / discharge current Icd is sufficiently small, so that it may not be necessary to increase the buffer capacity.

Therefore, it is possible to control the buffer capacity depending on whether the DRAM is in the self-refresh mode.

FIG. 14 is a schematic block diagram showing a configuration of an internal potential generating circuit 2600 according to the third embodiment of the present invention.

The structure of reference potential generating circuit 2400 of the first embodiment shown in FIG. 8 is such that buffer circuits 2044 and 2054 are controlled by signal ZSRM indicating that the self-refresh mode is designated. In other respects, the configuration is the same as that shown in FIG. 8, so that the same portions are denoted by the same reference characters and description thereof will not be repeated.

FIG. 15 is a circuit diagram for illustrating a configuration of buffer circuit 2044 according to the third embodiment of the present invention.

The only difference from the structure of the buffer circuit of the first embodiment shown in FIG. 9 is that the gate of transistor TN54 is controlled not by signal PUM but by signal ZSRM. Have the same reference characters allotted, and description thereof will not be repeated.

FIG. 16 is a timing chart for explaining the operation of the internal voltage generating circuit according to the third embodiment of the present invention. In the normal operation mode, the signal ZSRM is "H".
Level and buffer circuits 2044 and 2054
Is controlled to a large level Ibh.

When the self-refresh mode is entered, signal Z
SRM attains the “L” level, and through current Ib in buffer circuits 2040 and 2050 is at low level Ibl.
Is controlled.

Such a configuration is particularly effective when the system requirements for the value of the standby current Iccs are not severe.

In the above description, the present invention has been described as a configuration of an internal potential generating circuit for supplying an internal power supply potential to the sense amplifier S / A in the circuit configuration of the DRAM, but such a configuration is more generally extended. It is possible to That is, the configuration of the internal potential generation circuit or the configuration for generating the reference potential according to the present application is not limited to the configuration of the internal potential generation circuit that generates two levels of potentials as the internal potential.

For example, in a system in which an output signal from an internal potential generating circuit, which is generated by switching a plurality of intermediate potentials, is received by the gate of a MOS transistor in a certain circuit,
The present invention described above can be applied to suppressing the fluctuation of the intermediate potential itself due to the switching operation and suppressing the through current in the internal potential generating circuit or the configuration for generating the reference potential. is there.

The embodiments disclosed this time are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[0145]

According to the semiconductor device of the present invention,
Even when the level of the reference potential output from the reference potential generation circuit is switched according to the operation mode, it is possible to suppress the potential fluctuation due to the interference between the reference potentials.

In the semiconductor device according to the third and fourth aspects, the potential supplied to the internal circuit can be prevented from transiently deviating from a desired value every time the operation mode is switched, and the increase in power consumption can be suppressed. it can.

In the semiconductor device according to the fifth to ninth aspects, even when the output level output from the internal potential generating circuit is switched according to the operation mode, the output level can be prevented from being transiently deviated from a desired value. In addition, an increase in power consumption can be suppressed.

According to a tenth aspect of the present invention, in the dynamic semiconductor memory device, an active state of the sense amplifier is controlled.
It is possible to suppress a transient shift of the drive potential from the desired value when the inactivity is switched, and to suppress an increase in power consumption.

The semiconductor device according to the eleventh aspect can reduce power consumption in the self-refresh mode.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram showing an overall configuration of a DRAM 1000 according to a first embodiment of the present invention.

FIG. 2 is a schematic block diagram showing a configuration of a preboost type internal potential generation circuit 2000.

FIG. 3 is a circuit diagram for describing a configuration of constant current source 2010 shown in FIG.

FIG. 4 is a diagram showing a first Vref generation circuit 202 shown in FIG. 2;
FIG. 3 is a circuit diagram for explaining a configuration of a zero.

FIG. 5 is a circuit diagram for describing a configuration of first buffer circuit 2040 shown in FIG.

FIG. 6 shows a DR using the step-down circuit 2000 shown in FIG. 2;
6 is a timing chart for explaining a sensing operation in AM1000.

FIG. 7 shows a reference potential Vref based on a charge / discharge current Icd.
FIG. 9 is a diagram for explaining a transient change occurring in M.

FIG. 8 is a schematic block diagram for describing a configuration of internal potential generation circuit 2400.

FIG. 9 is a circuit diagram illustrating a configuration of a first buffer circuit 2042.

FIG. 10 is a schematic block diagram showing a configuration of a PUM signal generation circuit 3000.

FIG. 11 is a timing chart for describing a generation operation of a reference potential of an internal potential generation circuit 2400.

FIG. 12 is a schematic block diagram illustrating a configuration of a PUM signal generation circuit 4000 according to the second embodiment of the present invention.

FIG. 13 is a timing chart for explaining the operation of the internal potential generation circuit when the PUM signal generation circuit 4000 is used.

FIG. 14 is a schematic block diagram showing a configuration of an internal potential generation circuit 2600 according to a third embodiment of the present invention.

FIG. 15 shows a buffer circuit 20 according to the third embodiment of the present invention.
FIG. 4 is a circuit diagram for explaining a configuration of the control unit.

FIG. 16 is a timing chart for explaining an operation of the internal voltage generation circuit according to the third embodiment of the present invention.

FIG. 17 is a schematic block diagram illustrating a configuration of a conventional internal potential generation circuit 8000.

[Explanation of symbols]

11 control signal input terminal group, 13 address signal input terminal group, 15 data input / output terminal group, 18 external power terminal, 19 external ground terminal, 26 control circuit, 3
0 address buffer, 40 row decoder, 45 word line driver, 50 column decoder, 52 column selection line, 60 sense amplifier, 72 internal control signal bus, 7
4 address bus, 76 data bus, 80 read amplifier / write driver, 85 input / output buffer, 100 memory cell array, 200 column selection circuit, 1000 DA
RM, 2000 internal potential generation circuit, 2010 constant current source, 2020, 2030 Vref generation circuit, 204
0, 2042, 2044, 2050, 2052, 205
4 Buffer circuit, 2100 switching circuit, 2110 inverter, 2120, 2130 transmission gate, 2200 voltage conversion circuit, 3000, 4000
PUM signal generation circuit.

Claims (11)

[Claims] 1. A semiconductor device, comprising: a reference potential generation circuit receiving a power supply potential, selectively outputting one of a plurality of reference potentials according to an operation mode, and outputting the selected reference potential. A plurality of potential generation circuits for respectively generating the plurality of reference potentials and increasing a current driving capability for at least a predetermined period in accordance with the switching of the operation mode; and an output of the plurality of potential generation circuits. And a switching circuit that receives the reference potential generating circuit and outputs the signal in response to the operation mode. The internal circuit further operates based on the output of the reference potential generating circuit. 2. Each of the potential generation circuits includes a reference potential generation circuit that generates a reference potential corresponding to the generated reference potential, and a buffer circuit that outputs the reference potential according to the reference potential. A buffer circuit that receives an output node, receives the power supply potential, and drives a potential level of the output node to the reference potential level in accordance with the reference potential; 2. The semiconductor device according to claim 1, further comprising: a current control circuit that switches a current value flowing through the drive circuit in an active state for at least the predetermined period. 3. A path of a current flowing through the drive circuit includes first and second paths parallel to each other, and the current control circuit is in an active state for the predetermined period according to switching of the operation mode. 3. The semiconductor device according to claim 2, further comprising: a pulse signal generation circuit configured to generate a pulse signal; and a switch circuit provided on the second path, which is turned on in response to activation of the pulse signal. 4. 4. A current signal flowing through the drive circuit includes a first path and a second path parallel to each other, and the current control circuit generates a mode signal according to the operation mode. 3. The semiconductor device according to claim 2, further comprising: a circuit; and a switch circuit provided on the second path, which is turned on in response to activation of the mode designation signal. 4. 5. A semiconductor device, comprising: an internal circuit driven by an internal potential; a wiring for transmitting the internal potential to the internal circuit; and a first potential and a first potential receiving a power supply potential. An internal potential generating circuit that selectively switches one of the second potentials higher than the second potential to an internal potential and outputs the selected internal potential to the wiring according to an operation mode of the internal circuit; Switches and outputs first and second reference potentials corresponding to the first and second potentials, respectively, in accordance with the operation mode, and performs current drive for at least a predetermined period in accordance with the operation mode switching A reference potential generation circuit for increasing the capacity; and a voltage conversion circuit receiving an output of the reference potential generation circuit at an input node and generating the internal potential. Having a MOS transistor for coupling the input node, the semiconductor device. 6. The reference potential generation circuit, comprising: a first reference potential generation circuit for generating a first reference potential corresponding to the first reference potential; and a second reference potential generation circuit for generating a second reference potential corresponding to the second reference potential. A second reference potential generation circuit that generates a reference potential, a first buffer circuit that outputs the first reference potential according to the first reference potential, and a second buffer according to the second reference potential. A second buffer circuit that outputs the second reference potential, wherein each of the first buffer circuit and the second buffer circuit receives an output node, and receives the power supply potential, and in the active state, Is increased at least for the predetermined period after the transition of the operation mode, whereby the potential level of the output node is set to the potential level of the output node according to the corresponding one of the first and second reference potentials. 1st and 1st And a drive circuit for driving to a corresponding one of the reference potentials, receiving an output of the first and second buffer circuits and selectively outputting one of them according to the operation mode. 6. The semiconductor device according to claim 5, further comprising a switching circuit that performs switching. 7. A path of a current flowing through the driving circuit includes first and second paths parallel to each other, wherein the driving circuit is provided on the second path, and after a transition of the operation mode. 7. The semiconductor device according to claim 6, further comprising a switch circuit that is turned on in response to activation of a pulse signal that maintains an active state during the predetermined period. 8. A path of a current flowing through the drive circuit includes first and second paths parallel to each other, and the current control circuit is provided on the second path and specifies the operation mode. 7. The semiconductor device according to claim 6, further comprising a switch circuit that is turned on in response to activation of the mode designation signal. 9. The voltage conversion circuit changes from an inactive state to an active state prior to switching of the operation mode.
The semiconductor device according to claim 5. 10. The internal circuit includes: a control circuit that controls an operation of the internal circuit in accordance with a control signal supplied; a memory cell array including a plurality of dynamic memory cells arranged in a matrix; A plurality of bit line pairs provided corresponding to a column of cells; a memory cell selection circuit for selecting the memory cell in accordance with an address signal; and a selection in accordance with data held in the selected memory cell. A plurality of sense amplifiers for amplifying the potential of the bit line pair coupled to the memory cell, and a sense amplifier drive circuit controlled by the control circuit to control supply of the internal potential to the sense amplifier. 6. The semiconductor device according to claim 5, wherein switching of the operation mode corresponds to switching of a sense operation by a sense amplifier between active and inactive. 11. A reference potential generation circuit, comprising: a first reference potential generation circuit for generating a first reference potential corresponding to the first reference potential; and a second reference potential generation circuit for generating a second reference potential corresponding to the second reference potential. A second reference potential generation circuit that generates a reference potential, a first buffer circuit that outputs the first reference potential according to the first reference potential, and a second buffer according to the second reference potential. A second buffer circuit for outputting the second reference potential, wherein each of the first buffer circuit and the second buffer circuit receives an output node, and a current flowing therethrough upon receiving the power supply potential By reducing the value in response to the designation of the self-refresh mode, the potential level of the output node is increased in accordance with one of the first and second reference potentials corresponding to the corresponding one of the first and second reference potentials. Second reference phone And a drive circuit for driving to a corresponding one of the potential levels, and receiving the outputs of the first and second buffer circuits and selectively outputting one of them according to the operation mode. A control circuit that controls the operation of the internal circuit according to a control signal supplied thereto; a memory cell array including a plurality of dynamic memory cells arranged in a matrix; and the memory cell. A plurality of bit line pairs provided corresponding to the columns, a memory cell selection circuit for selecting the memory cell according to an address signal, and a memory cell selection circuit selected according to data held in the selected memory cell. A plurality of sense amplifiers for amplifying the potential of the bit line pair to which the memory cells are coupled; Controlling the and a sense amplifier drive circuit, a semiconductor device according to claim 5, wherein.