JP2001034649A - Clock distributing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate the need to remove a timing error accompanying the design alteration of conventional repetitive and redundant data lines by inserting an element for delay compensation into a specified data line after a clock distributing method was implemented. SOLUTION: A step C1 consists of a step C11 for judging whether or not a data line is specified, a delay calculation step C12, and a modular step 'delay insertion'. The delay insertion step consists of an element insertion step C13 for delay compensation including a necessary net list and arrangement altering process and a process step C14 for equally-delayed wiring. After all clocks end, the update net list of the corrected specific data line is transferred to an input file L3. Thus, the element for delay compensation is inserted into the specified data line after conventional clock tree synthesis(CTS). The element for delay compensation can be selected out of three, i.e., a buffer or inverter, a flip-flop circuit(F/F) of the same edge, and an F/F of the opposite edge.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of distributing a clock signal to a semiconductor integrated circuit in a tree shape, and more particularly, to a method of distributing a clock signal to a semiconductor integrated circuit.
The present invention relates to a process for removing timing errors of a flip-flop circuit (hereinafter, referred to as F / F).

[0002]

2. Description of the Related Art A semiconductor integrated circuit is subjected to a process abbreviated as CTS (Clock Tree Synthesis) to distribute clock signals in a tree-like manner and to input clock signals to all F at the same time within an allowable error. Design the supply clock tree for the / F circuit.

The conventional CTS process will be described with reference to a flowchart shown in FIG. In the first step, execution conditions are interactively input from a keyboard (step A1). Next, initial circuit connection information (netlist)
Is read from the file L1, the F / F is grouped, the variation in load capacity is minimized, and the number of buffers, inverters, and fanouts to be inserted is determined (step A21). ), Change of the netlist, and insertion of a buffer and an inverter based on the arrangement (step A22), and equi-delay wiring by balance wiring and bypass wiring (step A23). The configured block process (step A2) is performed. The result of step A2 is transferred to L2 as a conventional netlist file after CTS. Step A3 is a process for judging whether or not the processing of step A2 has been completed for all clock trees. If the result is Yes, a report is output (step A4) to complete the CTS process.

If the result of step A3 is No, CT
Until the S process is completed, the loop process is repeatedly performed on the incomplete clock lines.

In step A1, the condition values of the respective items described in the following execution condition 1 are interactively input. The item of the execution condition 1 is designation of execution of the gated clock,
Clock tree root instance name, clock net name, buffer insertion level, buffer type, output buffer capacity restriction of inserted buffer, capacity restriction of each divided terminal when multiple pins are separated , Number of buffers to be inserted, tree structure generated for each instance,
Element block for delay adjustment inserted when performing gated CTS, buffer type of route instance, prefix of added instance name and net name, terminal name connected to power supply, power supply net connected to terminal Each item is a name, a cost file used for wiring, and a map file used for separating multiple pins of a high-drive buffer.

FIG. 18 is a flowchart of an integrated circuit (hereinafter abbreviated as LSI) design process. Functional design (step B1), logical design (step B3),
Then, the logic circuit processed by the logic synthesis (step B4) is processed as a floor plan (step B5), and the automatic arrangement of the elements is determined by step B6.
After the TS (step B7) and the automatic wiring of the LSI (step B8), delay verification (step B9) is performed.

The delay verification is a process for confirming a stable F / F data storage operation. Data with stable F / F
In order to perform the data storage operation, two signal inputs of data and a clock without a timing error are required. The result of the delay verification (step B9) is divided into the following two options depending on the judgment (step B10).

If the judgment (B10) is OK, the LSI F
For all / F, the stable data storage operation state is confirmed, and the layout is verified (step B11) and the mask data creation processing (step B12) is performed.
End the design process.

When the judgment (B10) is NG, all F /
Until a stable data storage operation is confirmed for F, the data line is replaced by a loop of cell replacement (step B21), automatic placement (step B22), and automatic wiring (step B23). It is necessary to repeat the correction.

It is rare that the timing error is removed in the first trial process of the loop process. Because of the attendant delays due to trial modification of the circuit, often a NG consecutive result decision (step B10) follows and several rounds of
Usually, it is usually confirmed that the timing error has been removed for the first time after the repetition processing. The cost increase for performing such repetitive processing a few times amounts to about a few weeks in terms of design time.

FIG. 19 shows an example of a logic circuit which is a component of an LSI. In particular, the F / F 14 (R
The input signal of EGB) and its path will be described. CL
The OCK signal sequentially propagates through the following three transmission paths and is input to the F / F 14 as a clk signal. The three transmission lines are a wiring line 11 from the clock terminal to the input terminal of the first buffer (or inverter), and a buffer (or an inverter) which is a component element of a clock tree between the lines 11 and 13. And the wiring line 13 connecting the output terminal of the final delay element of the clock tree and the clock input terminal of the F / F 14.

Referring to FIG. 19, the clock terminal and the data
2 signals (CLOCK and DATA) applied from the data terminal
Is a signal which is synchronized and has no timing error. The preceding circuit that outputs the DATA signal is C
Under the conditions of FIG. 19 that are not included in the processing area of the TS, the line 12 is referred to as a “data line serving as a cut line of the CTS” for convenience. In the CTS, since a buffer or an inverter is not inserted except for the clock line, the DATA signal is supplied from the data terminal to the F terminal.
/ F14 is input to the data input terminal D under a conduction condition.

FIG. 20 shows a timing chart. T1
0 indicates the delay of the clk signal due to the clock tree circuit element. In order for the F / F 14 to stably store the input DATA signal at the rising time T11 of the clk signal, during the elapse of the setup time and the hold time, which is the operation characteristic of the F / F, the DATA signal at the time T11. The level must not fluctuate. Clk signal delay T
If 10 is sufficiently small, F / F14 (REGB) is DA
The TA signal can be stored stably and transferred to the output terminal Q. FIG. 20 is a timing chart illustrating a state in which the synchronized clk signal and DATA signal are input and the F / F 14 can perform a stable data storage operation.

FIG. 21 is a timing chart showing another operation of the F / F 14 (REGB). Clock tree
As a result, the clk signal is input with a large delay T20, and the cut level of the DATA signal at the rising time T21 is fluctuating with respect to any of the signals (C) and (D), so that the F / F 14 has stable data. This is not a condition for performing the storing operation. Referring to the flowchart of FIG.
The result of the delay verification (step B9) is
In the case of 10), the case is processed to the option of NO.

[0015]

SUMMARY OF THE INVENTION An object of the present invention is to provide a CT system.
The object of the present invention is to establish a clock distribution method that does not include a timing error after the processing of S, thereby eliminating the need for the conventional repetition and the work of removing the timing error accompanied by the design change of the redundant data line.

[0016]

A means of the clock distribution method of the present invention is to insert a delay compensation element into a designated data line after the conventional CTS.

The selection of the delay compensating element to be inserted into the designated data line is made up of a buffer or an inverter, an F / F of the same edge, and an F / F of the opposite edge. Alternatives are possible.

[0018]

Next, embodiments of the present invention will be described with reference to the drawings.

<< First Embodiment >> FIG. 1 shows a clock distribution method according to a first embodiment of the present invention, in which the same amount of delay compensation elements are used to compensate for the clock delay of the F / F. To
This shows a flowchart of CTS to be inserted into the designated data line. Each step, A1, A2 (consisting of A21, A22 and A23), A3, A4, input / output files, L1, and L2 are the same as those shown in FIG. Step C1 is a step C11 of determining whether or not a data line is designated, and a delay calculation step C.
12 and the modular step "delay insertion" shown in FIG. The delay inserting step shown in FIG. 2 includes a delay compensating element inserting step C13 including a necessary netlist and arrangement change processing, and an equal delay wiring processing step C14. After the completion of all clocks, the updated netlist of the corrected designated data line is transferred to the input file L3.

In step A1, the condition values described in the following execution condition 2 are interactively input. Execution condition 2
Are the specification of the execution of the gated clock, the name of the instance which is the root of the clock tree, the name of the clock net, the level at which the buffer is inserted, the type of the buffer,
The capacity limitation of the output terminal of the buffer to be inserted, the capacity limitation of each divided terminal when multiple pins are separated, the number of buffers to be inserted, the tree structure generated for each instance, and the insertion when the gated CTS is executed. Element block for delay matching, buffer type of route instance, prefix of instance name and net name to be added, name of terminal connected to power supply, name of power supply net connected to terminal, cost file used for wiring, cost Each item is a map file used for separating multiple pins of the driving buffer and a data line specification (item C2) for inserting a delay.

Execution condition 2 is equivalent in form to execution condition 1 with the addition of the last item C2 of the above list.

FIG. 3 shows an example of a logic circuit obtained by designating the designated data line 21 in the item C2 of the execution condition 2. A line 11 connected to a clock terminal;
Four buffers shown and connected between the input lines 13 of F14 (REGB) are insertion delay elements based on CTS. Referring to the timing chart of FIG.
The operation of the logic circuit will be described focusing on the F / F (REGB). The delay T30 between dat by the delay compensation element 22 is equal to the delay T20 by the clock tree.
Therefore, at the rising time T21 of the clk signal, the F / F 14 (REGB) can stably store the input dat signal.

Timing error in the present logic circuit
In order to remove the clock tree and the clock tree, simply insert the delay compensating element 22 into the designated data line 21.
No change is made to the data lines other than the designated data line 21.

<< Second Embodiment >> FIG. 5 shows a second embodiment of the clock distribution method according to the present invention, in which a clock delay compensation F / F is inserted into a designated data line.
5 shows a flowchart of S. The input in step A1 is "data having a designation for inserting a F / F into the data line.
Designation of insertion of F / F for taking in data at the same edge as the F / F whose data line is the input ”and“ F / F to be inserted ”
Designation of F ”(collectively symbolized as D2)
In execution condition 3 obtained by adding to execution condition 1.
That is, the execution condition 3 includes designation of execution of a gated clock, an instance name serving as a root of a clock tree, a clock net name, a level at which a buffer is inserted,
Type of buffer, capacity limit of output terminal of buffer to be inserted, capacity limit of each divided terminal when multiple pins are separated, number of buffers to be inserted, tree structure generated for each instance, execution of gated CTS Element block for delay adjustment inserted at the time, buffer type of route instance, prefix of instance name and net name to be added, terminal name connected to power supply, power supply net name connected to terminal, used for wiring Cost file,
Map file used for multi-pin release of high-drive buffer, F / F insertion for data line Insertion of F / F for taking in data at the same edge as input F / F where data line specified is inserted (Item D2), F / F to be inserted
(Item D2).

Step D1 is a step of determining the F / F in D2.
To determine whether there is a designated data line for inserting
1), delay calculation (step D12), and "F / F
It consists of an “insert” step. The other steps shown in FIG. 5, A2 (including A21, A22 and A23), A3, A4, input / output files, L1, L2, and L3 are the same as those in FIG.
Each is the same.

The input / output F / F described in D2 above is designated as an input F / F, and the input / output F / F taking in data at the same edge is referred to as an "insertion F / F". , Respectively.

FIG. 6 shows a flowchart of the subroutine step "F / F insertion". D12 is “input F /
"F" indicates the arrangement of "insertion F / F" for fetching data at the same edge and the update processing of the netlist. There are the following two combinations of the above-mentioned F / Fs that take in data at the same edge.
/ F ", when both store data with a rising clock signal, and in the other case, when both store data with a falling clock signal.

The determination (step D14) determines whether or not the intermediate branch point of the clock tree can be selected while avoiding the area occupied by the components (buffers or inverters) of the clock tree.

If the determination in step D14 is Yes,
The clock branching process for the "insertion F / F" minimizes both the increase in the wiring capacity and the variation in the propagation delay of the clock signal due to the insertion of the F / F at the output end of the buffer or the inverter. The point is to select This is Step D15.

If the determination in step D14 is No, F /
It is necessary to determine on the connection wiring between two components of the clock tree adjacent to each other, with the point of minimizing both the increase in the wiring capacity and the increase in the variation in the propagation delay of the clock signal due to the insertion of the F as a branch point. Becomes The step of performing this processing is D16. Step D17
Relates to a process of designing a clock signal wiring to be input to the “insert F / F”.

FIG. 7 shows that in the second embodiment, among the execution conditions 3, the "insertion F / F" of D2 is an F / F 33 for storing data with a rising clock signal, and designated data. FIG. 4 shows an example of a circuit diagram obtained by applying a condition to be inserted into the pipeline 31.

Referring to the timing chart of FIG. 8, the circuit operation of FIG. 7 will be described, particularly focusing on the F / F 14 (REGB). T20 is a delay caused by a clock tree,
T40 indicates the delay of signal clkA due to the partial clock tree element between lines 11-32. Due to the clock line wiring process (D17) of the F / F insertion process chart (FIG. 6), T40 is equal to half of T20. As a result, between the input signals of the F / F 14 (REGB) (clk
And dat) do not have a timing error.
F "14 (REGB) can perform a stable data storage operation. By observing the timing chart, before the placement of the "insertion F / F" 33, due to the timing error between the input signals (clk and DATA), F / F
F14 could not execute data storage.

FIG. 9 shows that in the second embodiment, among the execution conditions 3, the "insertion F / F" of D2 is an F / F 331 for storing data with a falling clock signal, and the designated data is designated. FIG. 11 shows an example of a circuit diagram processed by applying a condition to be inserted into the horizontal line 311.

Referring to the timing chart of FIG.
In particular, the circuit operation of FIG. 9 will be described focusing on the F / F 141 (REGB). T20 indicates a delay due to the clock tree, and T60 indicates a delay of the signal clkA due to the partial clock tree element between lines 11-321. F / F
Due to the clock line wiring process (D17) of the insertion process chart (FIG. 6), T60 is equal to half of T20. As a result, there is no timing error between clk and dat between the input signals of the F / F 141 (REGB).
The "input F / F" 141 (REGB) can perform a stable data storage operation. By observing the timing chart, the F / F 141 can store data before the placement of the "insertion F / F" 331 due to timing errors between clk and DATA between input signals. Did not.

<< Third Embodiment >> FIG. 11 shows the designated data.
The flowchart of the CTS according to the third embodiment in which the F / F is inserted into the contour line is shown. The input condition assignment in step (A1) is based on the following list of execution conditions 4. In the embodiment, the execution condition 4 is the execution condition 1 and the last 2 in the following list.
This is equivalent to the addition of the item (E2), and specifies execution of a gated clock, an instance name serving as a route of a clock tree, a clock net name, a buffer insertion level, and a buffer type. , The capacity of the output terminal of the buffer to be inserted, the capacity of each divided terminal when multiple pins are separated, the number of buffers to be inserted, the tree structure to be generated for each instance, and the execution of gated CTS. An element block for delay adjustment to be inserted, a loop
Buffer type of instance, prefix of instance name and net name to be added, name of terminal connected to power supply, name of power supply net connected to terminal, cost file used for wiring, map file used for high-pinning buffer with multiple pins The insertion of the F / F which takes in data at the reverse edge of the F / F which is the input of the data line for which the F / F is inserted into the data line (item E)
2), each item of designation of F / F to be inserted (item E2).

Step E1 is the F / F in E2.
Step E11 for determining whether there is a designated data line for inserting
And the subroutine step "F / F insertion" shown in FIG. Other steps shown in FIG. 11, A2 (including A21, A22 and A23), A3, A4, input / output files L1, L2, and L3 are the same as those in FIG.
Is the same.

In the flowchart of FIG. 12, step E12 is simplified according to the second embodiment.
“Insert F / F” takes in data at the opposite edge to “Input F / F”
/ F ”and netlist update processing. When fetching data at the reverse edge, there are two combinations. One is to store the data of "insertion F / F" at the time of falling of the clock signal and "input F / F". The date of
The data is stored at the time of the rising clock signal. On the other hand, the data storage of the "insertion F / F" is performed at the time of the rising of the clock signal and the data storage of the "input F / F" is performed. ,
This applies to each case when the clock signal falls.

Step E13 is a process of extracting the clock input signal of "insertion F / F". The branch point at which the increase in the wiring capacity and the increase in the variation in the clock due to the insertion of the F / F are minimized is determined as the output terminal of the buffer (or the inverter) at the last stage of the clock tree. Step E14 relates to the processing of the clock input wiring of “insertion F / F”.

FIG. 13 shows the third embodiment.
Among the execution conditions 4, the "insertion F / F" of E2 is the F / F 42 for performing the data storage operation at the falling clock, and the circuit is processed by applying the condition for insertion into the designated data line 41. FIG.

Referring to the timing chart of FIG.
In particular, the operation of the circuit will be described focusing on the F / F 42 and the F / F 14 (REGB). At the falling time T51 of the clk signal, the “insertion F / F” 42 that stably stores the input DATA signal transfers the dat signal from the output terminal Q to the input terminal D of the F / F. F / F is applied to the designated data line 41 by the clock distribution method according to the present invention.
If 42 is not inserted, the circuit of the F / F 14 has been determined to be NG in the delay verification.

FIG. 15 shows a third embodiment of the present invention.
In the execution condition 4, the "insertion F / F" of E2 is an F / F 421 for storing data at the rising clock, and an example of a circuit diagram processed by applying the condition for insertion into the designated data line 411 Is shown.

Referring to the timing chart of FIG.
In particular, F / F421 and F / F141 (REG
The circuit operation will be described focusing on B). F / F421
Changes the DATA signal to the rising time T6 of the clk signal.
1, the data is stably stored and transferred from the output terminal Q as an input signal of the F / F 141 without delay. Since there is no timing error between the input signals (clk and dat), F / F1
41 can perform a stable data storing operation.

[0043]

According to the present invention, there is provided a clock distribution process in which a delay compensation element is inserted into a designated data line in an F / F circuit of a semiconductor integrated circuit.

In the first embodiment of the present invention, the delay compensating element is configured such that the delay amount is equal to the delay amount inserted into the clock line of the F / F to which the designated data line is input. In the case of a buffer or an inverter. In this case, since the same amount of delay occurs in the data line, it is ensured that a stable data storage operation is performed.

In the second embodiment of the present invention, the compensation delay element is an "insertion F / F" and an "input F / F"
In this case, data is stored with a clock signal having the same edge as that of FIG. In this case, the "insertion F / F" as a compensation delay element ensures the stable data storage operation by the clock line wiring change process.

According to the third embodiment of the present invention, the compensation delay element in the first embodiment is an "insertion F / F", which is a clock signal having an edge opposite to that of the "input F / F". This is a case where data is stored. In this case, the "insertion F / F" as a compensation delay element ensures the stable data storage operation by the clock line wiring change process.

Regardless of any of the above embodiments, in order to provide a clock distribution method that does not fail the delay verification after the CTS, a cumbersome circuit required for each case of the conventional delay verification failure is required. It has the effect of eliminating all the change work and the cost required for the work.

[Brief description of the drawings]

FIG. 1 is a flowchart of a CTS of the present invention.

FIG. 2 is a subroutine flowchart of delay insertion into a data line.

FIG. 3 is a block circuit diagram of a first embodiment of a clock distribution method according to the present invention.

FIG. 4 is a timing chart of the block circuit diagram of the first embodiment of the clock distribution method of the present invention.

FIG. 5 is a flowchart of a clock distribution method according to a second embodiment of the present invention;

FIG. 6 shows a subroutine for inserting a F / F into a data line in a second embodiment of the clock distribution method of the present invention.
This is a flowchart (“insertion F / F” of the same edge).

FIG. 7 is a block circuit diagram of a clock distribution method according to a second embodiment of the present invention.

FIG. 8 is a timing chart of a block circuit diagram of a clock distribution method according to a second embodiment of the present invention.

FIG. 9 is a block circuit diagram of a clock distribution method according to a second embodiment of the present invention.

FIG. 10 is a timing chart of a block circuit diagram of a second embodiment of the clock distribution method of the present invention.

FIG. 11 is a flowchart of a clock distribution method according to a third embodiment of the present invention.

FIG. 12 is a subroutine flowchart of inserting a F / F into a data line according to a third embodiment of the clock distribution method of the present invention (“insertion F / F” of the reverse edge). .

FIG. 13 is a block circuit diagram of a clock distribution method according to a third embodiment of the present invention.

FIG. 14 is a timing chart of a block circuit diagram according to a third embodiment of the clock distribution method of the present invention.

FIG. 15 is a block circuit diagram of a third embodiment of the clock distribution method of the present invention.

FIG. 16 is a timing chart of a block circuit diagram according to a third embodiment of the clock distribution method of the present invention.

FIG. 17 is a flowchart of a conventional CTS.

FIG. 18 is a flowchart of an LSI design.

FIG. 19 is an example of a logic circuit to which a conventional CTS method is applied.

FIG. 20 is a timing chart of a logic circuit to which a conventional CTS method is applied and does not require compensation for timing errors.

FIG. 21 is a timing chart of a logic circuit which requires compensation for timing errors, to which a conventional CTS method is applied.

[Explanation of symbols]

11, 13, 32, 321, clock line 14, 15, 33, 42, 141, 331,
421, F / F 12, 18, 21, 23, 31, 34, 4
1, 43, 331, 341, 411, 431,
Data line 22, delay element

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Yasumitsu Makita 1-403, Kosugi-cho, Nakahara-ku, Kawasaki-shi, Kanagawa 53 F-term in NEC Icy Microcomputer Systems Co., Ltd. 5B046 AA08 BA03 DA05 JA03 5B079 BA20 BB10 BC03 CC02 CC14 DD06 DD08 DD20

Claims (5)

[Claims] A clock signal is supplied to a semiconductor integrated circuit.
In a clock distribution method, a delay compensation element is inserted into a designated data line after the clock distribution method is performed. 2. The method according to claim 1, wherein said specified data line is output by a delay element inserted by a clock distribution method.
A data line of a flip-flop input as a clock, a data line connected to an input data terminal of the flip-flop, which enters an execution area from a non-operation area of the clock distribution method, and 2. A clock distribution method according to claim 1, wherein said input data is a data line synchronized with an output of a delay element inserted by the clock distribution method. 3. The delay compensating element to be inserted into the designated data line, the delay compensating element being inserted into the flip-flop clock line to which the designated data line is input, the same amount of delay as the delay inserted. 2. The clock distribution method according to claim 1, wherein the clock distribution means is a buffer or an inverter. 4. The clock distribution method according to claim 2, wherein said delay compensating elements inserted into said designated data lines are flip-flops having the same edge. 5. The clock distribution method according to claim 2, wherein the delay compensating element inserted into the designated data line is a flip-flop having an opposite edge.