JP2001028545A - Receiving circuit and method for reducing power consumption of the receiving circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a receiving circuit capable of reducing power consumption, even when waiting for and receiving an incoming call. SOLUTION: While a comparator 1 detects a positive polarity of an AMI (alternate mark inversion) signal, an AND circuit 28 supplies a power down signal, and a comparator 2 goes into power down state. While the comparator 2 detects the negative polarity of the AMI signal, an AND circuit 29 supplies a power down signal, and the comparator 2 goes into power down state. Even though both of the compactors 1 and respectively are at power down state each output signal is fixed to a low level by NMOS transistors 20 and 21.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a receiving circuit for receiving an AMI signal, and more particularly to an AMI signal receiving circuit capable of reducing power consumption.

[0002]

2. Description of the Related Art In recent years, ISDN (Integrated Services)
Digital networks) can be used to transmit and receive large amounts of data, such as images and sounds, in a short time. Such ISDN terminals and the like include AMI (Altern
ate Mark Inversion) is provided with an AMI signal receiving circuit for receiving an encoded digital signal. Recently, in order to suppress the power consumption of the entire terminal, a device for reducing the power consumption in the AMI signal receiving circuit has been devised. Techniques for reducing the power consumption of such an AMI signal receiving circuit are disclosed in Japanese Patent Application Laid-Open Nos.
It is disclosed in Japanese Patent No. 1329297.

First, FIG. 7 shows a receiver circuit of the S interface described in JP-A-6-85958.
As shown, the receiver circuit includes a pulse transformer 210, a reference voltage input terminal 211, a voltage dividing resistor 212
, The positive comparator 213 and the negative comparator 21
4 and a wake-up circuit 215.

[0004] The pulse transformer 210 is provided with an AMI-coded ternary level (+,-,
0) (hereinafter, an AMI signal), and outputs a positive pulse and a negative pulse alternately. The voltage dividing resistor 212 divides the reference voltage supplied from the reference voltage input terminal 211 to obtain a voltage level Vb at one end of the pulse transformer 210,
A positive component reference signal level + Vth supplied to the positive comparator 213 and a negative component reference signal level −Vth supplied to the negative comparator 214 are set.

The positive comparator 213 changes the output level from "0" to "1" when receiving a positive pulse from the pulse transformer 210. Negative comparator 21
4 is provided with a power down function,
When a negative pulse is received from, the output level is changed from “0” to “1”. The wake-up circuit 215
When the positive comparator 213 receives a signal while the negative comparator 214 is powered down, the power down of the negative comparator 214 is released.

In this receiver circuit, one of the two comparators is provided with a power down function, and the power down is performed, so that power consumption can be reduced.

FIG. 8 shows a communication control semiconductor device described in Japanese Patent Application Laid-Open No. 6-132987. As shown in the figure, the semiconductor device for communication control includes a signal line 22 for reception.
1, 222, a first receiver 223, a second receiver 224, an internal circuit 225, an oscillator 226, and a receiver control device 227.

The first receiver 223 has a fast response speed and high accuracy, receives line data composed of AMI transmission waveform signals transmitted through the reception signal lines 221 and 222, and outputs the reception data. I do. Second receiver 2
The line 24 receives the line data composed of the AMI transmission waveform signal transmitted via the reception signal lines 221 and 222 with low response speed and low accuracy, and outputs the received data. The oscillator 226 generates a clock signal CK for operating the internal circuit 225 that processes the received data output from the first receiver 223.

[0009] The receiver control device 227 determines whether it is in the receiving state or the incoming call waiting state based on whether or not the first receiver 223 is outputting received data. If it is determined in this determination that the receiver is in the receiving state, the first receiver 223 and the internal circuit 225 are made operable, and the oscillator 226 generates the clock signal CK, so that the second receiver 224 is stopped. On the other hand, if it is determined that the incoming call is waiting, the second receiver 224 is made operable, the first receiver 223 and the internal circuit 225 are put into an operation stop state, and the oscillator 226 stops generating the clock signal CK.

In this device, the first receiver 223
In the second receiver 224, the power consumption is large because the response speed is high and the accuracy is high, while the power consumption of the second receiver 224 is small because the response speed is low and the accuracy is low. Therefore, the power consumption of the entire apparatus can be reduced by the power consumption of the first receiver 223 and the internal circuit 225 from the power consumption in the normal reception state while waiting for an incoming call.

[0011]

As described above, the receiver circuit disclosed in Japanese Patent Laid-Open No. 6-85958 reduces the power consumption by powering down one of the comparators when waiting for an incoming call. ), The power down of the comparator is released. For this reason, power consumption during standby for incoming calls can be reduced, but power consumption during incoming calls cannot be reduced.

Further, the communication control semiconductor device described in Japanese Patent Application Laid-Open No. 6-132987 operates a receiver with low power consumption during standby for incoming calls, and operates a receiver with high power consumption during incoming calls. Therefore, power consumption during standby for incoming calls can be reduced, but power consumption during incoming calls (during communication) cannot be reduced to the same extent as during standby for incoming calls.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a receiving circuit capable of reducing power consumption during incoming call standby and incoming call (during communication).

[0014]

To achieve the above object, a receiving circuit according to a first aspect of the present invention receives an AMI coded signal and detects a positive pulse of the AMI coded signal. , A first detection circuit that outputs a first detection signal and, when a control signal is supplied, receives a first detection circuit that powers down and an AMI coded signal, and detects a negative polarity pulse of the AMI coded signal. A second detection circuit that outputs a second detection signal and powers down when a control signal is supplied; a first detection signal output by the first detection circuit; A control signal for powering down the detection circuit for a predetermined period is generated based on the second detection signal output by the detection circuit, and the first detection circuit outputs the generated control signal to the first detection signal. At the same time as the second The detection circuit, the second detection circuit in the timing of outputting the second detection signal, characterized in that it is composed of, a control signal generating circuit for supplying to said first detection circuit.

According to the present invention, the first detection circuit is provided with A
Upon receiving the MI coded signal, detecting a positive polarity pulse of the AMI coded signal, outputting a first detection signal, and powering down when a control signal is supplied. The second detection circuit receives the AMI coded signal, detects a negative polarity pulse of the AMI coded signal, outputs a second detection signal, and, when a control signal is supplied, power-down. I do. The control signal generation circuit is a control signal for powering down the detection circuit for a predetermined period based on the first detection signal output by the first detection circuit and the second detection signal output by the second detection circuit. Is generated, and the generated control signal is output to the second detection circuit and the second detection circuit outputs the second detection signal at the timing when the first detection circuit outputs the first detection signal. At the timing, it is supplied to the first detection circuit. As described above, when the first detection circuit is detecting the positive polarity of the AMI signal, the second detection circuit is in the power down state, and the second detection circuit is in the AMI signal state.
In a state where the negative polarity of the signal is detected, the first detection circuit is in a power down state. As a result, power consumption can be reduced not only during standby for incoming calls, but also during communication.

The control signal generation circuit includes the first and second control signals.
May be provided with means for fixing the voltage at the output terminal of the detection circuit to which the control signal is supplied, to a predetermined level. In this case, a malfunction of the receiving circuit can be prevented by stabilizing the signal level of the output signal of any of the detection circuits that are powered down.

The control signal generation circuit receives the first detection signal output by the first detection circuit and the second detection signal output by the second detection circuit, and generates the control signal. Control signal generation means, selection means for selecting and supplying the control signal generated by the control signal generation means to one of the first detection circuit and the second detection circuit,
May be provided. In this case, while the first detection circuit is detecting the positive polarity of the AMI signal, the second detection circuit is powered down, and the second detection circuit is detecting the negative polarity of the AMI signal. In this state, the first detection circuit is powered down, so that power consumption can be reduced not only during standby for incoming calls but also during communication.

The control signal generation circuit detects a level change of a first detection signal output by the first detection circuit and a level change of a second detection signal output by the second detection circuit, and generates a predetermined differential pulse. A differential pulse generation unit that generates a signal, a pulse width expansion unit that extends the pulse width of the differential pulse signal generated by the differential pulse generation unit and generates the control signal having a predetermined pulse width, and the pulse width expansion unit. Supplying the generated control signal to the second detection circuit while the first detection circuit is outputting the first detection signal;
Control signal supply means for supplying the first detection circuit while the detection circuit outputs the second detection signal. In this case, while the first detection circuit is detecting the positive polarity of the AMI signal, the second detection circuit is powered down, and the second detection circuit is detecting the negative polarity of the AMI signal. In this state, the first detection circuit is powered down, so that power consumption can be reduced not only during standby for incoming calls but also during communication.

The pulse width extending means controls the pulse width shorter than a pulse width of a first detection signal output by the first detection circuit and a second detection signal output by the second detection circuit. A signal may be generated. In this case, the time required for the first and second detection circuits to transition from the power-down state to the power-on state and stabilize can be secured.

In order to achieve the above object, a second aspect of the present invention is provided.
The method for reducing the power consumption of the receiving circuit according to the aspect of the present invention includes the steps of: detecting a positive polarity pulse of the received AMI-encoded signal and driving a first detection circuit unit that outputs a predetermined detection signal;
A driving step, a second driving step of detecting a negative-polarity pulse of the received AMI encoded signal, and driving a second detection circuit unit that outputs a predetermined detection signal, and the first driving step On the basis of the detection signal output by the first detection circuit unit driven by the detection signal output by the second detection circuit unit driven by the second driving step, and
A generation step of generating a control signal for stopping the operation of any of the first detection circuit section and the second detection circuit section, and a control signal generated in the generation step, At the timing when the driven first detection circuit section outputs the detection signal, the second detection circuit section driven in the second driving step outputs a detection signal to the second detection circuit. And a control step of supplying to the first detection circuit at the given timing.

According to the present invention, the first driving step detects the positive pulse of the AMI coded signal being received and drives the first detection circuit unit that outputs a predetermined detection signal. The second driving step is to receive the AMI
A second detection circuit unit that detects a negative pulse of the encoded signal and outputs a predetermined detection signal is driven. The generation step is based on a detection signal output from the first detection circuit unit driven in the first driving step and a detection signal output from the second detection circuit unit driven in the second driving step. Thus, a control signal for stopping driving of either the first detection circuit portion or the second detection circuit portion is generated. The control step includes transmitting the control signal generated in the generation step to the second detection circuit at a timing when the first detection circuit section driven in the first driving step outputs the detection signal,
At the timing when the second detection circuit section driven in the driving step is outputting the detection signal, the signal is supplied to the first detection circuit. As described above, in a state where the first detection circuit is detecting the positive polarity of the AMI signal, the second detection circuit is in the power-down state, and the second detection circuit is detecting the negative polarity of the AMI signal. In this state, the first detection circuit is in a power down state. As a result, power consumption can be reduced not only during standby for incoming calls, but also during communication.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A receiving circuit according to an embodiment of the present invention will be described below with reference to the drawings.

(First Embodiment) First, a receiving circuit according to a first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a circuit diagram illustrating an example of the receiving circuit according to the first embodiment.

As shown, the receiving circuit includes comparators 1 and 2, an input terminal 3, a reference voltage input terminal 4,
5, output terminals 7, 8, clock signal input terminal 9,
And a power down signal generation circuit 100.

The comparator 1 has a positive input terminal (non-inverting input terminal) connected to the input terminal 3, and a negative input terminal (inverting input terminal) connected to the reference voltage input terminal 4. The input terminal 3 to which the positive input terminal is connected has an AMI
(Alternate Mark Inversion) Encoded ternary level (+,-, 0) signal (hereinafter referred to as "AMI signal")
Is entered. Further, a reference voltage + Vr is applied to the reference voltage input terminal 4 to which the negative input terminal is connected.

The comparator 1 compares the voltage of the AMI signal input to the positive input terminal with the reference voltage + Vr applied to the negative input terminal, and compares the voltage of the AMI signal with the reference voltage + Vr.
When it is higher, a high-level (logic 1 level) signal is output. The output terminal of the comparator 1 is connected to the output terminal 7 of the receiving circuit and the positive input terminal 10 of the power down signal generating circuit 100.

The comparator 1 has a power-down function. When a power-down signal instructing a power-down mode is supplied to its control terminal, the comparator 1 is turned off, and its power consumption is greatly reduced. At this time, the signal level of the output terminal is undefined (open state), but is fixed to the low level (logic 0 level) by the NMOS transistor 20 of the power down signal generation circuit 100 described later.

The comparator 2 has a positive input terminal connected to the reference voltage input terminal 5 and a negative input terminal connected to the input terminal 3, as opposed to the comparator 1. The reference voltage input terminal 4 to which the positive input terminal is connected has a reference voltage −
Vr is applied. The comparator 2 has a reference voltage −Vr applied to the positive input terminal and an AM input to the negative input terminal.
The voltage of the AMI signal is compared with the voltage of the I signal, and when the voltage of the AMI signal is lower than the reference voltage -Vr, a high-level signal is output. The output terminal of the comparator 2 is the output terminal 8 of the receiving circuit.
And the negative input terminal 11 of the power down signal generation circuit 100.

The comparator 2 also has a comparator 1
A power down function is provided in the same manner as described above, and the power is turned off when a power down signal is supplied to the control terminal. At this time, the signal level of the output terminal is undefined,
The low level is fixed by the transistor 21.

The power down signal generation circuit 100
OS (N-channel MOS) transistors 20 and 21
AND circuits 28 and 29, OR circuits 30 and 31,
It comprises an edge detection circuit 40, a shift register 50, and a clock signal input terminal 9.

The NMOS transistor 20 has a gate connected to the negative input terminal 11 and one end (source) of a current path.
Are grounded, and the other end (drain) of the current path is connected to the OR circuit 30 and the AND circuit 28 via the positive input terminal 10. The output signal of the comparator 2 is supplied to the negative input terminal 11 to which the gate is connected. That is, the NMOS transistor 20 is connected to the comparator 2
Outputs a high-level signal, and outputs a low-level signal to the OR circuit 30 and AND
Supply to circuit 28.

The NMOS transistor 21 has a gate connected to the positive input terminal 10 and one end (source) of a current path.
Are grounded, and the other end (drain) of the current path is connected to the OR circuit 30 and the AND circuit 29 via the negative input terminal 11. That is, the NMOS transistor 21
When the comparator 1 outputs a high-level signal, the low-level signal is supplied to the OR circuit 30 and the AND circuit 29 via the negative input terminal 11.

The OR circuit 30 has one input terminal connected to the positive input terminal 10, the other input terminal connected to the negative input terminal 11, and the output terminal A 1 connected to the input terminal of the edge detection circuit 40. Have been. The OR circuit 30 takes the logical sum of the signal levels of the positive input terminal 10 and the negative input terminal 11 and supplies the logical sum to the input terminal of the edge detection circuit 40. That is, the OR circuit 30 supplies a high-level signal to the input terminal of the edge detection circuit 40 when the signal level of either the positive input terminal 10 or the negative input terminal 11 is high.

The edge detection circuit 40 comprises a two-stage D flip-flop circuit (DFF) and an AND circuit. The edge detection circuit 40 has one input terminal connected to the OR circuit 3.
0 is connected to the output terminal A1, the other input terminal is connected to the clock signal input terminal 9, and the output terminal A2 is connected to the shift register 50. The clock signal input terminal 9 connected to the other input terminal is supplied with a predetermined clock signal CLK having a higher frequency than the AMI signal.

More specifically, the first stage DFF is:
The D input is connected to the output terminal A1 of the OR circuit 30, the C input is connected to the clock signal input terminal 9, and the Q output is connected to the D input of the second stage DFF and one input of the AND circuit. The second stage DFF has a C input connected to the clock signal input terminal 9 and an inverted Q output connected to the other input of the AND circuit. The output of the AND circuit is connected to the shift register 50.

That is, the first-stage DFF detects a high-level signal output from the OR circuit 30 in synchronization with the supplied clock signal CLK, and connects the second-stage DFF to the second-stage DFF from the non-inverting output terminal. Output to AND circuit. The second-stage DFF detects the signal supplied from the first-stage DFF in synchronization with the clock signal CLK and outputs the signal from the inverted output terminal to the AND circuit. Then, the AND circuit takes a logical product of the signal levels output by the first-stage DFF and the second-stage DFF, and outputs the result to the shift register 50. That is, the edge detection circuit 40 is connected to the output terminal A1 of the OR circuit 30.
An edge when the signal level rises from a low level to a high level is detected, and a high-level signal is supplied to the shift register 50 via the output terminal A2.

The shift register 50 comprises a multi-stage D flip-flop circuit (DFF). The shift register 50 has one input terminal connected to the output terminal A2 of the edge detection circuit 40, the other input terminal connected to the clock signal input terminal 9, and the output terminal A2 connected to one input terminal of the OR circuit 31. Have been. Note that the output terminal A2 of the edge detection circuit 40 is also connected to one input terminal of the OR circuit 31.

More specifically, the first stage DFF is:
The D input is connected to the output terminal A2 of the edge detection circuit 40,
The C input is connected to the clock signal input terminal 9, and the Q output is connected to the D input of the second stage DFF and the input of the OR circuit 31. The DFFs in the second and subsequent stages have the D input
The FF is connected to the Q output, the C input is connected to the clock signal input terminal 9, and the Q output is connected to the D input and the O of the next stage DFF.
Connected to the input of R circuit 31.

That is, the first-stage DFF shifts the signal output from the edge detection circuit 40 in synchronization with the supplied clock signal CLK, supplies the signal to the second-stage DFF, and Feed one input. The DFFs in the second and subsequent stages shift the signal supplied from the preceding DFF in synchronization with the clock signal CLK, and
F and to one input of the OR circuit 31. As described above, the preceding DFF sequentially shifts and outputs the signal to the next DFF, and each DFF is connected to the OR circuit 3.
Each signal is output to one input. In other words, the shift register 50 sequentially shifts the high-level signal or the like output from the edge detection circuit 40, and
1 to each input.

The OR circuit 31 has one input terminal of a plurality of input terminals connected to the output terminal A2 of the edge detection circuit 40, and the other input terminal having the Q output of each DFF constituting the shift register 50. , And the output terminal A3 is connected to one input terminal of each of the AND circuits 28 and 29. The OR circuit 31 calculates the logical sum of the signal levels input from the respective input terminals and supplies the logical sum to the input terminals of the AND circuits 28 and 29. That is, the OR circuit 31 generates a signal having a long pulse width determined by the number of DFFs constituting the shift register 50 and outputs the signal to the input terminals of the AND circuits 28 and 29.

The AND circuit 28 has one input terminal connected to the positive input terminal 10 and the other input terminal connected to the OR circuit 31.
The output terminal is connected to the control input terminal of the comparator 2. The AND circuit 28 calculates the logical product of the signal level output from the comparator 1 input via the positive input terminal 10 and the signal level output from the output terminal A3 of the OR circuit 31, and the control input of the comparator 2 Output to the end. That is, the AND circuit 28
Comparator 1 outputs a high-level signal, and
When a high-level signal is output from the output terminal A3 of the R circuit 31, a power-down signal (high-level signal) indicating a power-down mode is supplied to the comparator 2.

The AND circuit 29 has one input terminal connected to the negative input terminal 11 and the other input terminal connected to the OR circuit 31.
, And the output terminal is connected to the control input terminal of the comparator 1. The AND circuit 29 obtains the logical product of the signal level output from the comparator 2 input through the negative input terminal 11 and the signal level output from the output terminal A3 of the OR circuit 31, and the control input of the comparator 1 is obtained. Output to the end. That is, the AND circuit 29
Comparator 2 outputs a high-level signal, and
When a high-level signal is being output from the output terminal A3 of the R circuit 31, a power-down signal (high-level signal) indicating a power-down mode is supplied to the comparator 1.

Next, the operation of the receiving circuit according to the first embodiment of the present invention will be specifically described with reference to FIG.
FIG. 2 is a timing chart for explaining the operation of the receiving circuit. Here, in order to facilitate understanding, the operation of the receiving circuit will be described by dividing into three possible states of the AMI signal input from the input terminal 3. The three states are A
MI signal is positive pulse, no signal (no pulse)
And the state of the negative pulse. Hereinafter, simply, the voltage of the AMI signal is larger than the reference voltage + Vr (section T11), and is equal to or less than the reference voltage + Vr to the reference voltage -Vr.
The case where the operation sequentially shifts to three sections (T12 section) and smaller than the reference voltage + Vr (T13 section) will be sequentially described as an example.

(The AMI signal is higher than the reference voltage + Vr) First, the case where the voltage of the AMI signal input from the input terminal 3 is higher than the reference voltage + Vr (section T11) will be described.

The comparator 1 compares the voltage of the AMI signal shown in FIG. 2A supplied from the input terminal 3 with the reference voltage + Vr supplied from the reference voltage input terminal 4. As a result of this comparison, since the voltage of the AMI signal is higher than the reference voltage + Vr, the comparator 1 uses the high-level signal shown in FIG. 2B as a detection signal via the output terminal 7 and the positive input terminal 10. It is supplied to the gate of the NMOS transistor 21. On the other hand, since the voltage of the AMI signal is higher than the reference voltage −Vr supplied from the reference voltage input terminal 5, the comparator 2 supplies a low-level signal shown in FIG.

The NMOS transistor 21 is turned on when a detection signal (high-level signal) is applied to the gate, and the signal level of the signal line (the output terminal 8 and the like) connected to the output terminal of the comparator 2 is grounded. Fixed to. The OR circuit 30 is supplied with a high-level signal from the positive input terminal 10 and a low-level signal from the negative input terminal 11.

The OR circuit 30 performs a logical OR operation on the supplied high-level signal and low-level signal, and performs an OR operation as shown in FIG.
A high-level signal shown in FIG.
Is supplied to the edge detection circuit 40 via the.

The edge detection circuit 40 receives the high-level signal output from the OR circuit 30 from one input terminal, and receives the signal from the other input terminal via the clock input terminal 9 as shown in FIG.
Is input. Then, the edge detection circuit 40 generates a differential pulse signal of one clock width shown in FIG. 2F synchronized with the rise of the clock signal CLK, and supplies it to the shift register 50 and the OR circuit 31 via the output terminal A2. I do.

The multi-stage DFF of the shift register 50 receives the differentiated pulse signal output from the edge detection circuit 40 and the clock signal CLK via the clock input terminal 9, respectively, and converts the input differentiated pulse signal into the next stage DFF. To the OR circuit 31. And OR
The differential pulse signal output from the edge detection circuit 40 and the differential pulse signal output from each DFF of the shift register 50 are sequentially supplied to each input terminal of the circuit 31.

The OR circuit 31 takes a logical sum of the signal levels input from the respective input terminals, generates a high-level signal having a predetermined pulse width shown in FIG. 2 (g), and outputs the AND signal via the output terminal A3. The signals are supplied to circuits 28 and 29.

The AND circuit 28 receives a high-level signal shown in FIG. 2B from one input terminal via the positive input terminal 10, and a high-level signal shown in FIG. 2G from the other input terminal. Input signal. And the AND circuit 28
The logical product of these is taken, a high-level signal shown in FIG. 2 (i) is generated, and supplied to the comparator 2 as a power-down signal indicating a power-down mode.

The comparator 2 receives the signal AN via the control terminal.
When the power down signal sent from the D circuit 28 is input, the state shifts to the power down state. As a result, as shown in FIG. 2K, the comparator 2 is in a power-down state in which power consumption is suppressed while the power-down signal is being input from the AND circuit 28.

On the other hand, the AND circuit 29 is supplied with the low-level signal shown in FIG. 2C from one input terminal via the negative input terminal 11, so that the low-level signal shown in FIG. Is generated and supplied to the comparator 1. Therefore, the comparator 1 detecting the high-level signal from the AMI signal continues to operate.

When the power of the comparator is reduced, the output of the comparator usually becomes unstable. However, in this case, while the detection signal output from the comparator 1 is at the high level, the NMOS transistor 21 is turned on, and the output level of the comparator 2 is fixed to the ground. Therefore, the receiving circuit does not impair the original operation.

(The AMI signal is equal to or lower than the reference voltage + Vr to equal to or higher than the reference voltage -Vr.)
The case where the signal voltage is equal to or lower than the reference voltage + Vr to equal to or higher than the reference voltage -Vr (section T12) will be described.

When the AMI signal shifts from a level higher than the reference voltage + Vr to a level lower than the reference voltage + Vr to a level higher than the reference voltage -Vr, the comparator 1 determines that the voltage of the AMI signal is lower than the reference voltage + Vr. The low-level signal shown in b) is supplied to the output terminal 7 and the gate of the NMOS transistor 21 via the positive input terminal 10.
On the other hand, the comparator 2 determines that the voltage of the AMI signal is the reference voltage −Vr still supplied from the reference voltage input terminal 5.
Therefore, a low-level signal shown in FIG. 2C is supplied to the output terminal 8 and the like.

The NMOS transistor 21 is turned off when a low-level signal is applied instead of the high-level signal applied to the gate until now. Thereafter, the signal output from the output terminal of the comparator 2 is output via the output terminal 8 of the receiving circuit.

The AND circuit 28 receives a low-level signal shown in FIG. 2B from one input terminal via the positive input terminal 10 (the low-level signal is also supplied from the other input terminal). Signal is supplied), and a low-level signal shown in FIG. 2I is generated and supplied to the comparator 2. For this reason, the comparator 2 that has been in the power-down state restarts its operation as shown in FIG.

On the other hand, the AND circuit 29 receives a low-level signal shown in FIG. 2C from one input terminal or the like, generates a low-level signal shown in FIG. Therefore, the comparator 1 continues the operation.

Next, the case where the voltage of the AMI signal input from the input terminal 3 is smaller than the reference voltage -Vr (section T13) will be described.

The comparator 2 compares the voltage of the AMI signal shown in FIG. 2A supplied from the input terminal 3 with the reference voltage -Vr supplied from the reference voltage input terminal 5. As a result of the comparison, since the voltage of the AMI signal is smaller than the reference voltage −Vr, the comparator 2 uses the high-level signal shown in FIG. 2C as a detection signal via the output terminal 8 and the negative input terminal 11. And the gate of the NMOS transistor 20. On the other hand, since the voltage of the AMI signal is smaller than the reference voltage + Vr supplied from the reference voltage input terminal 4, the comparator 1 supplies a low-level signal shown in FIG.

The NMOS transistor 20 is turned on when a detection signal (high-level signal) is applied to the gate, and sets the signal level of the signal line (the output terminal 7 and the like) connected to the output terminal of the comparator 1 to the ground. Fixed to. The OR circuit 30 is supplied with a high-level signal from the negative input terminal 11 and a low-level signal from the positive input terminal 10.

The OR circuit 30 generates a high-level signal shown in FIG. 2D and supplies it to the edge detection circuit 40 via the output terminal A1. The edge detection circuit 40 synchronizes with the rising edge of the clock signal CLK as shown in FIG.
A differential pulse signal having a clock width is generated and supplied to the shift register 50 and the OR circuit 31. Shift register 5
The multi-stage DFF of 0 shifts the input differential pulse signal to the next-stage DFF and supplies the signal to the OR circuit 31.
The OR circuit 31 generates a high-level signal having a predetermined pulse width shown in FIG. 2 (g) and supplies the signal to the AND circuits 28 and 29.

The AND circuit 29 is connected to one input terminal of FIG.
To input the high-level signal shown in FIG. 2C and the high-level signal shown in FIG. 2G from the other input terminal, a high-level signal shown in FIG. It is supplied to the comparator 1 as a down signal. When the power down signal sent from the AND circuit 29 is input via the control terminal, the comparator 1 shifts to the power down state. As a result, the comparator 1 is as shown in FIG.
As shown in (5), while the power down signal is being input from the AND circuit 29, the power down state is achieved in which the power consumption is suppressed.

On the other hand, since the low-level signal shown in FIG. 2B is supplied from one input terminal of the AND circuit 28, the AND circuit 28 generates the low-level signal shown in FIG. Will be supplied. Therefore, AMI
The comparator 2 detecting the negative polarity from the signal continues to operate.

While the detection signal output from the comparator 2 is at the high level, the NMOS transistor 20 is turned on, and the output level of the comparator 1 is fixed to the ground. Therefore, the receiving circuit does not impair the original operation.

As described above, in the receiving circuit of this embodiment, when the comparator 1 detects the positive polarity of the AMI signal, the comparator 2 is in the power down state, and the comparator 2 is in the power down state. In a state where the negative polarity is detected, the comparator 1 is in a power down state. Even if the comparators 1 and 2 are in the power-down state, the NMOS transistor 2
Each output signal is fixed to a low level by 0 and 21.
As a result, it is possible to reduce the power consumption without impairing the operation even during normal communication when receiving the AMI signal.

The receiving circuit according to the present invention uses the sequentially supplied A
In order to allow the MI signal to be received normally, it is desirable to consider the time required for the comparators 1 and 2 to transition from the power down state to the power on state and stabilize. Specifically, it is desirable to release the power-down state of the comparator 1 before the output signal of the comparator 2 changes (returns) from the high level to the low level. It is desirable to release the signal before the output signal of the comparator 1 changes (returns) from the high level to the low level.

In the receiving circuit according to the first embodiment described above, a clock signal is required for the power-down signal generating circuit 100. However, a circuit configuration that does not require a clock signal may be employed. (Second embodiment)
Hereinafter, a receiving circuit according to a second embodiment of the present invention including a power-down signal generating circuit that does not require a clock signal will be described with reference to FIG. FIG. 3 is a circuit diagram illustrating an example of the receiving circuit according to the second embodiment.

As shown, the receiving circuit includes comparators 1 and 2, an input terminal 3, a reference voltage input terminal 4,
5, output terminals 7 and 8, power down signal generation circuit 1
And 10. Note that comparators 1, 2,
The configuration of the input terminal 3, the reference voltage input terminals 4 and 5, and the output terminals 7 and 8 is the same as that of the first embodiment described with reference to FIG.

The power down signal generation circuit 110 has a function of NM
OS transistors 20 and 21 and AND circuits 28 and 29
, An OR circuit 30, a differentiating circuit 60, and a monostable multivibrator 70. The NMOS transistors 20 and 21, the AND circuits 28 and 29, and
The configuration of the OR circuit 30 is similar to that of the first embodiment described with reference to FIG.

The differentiating circuit 60 includes, for example, an inverter, a delay circuit, and an AND circuit. Differentiating circuit 60
Has an input terminal connected to the output terminal A1 of the OR circuit 30, and an output terminal connected to the input terminal of the monostable multivibrator 70. The differentiating circuit 60 is connected to the output terminal A1 of the OR circuit 30.
An edge when the signal level rises from a low level to a high level is detected, and a high-level signal is supplied to the monostable multivibrator 70 via the output terminal A4.

The monostable multivibrator 70 comprises, for example, an OR circuit, a capacitor, a resistor, and an inverter. The monostable multivibrator 70 has an input terminal connected to the output terminal A4 of the differentiating circuit 60, and an output terminal connected to the AND terminal.
The input terminals of the circuits 28 and 29 are connected. The monostable multivibrator 70 extends the pulse width of the signal input from the differentiating circuit 60, and outputs a signal having a long pulse width determined by the capacitance of a capacitor or the like to the input terminals of the AND circuits 28 and 29.

Next, the operation of the receiving circuit according to the second embodiment of the present invention will be specifically described with reference to FIG.
FIG. 4 is a timing chart for explaining the operation of the receiving circuit. Here, in order to facilitate understanding, the operation of the receiving circuit will be described by dividing into three possible states of the AMI signal input from the input terminal 3. Hereinafter, as in the description of the first embodiment, the voltage of the AMI signal is higher than the reference voltage + Vr (section T21), lower than the reference voltage + Vr to higher than the reference voltage -Vr (section T22), and higher than the reference voltage + Vr. The case of sequentially shifting to three sections (small (T23 section)) will be sequentially described as an example.

First, the case where the voltage of the AMI signal input from the input terminal 3 is higher than the reference voltage + Vr (section T21) will be described. The comparator 1 receives the signal from the input terminal 3 shown in FIG.
The voltage of the AMI signal shown in FIG.
Is compared with the reference voltage + Vr supplied from. As a result of this comparison, since the voltage of the AMI signal is higher than the reference voltage + Vr, the comparator 1 supplies the high-level signal shown in FIG. 4B to the output terminal 7 and the gate of the NMOS transistor 21 as a detection signal. I do. On the other hand, since the voltage of the AMI signal is higher than the reference voltage −Vr supplied from the reference voltage input terminal 5, the comparator 2 supplies a low-level signal shown in FIG.

The NMOS transistor 21 is turned on when a detection signal (high-level signal) is applied to the gate, and the signal level of the signal line (the output terminal 8 and the like) connected to the output terminal of the comparator 2 is grounded. Fixed to. The OR circuit 30 performs an OR operation on the supplied high-level signal and low-level signal,
A high-level signal shown in FIG.
To the differentiating circuit 60 via

The differentiating circuit 60 detects the rising of the signal output from the OR circuit 30 from the low level to the high level, generates a differential pulse signal shown in FIG. 4E, and outputs the signal through the output terminal A4. Monostable multivibrator 70
To supply. When the monostable multivibrator 70 receives the differentiated pulse signal, the monostable multivibrator 70 extends the pulse width, and
A high-level signal having a predetermined pulse width shown in (f) is generated and supplied to the AND circuits 28 and 29 via the output terminal A5.

The AND circuit 28 is connected to one input terminal of FIG.
A high-level signal shown in FIG. 4B is input, and a high-level signal shown in FIG. 4F is input from the other input terminal. Then, the AND circuit 28 calculates the logical product of these, and outputs the result of FIG.
A high-level signal shown in (h) is generated and supplied to the comparator 2 as a power-down signal.

When the power down signal is input via the control terminal, the comparator 2 shifts to the power down state. As a result, as shown in FIG. 4J, the comparator 2 is in the power-down state in which the power consumption is suppressed while the power-down signal is being input from the AND circuit 28.

On the other hand, since the low-level signal shown in FIG. 4C is supplied from one input terminal of the AND circuit 29, the AND circuit 29 generates the low-level signal shown in FIG. Will be supplied. Therefore, AMI
The comparator 1 detecting a high-level signal from the signal continues to operate.

As in the first embodiment, while the detection signal output from the comparator 1 is at the high level, N
Since the MOS transistor 21 is turned on and the output level of the comparator 2 is fixed to the ground, the receiving circuit does not impair the original operation.

(When the AMI signal is equal to or lower than the reference voltage + Vr to equal to or higher than the reference voltage -Vr)
The case where the signal voltage is equal to or lower than the reference voltage + Vr to equal to or higher than the reference voltage -Vr (section T22) will be described.

When the AMI signal shifts from a level higher than the reference voltage + Vr to a level lower than the reference voltage + Vr to a level higher than the reference voltage -Vr, the comparator 1 changes the voltage of the AMI signal to a level lower than the reference voltage + Vr. The low-level signal shown in FIG.
And supply to the gate. On the other hand, the comparator 2
Since the voltage of the I signal is still higher than the reference voltage −Vr supplied from the reference voltage input terminal 5, a low-level signal shown in FIG. 4C is supplied to the output terminal 8 and the like.

The low level signal is applied to the gate of the NMOS transistor 21, and the NMOS transistor 21 shifts to the off state. Thereafter, the signal output from the output terminal of the comparator 2 is output via the output terminal 8 of the receiving circuit. The AND circuit 28 receives the signal from one input terminal as shown in FIG.
Since the low level signal shown in is supplied,
The low-level signal shown in FIG. 4H is generated and supplied to the comparator 2. Therefore, the comparator 2 that has been in the power-down state restarts its operation as shown in FIG.

On the other hand, since the low-level signal shown in FIG. 4C is still supplied from one input terminal or the like, the AND circuit 29 generates the low-level signal shown in FIG. This is supplied to the comparator 1. Therefore, the comparator 1 continues to operate.

(The AMI signal is smaller than the reference voltage -Vr) Next, the case where the voltage of the AMI signal input from the input terminal 3 is smaller than the reference voltage -Vr (section T23) will be described.

The comparator 2 compares the voltage of the AMI signal shown in FIG. 4A supplied from the input terminal 3 with the reference voltage −Vr supplied from the reference voltage input terminal 5. As a result of this comparison, since the voltage of the AMI signal is smaller than the reference voltage −Vr, the comparator 2 uses the high-level signal shown in FIG.
It is supplied to the gate of the transistor 20. On the other hand, the comparator 1 outputs the voltage of the AMI signal to the reference voltage input terminal 4.
4 is smaller than the reference voltage + Vr supplied from
The low-level signal shown in (b) is supplied to the output terminal 7 and the like.

The NMOS transistor 20 is turned on, and fixes the signal level of the signal line (such as the output terminal 7) connected to the output terminal of the comparator 1 to the ground. The OR circuit 30 generates a high-level signal shown in FIG. 4D and supplies the signal to the differentiating circuit 60 via the output terminal A1. The differentiating circuit 60 generates the differentiated pulse signal shown in FIG. 4E and supplies it to the monostable multivibrator 70. The monostable multivibrator 70 extends the pulse width of the input differential pulse signal, generates a high-level signal having a predetermined pulse width shown in FIG. 4 (f), and supplies it to the AND circuits 28 and 29.

The AND circuit 29 is connected to one input terminal of FIG.
In order to input a high-level signal shown in FIG. 4C and to input a high-level signal shown in FIG. 4F from the other input terminal, a high-level signal shown in FIG. It is supplied to the comparator 1 as a down signal. When the power down signal sent from the AND circuit 29 is input via the control terminal, the comparator 1 shifts to the power down state. As a result, the comparator 1 outputs the signal shown in FIG.
As shown in (5), while the power down signal is being input from the AND circuit 29, the power down state is achieved in which the power consumption is suppressed.

On the other hand, the AND circuit 28 supplies a low-level signal shown in FIG.
In order to generate the low-level signal shown in (h) and supply it to the comparator 2, the comparator 2 that detects the negative polarity from the AMI signal continues to operate.

Note that while the detection signal output from the comparator 2 is at a high level, the NMOS transistor 20 is turned on, and the output level of the comparator 1 is fixed to the ground. There is no loss.

As described above, the receiving circuit according to the second embodiment uses the power-down signal generating circuit having a configuration that does not require the clock signal (CLK) required in the first embodiment. Even in this case, exactly the same effects as in the first embodiment can be obtained.

In the above-described receiving circuit according to the second embodiment, the power-down signal generating circuit 110 is constituted by a differentiating circuit and a monostable multivibrator. However, the present invention is not limited to this structure. It is also possible to configure a power down signal generation circuit having the configuration. (Third Embodiment) A receiving circuit according to a third embodiment of the present invention including a power down signal generation circuit including a pulse width control circuit will be described below with reference to FIG. FIG. 5 is a circuit diagram illustrating an example of the receiving circuit according to the third embodiment.

As shown, the receiving circuit comprises comparators 1 and 2, an input terminal 3, a reference voltage input terminal 4,
5, output terminals 7 and 8, power down signal generation circuit 1
20. Note that comparators 1, 2,
The input terminal 3, the reference voltage input terminals 4 and 5, and the output terminals 7 and 8 have the same configuration as in the first embodiment described with reference to FIG.

The power down signal generation circuit 120 has a function of NM
OS transistors 20 and 21 and AND circuits 28 and 29
, An OR circuit 30, and a pulse width control circuit 80. The NMOS transistors 20, 21, A
The configurations of the ND circuits 28 and 29 and the OR circuit 30 are the same as those of the first embodiment described with reference to FIG.

The pulse width control circuit 80 includes an NMOS transistor 22, inverters 23 and 24, a resistor 25,
It is composed of a capacitor 26 and an AND circuit 27. The pulse width control circuit 80 has an input terminal connected to the output terminal A1 of the OR circuit 30, and an output terminal A8 connected to the AND circuit 28,
29 are connected to one of the input terminals.

More specifically, one end of the resistor 25 is connected to the output terminal A1 of the OR circuit 30 and the other end is connected to
It is connected to the drain of the NMOS transistor 22 and the like. The inverter 23 has an input terminal connected to the output terminal A1 or the like of the OR circuit 30 and an output terminal connected to the NMOS transistor 22.
Connected to the gate. NMOS transistor 22
Has a source grounded, a gate connected to the output terminal of the inverter 23, and a drain connected to the input terminal of the inverter 24 and the like. One end of the capacitor 26 is grounded,
The other end is connected to the input terminal of the inverter 24 and the like. The inverter 24 has an input terminal connected to one end of the resistor 25 and the like, and an output terminal A7 connected to one input terminal of the AND circuit 27. The AND circuit 27 has one input terminal connected to the output terminal A7 of the inverter 24, the other input terminal connected to the output terminal A1, etc. of the OR circuit 30, and the output terminal A8.
Are connected to one input terminals of the AND circuits 28 and 29, respectively. That is, the pulse width control circuit 80
0, the pulse width of the signal supplied from the output terminal A1 is extended, and a signal having a predetermined pulse width is output to the AND circuits 28 and 29.
Output to

Next, the operation of the receiving circuit according to the third embodiment of the present invention will be specifically described with reference to FIG.
FIG. 6 is a timing chart for explaining the operation of the receiving circuit. Here, in order to facilitate understanding, the operation of the receiving circuit will be described by dividing into three possible states of the AMI signal input from the input terminal 3. Hereinafter, as in the description of the first embodiment, the voltage of the AMI signal is higher than the reference voltage + Vr (section T31), lower than the reference voltage + Vr to higher than the reference voltage -Vr (section T32), and higher than the reference voltage + Vr. The case of sequentially shifting to three sections (small (T33 section)) will be sequentially described as an example.

First, the case where the voltage of the AMI signal input from the input terminal 3 is higher than the reference voltage + Vr (section T31) will be described. The comparator 1 receives the signal from the input terminal 3 shown in FIG.
The voltage of the AMI signal shown in FIG.
Is compared with the reference voltage + Vr supplied from. As a result of this comparison, since the voltage of the AMI signal is higher than the reference voltage + Vr, the comparator 1 supplies the high-level signal shown in FIG. 6B to the output terminal 7 and the gate of the NMOS transistor 21 as a detection signal. I do. On the other hand, since the voltage of the AMI signal is higher than the reference voltage −Vr supplied from the reference voltage input terminal 5, the comparator 2 supplies a low-level signal shown in FIG.

The NMOS transistor 21 is turned on to fix the signal level of the signal line (the output terminal 8 and the like) connected to the output terminal of the comparator 2 to the ground. The OR circuit 30 performs a logical OR operation on the supplied high-level signal and low-level signal, generates a high-level signal shown in FIG. 6D, and performs pulse width control via the output terminal A1. Supply to circuit 80.

When the signal sent from the OR circuit 30 is supplied to the pulse width control circuit 80, the rising edge of the signal output from the OR circuit 30 which changes from low level to high level is applied to the input terminal A6 of the inverter 24. As a starting point, a waveform signal shown in FIG. 6E in which the voltage increases due to the time constant of the resistor 25 and the capacitor 26 is input. Inverter 24
Outputs a high-level signal as shown in FIG. 6 (f) until the signal inputted from the input terminal A6 exceeds its own threshold voltage, and when the inputted signal exceeds its own threshold voltage. , Is supplied to one input terminal of the AND circuit 27 via the output terminal A7.

The AND circuit 27 is connected to one input terminal of FIG.
A high-level signal shown in (d) is input, and a signal that changes from high level to low level shown in FIG. 6 (f) is input from the other input terminal. Then, the AND circuit 27 takes the logical product of these, generates a high-level signal shown in FIG. 6G, and outputs the AND circuits 28 and 29 via the output terminal A8.
To supply.

The AND circuit 28 is connected to one input terminal of FIG.
A high-level signal shown in FIG. 6B is input, and a high-level signal shown in FIG. 6G is input from the other input terminal. Then, a logical product of them is calculated, and a high-level signal shown in FIG. 6I is generated and supplied to the comparator 2 as a power-down signal. When the power down signal is input via the control terminal, the comparator 2 shifts to the power down state. As a result, the comparator 2
As shown in (k), while the power down signal is being input from the AND circuit 28, the power down state is achieved in which the power consumption is suppressed.

On the other hand, the AND circuit 29 supplies a low-level signal shown in FIG.
In order to generate the low-level signal shown in (h) and supply it to the comparator 1, the comparator 1 detecting the high-level signal from the AMI signal continues to operate.

As in the first embodiment, while the detection signal output from the comparator 1 is at the high level, NM
Since the OS transistor 21 is turned on and the output level of the comparator 2 is fixed to the ground, the receiving circuit does not impair the original operation.

(The AMI signal is equal to or lower than the reference voltage + Vr to equal to or higher than the reference voltage -Vr)
The case where the voltage of the signal is equal to or lower than the reference voltage + Vr to equal to or higher than the reference voltage -Vr (section T32) will be described.

When the AMI signal shifts from a level higher than the reference voltage + Vr to a level equal to or lower than the reference voltage + Vr to a level equal to or higher than the reference voltage -Vr, the comparator 1 determines that the voltage of the AMI signal is equal to or lower than the reference voltage + Vr. The low-level signal shown in FIG.
And supply to the gate. On the other hand, the comparator 2
Since the voltage of the I signal is still higher than the reference voltage −Vr supplied from the reference voltage input terminal 5, the low-level signal shown in FIG. 6C is supplied to the output terminal 8 and the like.

The low level signal is applied to the gate of the NMOS transistor 21, and the NMOS transistor 21 shifts to the off state. Thereafter, the signal output from the output terminal of the comparator 2 is output via the output terminal 8 of the receiving circuit. The AND circuit 28 receives the signal from one input terminal as shown in FIG.
Since the low level signal shown in is supplied,
The low-level signal shown in FIG. 6I is generated and supplied to the comparator 2. Therefore, the comparator 2 that has been in the power-down state restarts its operation as shown in FIG. On the other hand, the AND circuit 29 is supplied with a low-level signal shown in FIG. 6C from one input terminal or the like, generates a low-level signal shown in FIG. Comparator 1
Continue operation.

Next, the case where the voltage of the AMI signal input from the input terminal 3 is smaller than the reference voltage -Vr (section T33) will be described.

The comparator 2 compares the voltage of the AMI signal shown in FIG. 6A supplied from the input terminal 3 with the reference voltage -Vr supplied from the reference voltage input terminal 5. As a result of this comparison, since the voltage of the AMI signal is smaller than the reference voltage −Vr, the comparator 2 uses the high-level signal shown in FIG.
It is supplied to the gate of the transistor 20. On the other hand, the comparator 1 outputs the voltage of the AMI signal to the reference voltage input terminal 4.
6 is smaller than the reference voltage + Vr supplied from
The low-level signal shown in (b) is supplied to the output terminal 7 and the like.

The NMOS transistor 20 is turned on, and fixes the signal level of the signal line (the output terminal 7 and the like) connected to the output terminal of the comparator 1 to the ground. The OR circuit 30 generates a high-level signal shown in FIG. 6D, and outputs the signal to the pulse width control circuit 8 through the output terminal A1.
Supply 0. AND circuit 27 of pulse width control circuit 80
Generates a high-level signal shown in FIG. 6G and supplies it to the AND circuits 28 and 29 via the output terminal A8.

The AND circuit 29 is connected to one input terminal of FIG.
In order to input a high-level signal shown in FIG. 6D and to input a high-level signal shown in FIG. 6F from the other input terminal, a high-level signal shown in FIG. It is supplied to the comparator 1 as a down signal. When the power down signal sent from the AND circuit 29 is input via the control terminal, the comparator 1 shifts to the power down state. As a result, the comparator 1 outputs the signal shown in FIG.
As shown in (5), while the power down signal is being input from the AND circuit 29, the power down state is achieved in which the power consumption is suppressed.

On the other hand, the AND circuit 28 supplies a low-level signal shown in FIG.
In order to generate the low-level signal shown in (i) and supply it to the comparator 2, the comparator 2 detecting the negative polarity from the AMI signal continues to operate.

While the detection signal output from the comparator 2 is at the high level, the NMOS transistor 20 is turned on, and the output level of the comparator 1 is fixed to the ground. There is no loss.

As described above, the receiving circuit according to the third embodiment of the present invention uses a power-down signal generating circuit composed of a pulse width control circuit different from the configuration of the second embodiment. However, the same effect as in the first embodiment can be obtained.

Note that the present invention is not limited to the above embodiment, and various modifications are possible. For example, the pulse width control circuit 80 of the power down signal generation circuit 120 uses the circuit shown in FIG.
Is not limited to this, and is arbitrary, and can be arbitrarily changed as long as the circuit configuration can generate an arbitrary pulse width starting from the rising edge of the signal A1 output from the OR circuit 30.

[0117]

As described above, according to the present invention, it is possible to reduce power consumption not only at the time of waiting for an incoming call, but also at the time of communication.

[Brief description of the drawings]

FIG. 1 is a circuit diagram illustrating an example of a receiving circuit according to a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining an operation of the receiving circuit according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram illustrating an example of a receiving circuit according to a second embodiment of the present invention.

FIG. 4 is a timing chart for explaining an operation of the receiving circuit according to the second embodiment of the present invention.

FIG. 5 is a circuit diagram illustrating an example of a receiving circuit according to a third embodiment of the present invention.

FIG. 6 is a timing chart for explaining an operation of the receiving circuit according to the third embodiment of the present invention.

FIG. 7 is a diagram illustrating a configuration of a conventional receiver circuit.

FIG. 8 is a diagram showing a configuration of a conventional communication control semiconductor device.

[Explanation of symbols]

1, 2 Comparator 3 AMI signal input terminal 4, 5 Reference voltage input terminal 7, 8 Output terminal 20, 21 N-channel type MOS transistor 23, 24 Inverter 25 Resistance 26 Capacity 27, 28, 29 AND circuit 30, 31 OR circuit 40 Edge detection circuit 50 Shift register 60 Differentiation circuit 70 Monostable multivibrator 80 Pulse width control circuit 100, 110, 120 Power down signal generation circuit

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5K029 AA13 CC01 DD15 FF03 HH01 LL02 LL08 LL11 5K034 AA15 BB01 CC02 CC05 DD01 EE05 FF15 GG06 HH02 KK04 TT02 TT07 5K037 AA13 AB01 AD01 AD02 BA02 BA04

Claims (6)

[Claims] An AMI (Alternate Mark Inversion) coded signal is received, a positive polarity pulse of the AMI coded signal is detected, a first detection signal is output, and a control signal is supplied. Receiving a AMI coded signal, detecting a negative pulse of the AMI coded signal, outputting a second detection signal, and supplying a control signal. A second detection circuit that powers down, a first detection signal output by the first detection circuit, and a second detection signal output by the second detection circuit.
A control signal for powering down the detection circuit for a predetermined period is generated, and the generated control signal is transmitted to the second detection circuit at the timing when the first detection circuit outputs the first detection signal. And a control signal generation circuit that supplies the control signal to the first detection circuit when the second detection circuit outputs the second detection signal. 2. The control signal generating circuit according to claim 1, wherein said control signal generating circuit includes said first and second control signals.
2. The receiving circuit according to claim 1, further comprising: means for fixing a voltage at an output terminal of the detecting circuit to which the control signal is supplied, to a predetermined level. 3. The control signal generation circuit receives a first detection signal output by the first detection circuit and a second detection signal output by the second detection circuit, and outputs the control signal. A control signal generating means for generating, and a control signal generated by the control signal generating means,
3. The receiving circuit according to claim 1, further comprising: a selection unit that selectively supplies the signal to one of the detection circuit and the second detection circuit. 4. 4. The control signal generation circuit detects a level change of a first detection signal output by the first detection circuit and a level change of a second detection signal output by the second detection circuit, and detects a change in level. Differential pulse generation means for generating a differential pulse signal; pulse width expansion means for expanding the pulse width of the differential pulse signal generated by the differential pulse generation means to generate the control signal having a predetermined pulse width; and Transmitting the control signal generated by the means to the first
Supplies the first detection signal to the second detection circuit while outputting the first detection signal, and supplies the second detection signal to the first detection circuit while outputting the second detection signal. The receiving circuit according to claim 1, further comprising: a control signal supply unit. 5. The pulse width expanding means according to claim 1, wherein said pulse width expanding means has a pulse width shorter than a pulse width of a first detection signal output by said first detection circuit and a second detection signal output by said second detection circuit. The reception circuit according to claim 1, wherein the control circuit generates the control signal. 6. A first driving step of detecting a positive polarity pulse of a received AMI coded signal and driving a first detection circuit for outputting a predetermined detection signal; A second driving step of driving a second detection circuit unit that detects a negative polarity pulse of the conversion signal and outputs a predetermined detection signal; and a first detection circuit unit driven in the first driving step Based on the detection signal output from the first detection circuit unit and the detection signal output from the second detection circuit unit driven in the second driving step. A generation step of generating a control signal for stopping driving, the control signal generated by the generation step
At the timing when the first detection circuit unit driven in the driving step is outputting the detection signal, the second detection circuit unit driven in the second driving step is connected to the second detection circuit. Controlling the supply of the detection signal to the first detection circuit at the timing of outputting the detection signal.