JP2001028411A - Spherical semiconductor packaging wiring board and manufacture thereof - Google Patents

Spherical semiconductor packaging wiring board and manufacture thereof

Info

Publication number
JP2001028411A
JP2001028411A JP11201260A JP20126099A JP2001028411A JP 2001028411 A JP2001028411 A JP 2001028411A JP 11201260 A JP11201260 A JP 11201260A JP 20126099 A JP20126099 A JP 20126099A JP 2001028411 A JP2001028411 A JP 2001028411A
Authority
JP
Japan
Prior art keywords
spherical
spherical semiconductor
wiring board
main surface
mounting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP11201260A
Other languages
Japanese (ja)
Inventor
Masao Kuroda
正雄 黒田
Michihiro Matsushima
理浩 松島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Niterra Co Ltd
Original Assignee
NGK Spark Plug Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NGK Spark Plug Co Ltd filed Critical NGK Spark Plug Co Ltd
Priority to JP11201260A priority Critical patent/JP2001028411A/en
Publication of JP2001028411A publication Critical patent/JP2001028411A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16135Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015Shape
    • H01L2924/1017Shape being a sphere
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a spherical semiconductor packaging wiring board of a structure, where spherical semiconductor materials can be mounted with a required strength and the heat dissipation characteristics of the semiconductor materials are also improved. SOLUTION: A spherical semiconductor packaging wiring board 1 comprises mounting parts 20, which are formed in the vicinity of the main surface 3 of the board 1 and respectively have a plurality of pads 18, spherical semiconductor materials 30, which are mounted on the mounting parts 20 by connecting each bump 34 in the vicinities of the bottoms of the spherical semiconductor materials 30 with each pad 18 on the mounting parts 20 via each solder bump 28, and a filling resin 39, which is formed on the main surface 3 and encircles the semiconductor materials 30.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、球面半導体を主面
上に実装する球面半導体実装配線基板及びその製造方法
に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board for mounting a spherical semiconductor on a main surface of a spherical semiconductor and a method for manufacturing the same.

【0002】[0002]

【従来の技術】従来の半導体は、ウェハ上で集積回路を
形成した多数の素子を個別に切り出した平板形状のもの
が一般的である。これに対し、近年では本体が球形から
なる球面半導体が提案されている。係る球面半導体40
は、図6(A)の左上に示すように、シリコン単結晶から
なる球形の本体42の球面上に図示しない集積回路が形
成されると共に、上記本体42の底部付近には上記集積
回路と導通する略球形のバンプ44が複数個リング状に
配置されている。
2. Description of the Related Art Generally, a conventional semiconductor has a flat plate shape obtained by cutting out a large number of elements each having an integrated circuit formed on a wafer. On the other hand, in recent years, spherical semiconductors having a spherical main body have been proposed. Such spherical semiconductor 40
6A, an integrated circuit (not shown) is formed on a spherical surface of a spherical main body 42 made of silicon single crystal, and an electric conduction with the integrated circuit is formed near the bottom of the main body 42, as shown in the upper left of FIG. A plurality of substantially spherical bumps 44 are arranged in a ring shape.

【0003】図6(A)の左側に示すように、上記球面半
導体40を配線基板46の主面47上に実装するには、
主面47上にリング状にして配置した複数の端子48と
上記各バンプ44とをハンダバンプ49を介して接続す
ることにより行われる。また、図6(A)の右側に示すよ
うに、上記球面半導体40の周側面に横向きのバンプ4
5を複数個リング状に配置し、配線基板46の主面47
上において隣接する球面半導体40,40をそれぞれの
バンプ45,45間を予めハンダバンプ49を介して実
装する場合もある(米国特許第5,877,943号公報
参照)。
As shown on the left side of FIG. 6A, in order to mount the spherical semiconductor 40 on a main surface 47 of a wiring board 46,
This is performed by connecting a plurality of terminals 48 arranged in a ring shape on the main surface 47 to the respective bumps 44 via solder bumps 49. Further, as shown on the right side of FIG.
5 are arranged in a ring shape, and the main surface 47 of the wiring board 46 is arranged.
In some cases, adjacent spherical semiconductors 40, 40 are mounted between the bumps 45, 45 via solder bumps 49 in advance (see US Pat. No. 5,877,943).

【0004】しかし、球面半導体40はその本体42が
球形であるため、配線基板46の主面47に接近し端子
48と接続できるのは、本体42の底部付近の各バンプ
44に限られる。即ち、主面47と球面半導体40との
接続は、係る本体42の底部付近の各バンプ44に依存
しているため、実装上の強度が不十分で外力により不用
意にハンダバンプ49が外れて断線し易いという問題が
あった。また、各球面半導体40から発生する熱は、上
記バンプ44のみを介して配線基板46に伝達され且つ
放熱されるため、放熱が十分に行えず球面半導体40自
体の動作が円滑でなくなるという問題もあった。更に、
配線基板46の主面47上において、球面半導体40の
バンプ44と接続できる端子48の数が制限されるた
め、実装される球面半導体40が本来有している機能を
十分に活用できないという問題もあった。
However, since the main body 42 of the spherical semiconductor 40 is spherical, only the bumps 44 near the bottom of the main body 42 can be connected to the main surface 47 of the wiring board 46 and connected to the terminals 48. That is, since the connection between the main surface 47 and the spherical semiconductor 40 depends on each of the bumps 44 near the bottom of the main body 42, the strength in mounting is insufficient and the solder bumps 49 are inadvertently detached by external force and disconnected. There was a problem that it was easy to do. Further, since the heat generated from each spherical semiconductor 40 is transmitted to the wiring board 46 via only the bumps 44 and is radiated, the heat is not sufficiently released, and the operation of the spherical semiconductor 40 itself is not smooth. there were. Furthermore,
Since the number of terminals 48 that can be connected to the bumps 44 of the spherical semiconductor 40 on the main surface 47 of the wiring board 46 is limited, the function inherent in the mounted spherical semiconductor 40 cannot be fully utilized. there were.

【0005】上述した問題点を解決し球面半導体40の
実装強度を高め、且つ配線基板46との接続可能な端子
を増やすため、図6(B)の左側に示すようなアダプタ5
0も提案されている。このアダプタ50は箱型の本体5
2に上向きに開口する略半球形の凹み54を形成し、こ
の凹み54内と本体52の底面との間に、本体52を垂
直に貫通する複数の配線56が平行に配置されている。
また、球面半導体41も図示のように、底部付近の各バ
ンプ44の外周に更に複数のバンプ43をリング状にし
て配置している。
[0005] In order to solve the above-mentioned problems, increase the mounting strength of the spherical semiconductor 40, and increase the number of terminals connectable to the wiring board 46, an adapter 5 as shown on the left side of FIG.
0 has also been proposed. This adapter 50 is a box-shaped main body 5
2, a substantially hemispherical recess 54 opening upward is formed, and a plurality of wirings 56 vertically penetrating the main body 52 are arranged in parallel between the recess 54 and the bottom surface of the main body 52.
As shown in the figure, the spherical semiconductor 41 also has a plurality of bumps 43 arranged in a ring shape on the outer periphery of each bump 44 near the bottom.

【0006】図6(B)の右側に示すように、アダプタ5
0の凹み54内に球面半導体41の略下半分を挿入し、
予め各バンプ43,44と各配線56の上端をハンダ付
けにより接続しておく。次に、係るアダプタ50を配線
基板46の主面47上に配置し、主面47上に内外2重
のリング形状にして配置した各端子48と各配線56の
下端部と個別にハンダ付けする。これにより、配線基板
46の主面47上において球面半導体41を強固に実装
でき且つ放熱特性も高められると共に、多数のバンプ4
3,44が端子48と接続できるため、実装される球面
半導体41の機能を十分に活用することができる(米国
特許第5,877,943号公報参照)。
[0006] As shown on the right side of FIG.
0, the lower half of the spherical semiconductor 41 is inserted into the recess 54,
The upper ends of the bumps 43 and 44 and the wiring 56 are connected in advance by soldering. Next, the adapter 50 is disposed on the main surface 47 of the wiring board 46, and the terminals 48 and the lower ends of the wirings 56 arranged in a double ring shape on the main surface 47 are individually soldered. . Thus, the spherical semiconductor 41 can be firmly mounted on the main surface 47 of the wiring board 46, the heat radiation characteristics can be improved, and the large number of bumps 4
Since the terminals 3 and 44 can be connected to the terminals 48, the function of the mounted spherical semiconductor 41 can be sufficiently utilized (see US Pat. No. 5,877,943).

【0007】[0007]

【発明が解決すべき課題】しかしながら、上述したアダ
プタ50を用いると、実装する球面半導体41毎に上記
アダプタ50が必要となるため、製造コストを増大させ
且つ組立工数も増えてコスト高を招く。しかも、アダプ
タ50を配置するためのスペースが配線基板46の主面
47上に必要となり、配線基板46に求められている小
型・薄肉化の要請にも応えられなくなる、という問題が
あった。本発明は、上記従来の技術における問題点を解
決し、球面半導体を所要の強度をもって実装でき、且つ
その放熱特性も良好にする球面半導体実装配線基板と、
実装すべき球面半導体の数に応じて容易且つ確実に製造
できる上記球面半導体実装配線基板の製造方法を提供す
ることを課題とする。
However, when the above-described adapter 50 is used, the adapter 50 is required for each spherical semiconductor 41 to be mounted, so that the manufacturing cost is increased and the number of assembling steps is increased, resulting in an increase in cost. In addition, a space for arranging the adapter 50 is required on the main surface 47 of the wiring board 46, and there is a problem that it is not possible to meet the demand for a smaller and thinner wall board 46. The present invention solves the above-mentioned problems in the prior art, a spherical semiconductor mounting wiring board that can mount a spherical semiconductor with a required strength, and also has good heat radiation characteristics,
An object of the present invention is to provide a method of manufacturing the above-mentioned spherical semiconductor mounting wiring board, which can be easily and reliably manufactured according to the number of spherical semiconductors to be mounted.

【0008】[0008]

【課題を解決するための手段】本発明は、上記課題を解
決するため、主面上に実装する球面半導体を充填樹脂で
包囲することに着想して得られたものである。即ち、本
発明の球面半導体実装配線基板は、主面近傍に形成され
複数のパッドを有する実装部と、この実装部のパッドに
球面半導体の底部付近のバンプを接続することにより、
上記実装部に実装される球面半導体と、上記主面上に形
成され且つ上記球面半導体を包囲する充填樹脂と、を含
む、ことを特徴とする。
In order to solve the above-mentioned problems, the present invention has been made with the idea of enclosing a spherical semiconductor mounted on a main surface with a filling resin. That is, the spherical semiconductor mounting wiring board of the present invention is formed by connecting a mounting portion formed near the main surface and having a plurality of pads, and a bump near the bottom of the spherical semiconductor to a pad of the mounting portion.
It is characterized by including a spherical semiconductor mounted on the mounting portion and a filling resin formed on the main surface and surrounding the spherical semiconductor.

【0009】これによれば、主面近傍の実装部における
各パッドと底部付近の各バンプとの接続により主面上に
実装された球面半導体は、更にその球形の本体を充填樹
脂により包囲されるので、実装上の強度を高めて接続で
き且つハンダバンプが外れて断線する事態を防止でき
る。しかも、実装された球面半導体の球面上の集積回路
から生じる発熱も、充填樹脂の層を介して配線基板の主
面側に放熱されるので、球面半導体の動作を安定させる
こともできる。尚、上記充填樹脂は、エポキシ系、アク
リル系、フェノール系、ウレタン系、シリコン系、又は
ゴム系樹脂等を配線基板の主面上に塗布し、且つ乾燥し
て硬化させたものである。また、主面近傍とは、主面上
は勿論、主面直下の位置や主面に形成した凹部内も含
む。
According to this, the spherical semiconductor mounted on the main surface by connecting each pad in the mounting portion near the main surface and each bump near the bottom portion is further surrounded by the filled resin. Therefore, it is possible to increase the strength in mounting and to connect, and it is possible to prevent a situation in which the solder bumps come off and break. Moreover, heat generated from the integrated circuit on the spherical surface of the mounted spherical semiconductor is also radiated to the main surface side of the wiring board through the filling resin layer, so that the operation of the spherical semiconductor can be stabilized. The filling resin is obtained by applying an epoxy-based, acrylic-based, phenol-based, urethane-based, silicon-based, or rubber-based resin on the main surface of the wiring board, and drying and curing the resin. Further, the vicinity of the main surface includes not only the position on the main surface but also the position immediately below the main surface and the inside of the concave portion formed on the main surface.

【0010】また、前記球面半導体が複数の前記実装部
に個別に複数個実装され、互いに隣接する球面半導体同
士が、各周側面から突設するバンプを介して接続され、
且つ係るバンプを含む接続部が前記充填樹脂内に埋設さ
れている球面半導体実装配線基板も含まれる。これによ
れば、配線基板の主面上において隣接する球面半導体同
士も、周側面の各バンプを介して直かに接続され且つ係
る接続部も充填樹脂内に埋設されので、各球面半導体間
の動作も直接伝達できると共に、上記接続部も充填樹脂
により防護することができる。
A plurality of the spherical semiconductors are individually mounted on the plurality of mounting portions, and the spherical semiconductors adjacent to each other are connected via bumps protruding from respective peripheral side surfaces,
Further, the present invention also includes a spherical semiconductor mounting wiring board in which a connection portion including the bump is embedded in the filling resin. According to this, the spherical semiconductors adjacent to each other on the main surface of the wiring substrate are also directly connected via the bumps on the peripheral side surface, and such connection portions are embedded in the filling resin. The operation can be directly transmitted, and the connection portion can be protected by the filling resin.

【0011】更に、前記複数の球面半導体の頂部付近の
バンプの上に上段の各球面半導体における底部付近のバ
ンプを接続し、係る上段において互いに隣接する球面半
導体同士が、各周側面から突設するバンプを介して互い
に接続され、且つ係るバンプを含む接続部が前記充填樹
脂内に埋設されている球面半導体実装配線基板も含まれ
る。これによれば、配線基板の主面上に複数段に渉り多
数の球面半導体を実装でき、且つ各段において隣接する
球面半導体同士も直かに接続されると共に、主面上の実
装部と各段における球面半導体、及びこれらの間におけ
る接続部を充填樹脂によって強固に保護し、且つ各球面
半導体の放熱特性を高めることができる。しかも、多数
の球面半導体を実装部や隣接する球面半導体と直接接続
でき、主面上の少ないスペースにおいて高密度にて実装
することも可能となる。
Furthermore, bumps near the bottom of each of the spherical semiconductors in the upper stage are connected to bumps near the top of the plurality of spherical semiconductors, and the spherical semiconductors adjacent to each other in the upper stage protrude from the peripheral side surfaces. The present invention also includes a spherical semiconductor mounting wiring board which is connected to each other via a bump and a connection portion including the bump is embedded in the filling resin. According to this, a large number of spherical semiconductors can be mounted on the main surface of the wiring board in a plurality of steps, and adjacent spherical semiconductors are directly connected to each other in each step, and the mounting parts on the main surface are connected to each other. The spherical semiconductor in each step and the connection between them can be firmly protected by the filling resin, and the heat radiation characteristics of each spherical semiconductor can be enhanced. In addition, a large number of spherical semiconductors can be directly connected to the mounting portion and the adjacent spherical semiconductor, and high-density mounting in a small space on the main surface becomes possible.

【0012】一方、本発明の球面半導体実装配線基板の
製造方法は、配線基板の主面近傍に設けた複数のパッド
からなる実装部に各パッドに球面半導体の底部付近の各
バンプを接続して当該球面半導体を実装する工程と、上
記実装部に実装された球面半導体を包囲するように主面
上に充填樹脂を形成する工程と、を含む、ことを特徴と
する。これによれば、前述した球面半導体実装配線基板
を球面半導体の数に応じて容易且つ確実に製造できる。
しかも、従来のようなアダプタを必要としないので、工
数、コスト、及び実装スペースを低減することも可能で
ある。
On the other hand, according to the method of manufacturing a spherical semiconductor mounted wiring board of the present invention, each pad is connected to each bump near the bottom of the spherical semiconductor to a mounting portion composed of a plurality of pads provided near the main surface of the wiring board. The method includes a step of mounting the spherical semiconductor and a step of forming a filling resin on the main surface so as to surround the spherical semiconductor mounted on the mounting portion. According to this, the above-mentioned spherical semiconductor mounting wiring board can be easily and reliably manufactured according to the number of spherical semiconductors.
In addition, since a conventional adapter is not required, the number of steps, cost, and mounting space can be reduced.

【0013】また、前記球面半導体が複数の前記実装部
に個別に複数個実装され、互いに隣接する球面半導体同
士が、各周側面から突設する各バンプを介して予め互い
に接続されている球面半導体実装配線基板の製造方法も
含まれる。これによれば、配線基板の主面上において隣
接する球面半導体同士は、予め接続された状態で配線基
板の各実装部に実装でき、且つ隣接する球面半導体同士
の接続部を含めて充填樹脂内に埋設することができ、複
数の球面半導体を効率良く実装することができる。更
に、前記球面半導体の実装工程と前記充填樹脂の形成工
程とを交互に繰り返すことにより、前記配線基板の主面
上に球面半導体を複数段に渉り実装すると共に、各段の
球面半導体を包囲するように上記充填樹脂を形成する、
球面半導体実装配線基板の製造方法も含まれる。これに
よれば、主面上において複数段に渉る多数の球面半導体
を強固で且つ高密度に配置して実装した球面半導体実装
配線基板を、確実且つ効率良く得ることができる。
A plurality of the spherical semiconductors are individually mounted on the plurality of mounting portions, and the spherical semiconductors adjacent to each other are connected to each other in advance through bumps protruding from respective peripheral side surfaces. The manufacturing method of the mounting wiring board is also included. According to this, the adjacent spherical semiconductors on the main surface of the wiring board can be mounted on each mounting portion of the wiring board in a state where they are connected in advance, and the filled resin including the connection portion between the adjacent spherical semiconductors can be filled in the filling resin. And a plurality of spherical semiconductors can be efficiently mounted. Further, by alternately repeating the mounting process of the spherical semiconductor and the forming process of the filling resin, the spherical semiconductor is mounted on the main surface of the wiring board in a plurality of stages, and the spherical semiconductor of each stage is surrounded. Forming the filling resin so that
A method for manufacturing a spherical semiconductor mounted wiring board is also included. According to this, it is possible to reliably and efficiently obtain a spherical semiconductor mounted wiring board on which a large number of spherical semiconductors extending over a plurality of stages on the main surface are arranged firmly and densely and mounted.

【0014】[0014]

【発明の実施の形態】以下において本発明の実施に好適
な形態を図面と共に説明する。図1(A)は、本発明によ
る球面半導体実装配線基板1の外観を示す。この基板1
は、薄い箱形状を呈する配線基板2と、その主面3上に
実装された直径約1mmのサイズを有する複数の球面半
導体30と、これらをその頂部を除いて包囲する充填樹
脂39と、を有している。図1(B)に示すように、配線
基板2は、約1.2mmの厚みを有し、その厚さ方向の中
央に位置しBTレジンからなるコア基板4と、これを上
下に貫通する複数のスルーホール導体5を有する。コア
基板4の上下両面上には、第一・第二・第三の配線層
6,10,14と、これらの間に位置し且つエポキシ系樹
脂からなる第一・第二の絶縁層8,12が形成され、各
絶縁層8,12にはその上下の配線層を導通するビア導
体9,13がそれぞれ貫通して配置されている。
Preferred embodiments of the present invention will be described below with reference to the drawings. FIG. 1A shows the appearance of a spherical semiconductor mounted wiring board 1 according to the present invention. This substrate 1
Comprises a wiring board 2 having a thin box shape, a plurality of spherical semiconductors 30 having a size of about 1 mm in diameter mounted on the main surface 3 thereof, and a filling resin 39 surrounding these except for their tops. Have. As shown in FIG. 1B, the wiring board 2 has a thickness of about 1.2 mm, a core board 4 made of BT resin positioned at the center in the thickness direction, and a plurality of Of the through hole conductor 5. On the upper and lower surfaces of the core substrate 4, first, second, and third wiring layers 6, 10, and 14, and first and second insulating layers 8, which are located therebetween and are made of epoxy resin, 12 are formed, and via conductors 9 and 13 for conducting the wiring layers above and below the insulating layers 8 and 12 are arranged to penetrate the insulating layers 8 and 12 respectively.

【0015】また、図1(B)に示すように、上下の第二
の絶縁層12及び第三の配線層14の上には、薄肉のソ
ルダーレジスト層16がそれぞれ形成されている。主面
3側の第三の配線層14の一部は、上記レジスト層16
に被覆されない複数のパッド18を形成している。更
に、底面側の第三の配線層14の一部は、上記レジスト
層16に設けた開口部26内に露出し、外部端子27を
形成している。尚、各配線層6,10,14やビア導体
9,13は、公知のフォトリソグラフィ技術により形成さ
れる。また、上記パッド18や端子27は、その表面に
薄いNiメッキ膜及びAuメッキ膜が被覆されている。
更に、図1(b)に示すように、主面3側の各パッド18
は、平面視で6個ずつがリング状にして配置され、球面
半導体30を個別に実装する実装部20を主面3の近傍
に形成している。
As shown in FIG. 1B, thin solder resist layers 16 are formed on the upper and lower second insulating layers 12 and the third wiring layers 14, respectively. Part of the third wiring layer 14 on the main surface 3 side is made of the resist layer 16
A plurality of pads 18 that are not covered with a pad are formed. Further, a part of the third wiring layer 14 on the bottom side is exposed in the opening 26 provided in the resist layer 16 to form an external terminal 27. The wiring layers 6, 10, 14 and the via conductors 9, 13 are formed by a known photolithography technique. The pad 18 and the terminal 27 are covered with a thin Ni plating film and Au plating film on the surface.
Further, as shown in FIG. 1B, each of the pads 18 on the main surface 3 side
Are arranged in a ring shape in plan view, and a mounting portion 20 for individually mounting the spherical semiconductors 30 is formed near the main surface 3.

【0016】図1(B)に示すように、各球面半導体30
における球形の本体32底部付近には6個のバンプ34
が突設され、且つ実装部20の各パッド18とハンダバ
ンプ28を介して接続されている。これにより、各球面
半導体30の本体32上に形成されている図示しない集
積回路と、配線基板2内の前記配線層6,10,14とが
導通される。また、隣接する球面半導体30,30の各
本体32における周側面にも複数のバンプ36が突設さ
れ、互いに近接して対向するバンプ36,36間にハン
ダバンプ38を介在させることにより、隣接する球面半
導体30同士を接続し、各本体32の表面に形成された
集積回路同士の間を導通している。
As shown in FIG. 1B, each spherical semiconductor 30
6 bumps 34 near the bottom of the spherical body 32
Are protruded, and are connected to the respective pads 18 of the mounting portion 20 via solder bumps 28. Thereby, the integrated circuit (not shown) formed on the main body 32 of each spherical semiconductor 30 and the wiring layers 6, 10, and 14 in the wiring board 2 are electrically connected. A plurality of bumps 36 are also provided on the peripheral side surface of each of the main bodies 32 of the adjacent spherical semiconductors 30, 30. The semiconductors 30 are connected to each other, and the integrated circuits formed on the surface of each main body 32 are electrically connected to each other.

【0017】更に、図1(A)及び(B)に示すように、各
球面半導体30は、その本体32の頂部を除いて充填樹
脂39に埋設され且つ包囲されている。このため、各球
面半導体30は、配線基板2の各実装部20に強固に実
装され、上述した導通状態を確保すると共に、本体32
表面の集積回路による発熱も、充填樹脂39を介して配
線基板2側に放出することができる。従って、係る球面
半導体実装配線基板1によれば、複数の球面半導体30
を主面3上に確実に実装でき、且つ配線基板2内部の配
線層6,10,14と正確に導通できると共に、複数の球
面半導体30同士も互いに本体32の表面上の各集積回
路と導通できる。しかも、各球面半導体30は、充填樹
脂39を介して容易に放熱できるので、その機能を安定
して発揮させることも可能となる。尚、球面半導体30
は、充填樹脂39内にその本体32を全て埋設しても良
い。
Further, as shown in FIGS. 1A and 1B, each spherical semiconductor 30 is buried and surrounded by a filling resin 39 except for the top of its main body 32. For this reason, each spherical semiconductor 30 is firmly mounted on each mounting portion 20 of the wiring board 2, while maintaining the above-described conductive state and the main body 32.
Heat generated by the integrated circuit on the surface can also be released to the wiring board 2 via the filling resin 39. Therefore, according to the spherical semiconductor mounting wiring board 1, the plurality of spherical semiconductors 30
Can be reliably mounted on the main surface 3 and can accurately conduct with the wiring layers 6, 10, and 14 inside the wiring board 2, and the plurality of spherical semiconductors 30 can also communicate with each integrated circuit on the surface of the main body 32. it can. In addition, since each spherical semiconductor 30 can easily radiate heat via the filling resin 39, it is possible to exhibit its function stably. The spherical semiconductor 30
Alternatively, the entire body 32 may be embedded in the filling resin 39.

【0018】ここで、上述した球面半導体実装配線基板
1の製造方法を図2,3で説明する。図2(A)は、配線
基板2の主面3付近の端面を示し、第二の絶縁層12の
上に6個ずつのパッド18からなる複数の実装部20が
配置されている。図2(A)に示すように、各パッド18
は、その周縁をソルダーレジスト層16に覆われると共
に、開口部22を通じて主面3側に露出している。図2
(B)に示すように、予め各本体32の周側面におけるバ
ンプ36同士をハンダバンプ38を介して隣接する球面
半導体30と接続した所要数の球面半導体30の集合体
を形成する。次に、図2(C)に示すように、各パッド1
8上に予め形成された半球体形状のハンダバンプ28に
球面半導体30の本体32底部におけるバンプ34を接
触させる。この状態でハンダバンプ28を加熱すること
により、複数の球面半導体30は、個別に基板2の主面
3近傍における各実装部20に実装される。
Here, a method of manufacturing the above-described spherical semiconductor mounted wiring board 1 will be described with reference to FIGS. FIG. 2A shows an end surface near the main surface 3 of the wiring board 2, and a plurality of mounting portions 20 each including six pads 18 are arranged on the second insulating layer 12. As shown in FIG.
Is covered with the solder resist layer 16 and is exposed to the main surface 3 through the opening 22. FIG.
As shown in FIG. 2B, a required number of spherical semiconductors 30 in which bumps 36 on the peripheral side surface of each body 32 are connected to adjacent spherical semiconductors 30 via solder bumps 38 are formed in advance. Next, as shown in FIG.
The bump 34 at the bottom of the main body 32 of the spherical semiconductor 30 is brought into contact with the hemispherical solder bump 28 formed in advance on the surface 8. By heating the solder bumps 28 in this state, the plurality of spherical semiconductors 30 are individually mounted on the mounting portions 20 near the main surface 3 of the substrate 2.

【0019】そして、図3(A)及び(B)に示すように、
主面3上で且つ実装された各球面半導体30,30間
に、図示しないディスペンサを用いて充填樹脂39を充
填しその層を形成する。この充填樹脂39は、例えばエ
ポキシ系樹脂からなり、液状の状態でディスペンサから
定量ずつ吐出され且つ乾燥して硬化する。図3(A)に示
すように、係る充填樹脂39を1層又は何層かに分けて
順次充填することにより、各実装部20を埋設する。更
に、図3(B)に示すように、隣接する球面半導体30,
30間の接続部(36,38,36)も埋設し、各球面半導
体30をその本体32の頂部付近を除いて充填樹脂39
で包囲する。
Then, as shown in FIGS. 3A and 3B,
A filling resin 39 is filled on the main surface 3 and between the mounted spherical semiconductors 30, 30 using a dispenser (not shown) to form a layer thereof. The filling resin 39 is made of, for example, an epoxy resin, and is discharged in a liquid state from the dispenser by a fixed amount, dried, and cured. As shown in FIG. 3A, each of the mounting portions 20 is buried by sequentially filling the filling resin 39 into one or several layers. Further, as shown in FIG.
The connection portions (36, 38, 36) between the spherical semiconductors 30 are also buried, and each spherical semiconductor 30 is filled with a resin 39 except for the vicinity of the top of the main body 32.
Surround with.

【0020】これにより、主面3上に実装した各球面半
導体30の実装上の強度を補強し安定させることができ
ると共に、球面半導体30,30間の接続部(36,38,
36)も保護することができる。尚、充填樹脂39に
は、アクリル系、フェノール系、ウレタン系、シリコン
系、又はゴム系樹脂等を用いることも可能である。ま
た、充填樹脂39の表面上に突出する各球面半導体30
の本体32の頂部には、当該球面半導体30の種類を示
す識別マークを付しておくこともできる。或いは、図1
に示したように、配線基板2の主面3上に一段のみで球
面半導体30,30を実装する形態では、各球面半導体3
0の本体32全てを充填樹脂39内に埋設して包囲する
こともできる。
As a result, the mounting strength of each of the spherical semiconductors 30 mounted on the main surface 3 can be reinforced and stabilized, and the connection portions (36, 38, 38) between the spherical semiconductors 30, 30 can be provided.
36) can also be protected. Note that, as the filling resin 39, an acrylic resin, a phenol resin, a urethane resin, a silicon resin, a rubber resin, or the like can be used. Further, each spherical semiconductor 30 projecting on the surface of the filling resin 39 is formed.
An identification mark indicating the type of the spherical semiconductor 30 can be provided on the top of the main body 32 of the first embodiment. Or Figure 1
As shown in FIG. 3, in the mode in which the spherical semiconductors 30 are mounted on the main surface 3 of the wiring board 2 in only one step, each spherical semiconductor 3
It is also possible to embed and surround the entirety of the main body 32 of the zero.

【0021】図4は異なる形態の球面半導体実装配線基
板等に関する。尚、以下において前記形態と同じ部分や
要素には、共通する符号を用いるものとする。図4(A)
は、図2〜図3と同じ方法で、配線基板2の主面3上に
複数の球面半導体30を一段にて各実装部20に実装
し、且つこれらを本体32の頂部付近を除き充填樹脂3
9にて包囲した状態を示す。各球面半導体30の本体3
2の頂部付近には、平面視で6個のバンプ35が予め突
設されている。次に、図4(B)に示すように、予め各本
体32の周側面におけるバンプ36同士をハンダバンプ
38を介して隣接する球面半導体30と接続した第二段
目となる複数の球面半導体30を、上記第一段目の各球
面半導体30に接近し、両者のバンプ35,34をハン
ダバンプ38を介してそれぞれ接続する。
FIG. 4 relates to a spherical semiconductor mounted wiring board of a different form. In the following, the same reference numerals are used for the same parts and elements as in the above embodiment. FIG. 4 (A)
In the same manner as in FIGS. 2 and 3, a plurality of spherical semiconductors 30 are mounted on the mounting surface 20 in one step on the main surface 3 of the wiring board 2, and these are filled with resin except for near the top of the main body 32. 3
9 shows a state of being surrounded. Body 3 of each spherical semiconductor 30
In the vicinity of the top of 2, two bumps 35 are provided in advance in plan view. Next, as shown in FIG. 4B, a plurality of second-stage spherical semiconductors 30 in which bumps 36 on the peripheral side surface of each main body 32 are connected in advance to adjacent spherical semiconductors 30 via solder bumps 38 are formed. The bumps 35 and 34 of the first-stage spherical semiconductor 30 are connected to each other via solder bumps 38.

【0022】この結果、第一段及び第二段目の各球面半
導体30は、その表面に形成された集積回路同士が導通
すると共に、第二段目の各球面半導体30の集積回路
も、配線基板2内の前記配線層6,10,14とそれぞれ
導通される。そして、図4(B)に示すように、第二段目
の各球面半導体30をその本体32の頂部付近を除い
て、充填樹脂39にて包囲することにより、多数の球面
半導体30を立体的に配置して実装した球面半導体実装
配線基板1aを得ることができる。尚、第二段目におけ
る各球面半導体30の本体32の頂部には、当該球面半
導体30と共に、その直下に位置する第一段目の球面半
導体30の種類を表示する識別マークを付しても良い。
また、第二段目の各球面半導体30の本体32の各頂部
にも上記同様にバンプ35を突設しておくことにより、
これらの上に第三段目以上に位置する多数の球面半導体
30,30,…を接続できる。この形態でも、最上段目に
おける各球面半導体30は、その本体32の頂部付近を
除いて充填樹脂39にて包囲される。勿論、最上段の各
球面半導体30の本体32を充填樹脂39内に埋設する
こともできる。
As a result, the first-stage and second-stage spherical semiconductors 30 are electrically connected to each other on the surface thereof, and the second-stage spherical semiconductors 30 are also connected to the wiring. It is electrically connected to the wiring layers 6, 10, and 14 in the substrate 2, respectively. Then, as shown in FIG. 4 (B), by enclosing each spherical semiconductor 30 in the second stage with the filling resin 39 except for the vicinity of the top of the main body 32, many spherical semiconductors 30 are three-dimensionally formed. Can be obtained. Note that, at the top of the main body 32 of each spherical semiconductor 30 in the second stage, together with the spherical semiconductor 30, an identification mark indicating the type of the first stage spherical semiconductor 30 located immediately below the spherical semiconductor 30 may be attached. good.
In addition, the bumps 35 are also protruded from the tops of the main bodies 32 of the spherical semiconductors 30 in the second stage in the same manner as described above.
On these, a large number of spherical semiconductors 30, 30,... Located at the third stage or higher can be connected. Also in this embodiment, each spherical semiconductor 30 in the uppermost stage is surrounded by the filling resin 39 except for the vicinity of the top of the main body 32. Of course, the main body 32 of each spherical semiconductor 30 at the top can be embedded in the filling resin 39.

【0023】図4(C)は、異なる形態の実装部21を示
す。この実装部21は、平面視で内周側に位置する前記
6個のパット18と、その周囲にリング状に配置された
12個のパット18aとからなる。図4(D)に示すよう
に、内周側の各パット18の上には低いハンダバンプ2
8が、外周側の各パット18aの上にはやや高いハンダ
バンプ29が立設されている。また、球面半導体30の
本体32底部には、上記ハンダバンプ28に対応するバ
ンプ34の外側に上記各ハンダバンプ29に対応する同
数のバンプ34aが突設されている。従って、図4(D)
に示すように、ハンダバンプ28,29とバンプ34,3
4aとを個別に接続すると、当該球面半導体30の本体
32の表面上に形成された集積回路と、配線基板2内の
配線層6,10,14とを一層緻密に導通でき、実装し
た球面半導体30の機能を一層確実に引き出すことが可
能となる。尚、上記球面半導体30の本体32も、前記
形態と同様に充填樹脂39に包囲される。
FIG. 4C shows a mounting section 21 having a different form. The mounting portion 21 includes the six pads 18 located on the inner peripheral side in a plan view, and twelve pads 18a arranged around the pads 18 in a ring shape. As shown in FIG. 4D, a low solder bump 2 is formed on each pad 18 on the inner peripheral side.
8, a slightly high solder bump 29 is erected on each pad 18a on the outer peripheral side. In addition, the same number of bumps 34 a corresponding to each of the solder bumps 29 protrude from the bottom of the main body 32 of the spherical semiconductor 30 outside the bump 34 corresponding to the solder bump 28. Therefore, FIG.
As shown in the figure, the solder bumps 28, 29 and the bumps 34, 3
4a, the integrated circuit formed on the surface of the main body 32 of the spherical semiconductor 30 and the wiring layers 6, 10, and 14 in the wiring board 2 can be conducted more densely, and the mounted spherical semiconductor 30 functions can be more reliably extracted. The main body 32 of the spherical semiconductor 30 is also surrounded by the filling resin 39 as in the above-described embodiment.

【0024】図5(A)及び(B)は、更に異なる形態の実
装部24を示す。実装部24は、前記配線基板2のソル
ダーレジスト層16及び第二の絶縁層12に平面視で円
形の凹部11を有し、この凹部11内に露出する第一の
絶縁層8の上に第二の配線層10の6本の端部が略求心
に配置され、それらの先端のパッド18b上にハンダバ
ンプ28aが固着される。また、凹部11の周縁上に沿
って配置される12個のパット18上には、それぞれハ
ンダバンプ28が固着されている。以上のような実装部
24も、配線基板2における主面3の近傍に形成された
ものである。
FIGS. 5A and 5B show a mounting section 24 having a further different form. The mounting portion 24 has a circular concave portion 11 in a plan view in the solder resist layer 16 and the second insulating layer 12 of the wiring board 2, and a first concave portion 11 is formed on the first insulating layer 8 exposed in the concave portion 11. The six ends of the two wiring layers 10 are substantially centripetally arranged, and the solder bumps 28a are fixed on the pads 18b at the ends thereof. Further, solder bumps 28 are fixed on the twelve pads 18 arranged along the periphery of the concave portion 11, respectively. The mounting section 24 as described above is also formed near the main surface 3 of the wiring board 2.

【0025】図5(C)に示すように、球面半導体30の
本体32の底部付近における6個のバンプ34とその外
側に12個のバンプ34aを、実装部24の各ハンダバ
ンプ28a,28上に載置し、且つ各バンプ28a,28
を加熱する。これにより、各バンプ28a,28を介し
て球面半導体30のバンプ34,34aと実装部24の
パッド18b,18が接続される。この球面半導体30
もその本体32の頂部付近を除き、図5(C)に示すよう
に、充填樹脂39により包囲される。係る形態によれ
ば、球面半導体30は、多くのバンプ34,34aを介し
て配線基板2内の配線層6,10,14と導通され、その
本体32上の集積回路を十分に機能させ得ると共に、係
る本体32も充填樹脂39によって実装部24に強固に
実装することができる。
As shown in FIG. 5C, six bumps 34 near the bottom of the main body 32 of the spherical semiconductor 30 and twelve bumps 34a on the outside thereof are placed on the solder bumps 28a, 28 of the mounting part 24. Placed and each bump 28a, 28
Heat. Thus, the bumps 34, 34a of the spherical semiconductor 30 and the pads 18b, 18 of the mounting portion 24 are connected via the bumps 28a, 28. This spherical semiconductor 30
Except for the vicinity of the top of the main body 32 as well, as shown in FIG. According to such an embodiment, the spherical semiconductor 30 is electrically connected to the wiring layers 6, 10, and 14 in the wiring board 2 via the many bumps 34 and 34a, so that the integrated circuit on the main body 32 can function sufficiently. The main body 32 can also be firmly mounted on the mounting portion 24 by the filling resin 39.

【0026】本発明は、以上において説明した各形態に
限定されるものではない。例えば、配線基板2の主面3
上に実装する球面半導体30の数は任意であり、且つ主
面3上の各段における数も任意である。また、互いに異
なる直径を有する球面半導体30同士を主面3上に実装
し、又は各段中に配置しても良い。この際、実装部2
0,21,24の位置は各球面半導体の直径に応じて配置
する。しかも、実装部20,21,24の配置も任意であ
り、且つこれらのパッド18等を主面3上に配置しても
良い。更に、充填樹脂39は、球面半導体30の実装パ
ターンに応じて、主面3上において複数の部分に分割し
て形成することもできる。尚、本発明が適用される配線
基板には、セラミック絶縁層の間に配線層を配置したセ
ラミック製の配線基板も含まれる。また、樹脂製やセラ
ミック製の多層配線基板に限らず、樹脂製やセラミック
製の単層配線基板も含まれる。
The present invention is not limited to the embodiments described above. For example, the main surface 3 of the wiring board 2
The number of the spherical semiconductors 30 mounted on the upper surface is arbitrary, and the number of each stage on the main surface 3 is also arbitrary. Further, the spherical semiconductors 30 having different diameters may be mounted on the main surface 3 or arranged in each stage. At this time, the mounting unit 2
The positions of 0, 21, and 24 are arranged according to the diameter of each spherical semiconductor. Moreover, the arrangement of the mounting portions 20, 21, 24 is arbitrary, and the pads 18 and the like may be arranged on the main surface 3. Further, the filling resin 39 can be formed by being divided into a plurality of portions on the main surface 3 according to the mounting pattern of the spherical semiconductor 30. The wiring board to which the present invention is applied includes a ceramic wiring board in which a wiring layer is disposed between ceramic insulating layers. Further, the present invention includes not only a resin or ceramic multilayer wiring board but also a resin or ceramic single layer wiring board.

【0027】[0027]

【発明の効果】以上において説明した本発明の球面半導
体実装配線基板によれば、主面上に実装した球面半導体
は、その球面の本体を充填樹脂により包囲されるので、
実装上の強度を高められ且つ接続部が外れて断線するこ
とを防止できる。しかも、実装された球面半導体におけ
る球面の集積回路から生じる発熱も、充填樹脂の層を介
して配線基板の主面側に放熱されるので、球面半導体の
動作を安定させることもできる。また、請求項3の球面
半導体実装配線基板によれば、主面上に複数段に渉り多
数の球面半導体を高密度で実装でき、且つ各段において
隣接する球面半導体同士も直かに接続される。しかも、
主面近傍の実装部と各段における球面半導体、及びこれ
らの間における接続部を充填樹脂にて強固に保護し、且
つ各球面半導体の放熱特性を高めることができる。
According to the spherical semiconductor mounting wiring board of the present invention described above, the spherical semiconductor mounted on the main surface has its spherical main body surrounded by the filling resin.
The mounting strength can be increased, and the disconnection of the connection portion can be prevented. In addition, heat generated from the spherical integrated circuit in the mounted spherical semiconductor is also radiated to the main surface side of the wiring board through the filling resin layer, so that the operation of the spherical semiconductor can be stabilized. According to the spherical semiconductor mounting wiring board of the third aspect, a large number of spherical semiconductors can be mounted on the main surface in a plurality of stages at high density, and adjacent spherical semiconductors are directly connected to each other in each stage. You. Moreover,
The mounting portion near the main surface, the spherical semiconductor in each step, and the connecting portion between them can be firmly protected by the filling resin, and the heat radiation characteristics of each spherical semiconductor can be improved.

【0028】一方、本発明の製造方法によれば、前記球
面半導体実装配線基板を球面半導体の数に応じて容易且
つ確実に製造でき、且つ従来のようなアダプタを必要と
しないので、工数、コスト、及び実装スペースを低減す
ることも可能である。また、請求項6の製造方法によれ
ば、主面上に複数段に渉って多数の球面半導体を高密度
で強固に立体配置して実装した球面半導体実装配線基板
を、確実且つ効率良く得ることができる。
On the other hand, according to the manufacturing method of the present invention, the spherical semiconductor mounting wiring board can be easily and reliably manufactured in accordance with the number of the spherical semiconductors, and the conventional adapter is not required. , And the mounting space can be reduced. Further, according to the manufacturing method of the sixth aspect, a spherical semiconductor mounted wiring board in which a large number of spherical semiconductors are densely and firmly three-dimensionally mounted on a main surface in a plurality of stages and mounted is reliably and efficiently obtained. be able to.

【図面の簡単な説明】[Brief description of the drawings]

【図1】(A)は本発明の球面半導体実装配線基板を示す
斜視図、(B)は(A)中のB−B線に沿った断面図、(b)
は(B)中の配線基板の実装部を示す概略平面図。
FIG. 1A is a perspective view showing a spherical semiconductor mounting wiring board of the present invention, FIG. 1B is a cross-sectional view taken along line BB in FIG. 1A, and FIG.
3 is a schematic plan view showing a mounting portion of the wiring board in (B).

【図2】(A)乃至(C)は本発明の球面半導体実装配線基
板の各製造工程を示す概略図。
FIGS. 2A to 2C are schematic diagrams showing respective manufacturing steps of a spherical semiconductor mounted wiring board of the present invention.

【図3】(A)及び(B)は図2(C)に続く各製造工程を示
す概略図。
3 (A) and 3 (B) are schematic views showing respective manufacturing steps following FIG. 2 (C).

【図4】(A)及び(B)は異なる形態の球面半導体実装配
線基板を得るための各製造工程を示す概略図、(C)は異
なる形態の実装部を示す概略平面図、(D)は(C)の実装
部に球面半導体を実装した状態を示す(C)中のD−D線
に沿う概略断面図。
4 (A) and 4 (B) are schematic views showing respective manufacturing steps for obtaining a spherical semiconductor mounting wiring board having different forms, FIG. 4 (C) is a schematic plan view showing a mounting section having different forms, and FIG. 4 (D). FIG. 4 is a schematic cross-sectional view taken along line DD in FIG. 4C, showing a state in which a spherical semiconductor is mounted on the mounting portion of FIG.

【図5】(A)は更に異なる形態の実装部を示す概略平面
図、(B)は(A)中のB−B線に沿った端面図、(C)は係
る実装部に球面半導体を実装した状態を示す概略図。
5A is a schematic plan view showing a mounting portion in a further different form, FIG. 5B is an end view along line BB in FIG. 5A, and FIG. FIG. 3 is a schematic diagram showing a mounted state.

【図6】(A)及び(B)は配線基板の主面上に球面半導体
を実装する従来の技術を示す概略図。
FIGS. 6A and 6B are schematic diagrams showing a conventional technique for mounting a spherical semiconductor on a main surface of a wiring board.

【符号の説明】[Explanation of symbols]

1,1a……………………球面半導体実装配線基板 2……………………………配線基板 3……………………………主面 18,18a,18b………パッド 20,21,24……………実装部 30…………………………球面半導体 34,34a,35,36…バンプ 39…………………………充填樹脂 1, 1a ………………………………………………………………………………………………………… Wiring board 3 ………………………………… Main surface 18, 18a, 18b ...... Pad 20,21,24 ............ Mounting part 30 ...... Spherical semiconductor 34,34a, 35,36 Bump 39 ............ Filled resin

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】主面近傍に形成され複数のパッドを有する
実装部と、 上記実装部のパッドに球面半導体の底部付近のバンプを
接続することにより、上記実装部に実装される球面半導
体と、 上記主面上に形成され且つ上記球面半導体を包囲する充
填樹脂と、を含む、ことを特徴とする球面半導体実装配
線基板。
1. A mounting portion formed near a main surface and having a plurality of pads; and a spherical semiconductor mounted on the mounting portion by connecting a bump near a bottom portion of the spherical semiconductor to a pad of the mounting portion; And a filling resin formed on the main surface and surrounding the spherical semiconductor.
【請求項2】前記球面半導体が複数の前記実装部に個別
に複数個実装され、互いに隣接する球面半導体同士が、
各周側面から突設するバンプを介して接続され、且つ係
るバンプを含む接続部が前記充填樹脂内に埋設されてい
る、 ことを特徴とする請求項1に記載の球面半導体実装配線
基板。
2. A plurality of spherical semiconductors are individually mounted on a plurality of mounting portions, and adjacent spherical semiconductors are
The spherical semiconductor mounting wiring board according to claim 1, wherein the connection is made via bumps projecting from the respective peripheral side surfaces, and a connection part including the bumps is embedded in the filling resin.
【請求項3】前記複数の球面半導体の頂部付近のバンプ
の上に上段の各球面半導体における底部付近のバンプを
接続し、係る上段において互いに隣接する球面半導体同
士が、各周側面から突設するバンプを介して互いに接続
され、且つ係るバンプを含む接続部が前記充填樹脂内に
埋設されている、 ことを特徴とする請求項2に記載の球面半導体実装配線
基板。
3. A bump near the bottom of each of the spherical semiconductors in the upper stage is connected to a bump near the top of the plurality of spherical semiconductors, and the spherical semiconductors adjacent to each other in the upper stage protrude from respective peripheral side surfaces. The spherical semiconductor-mounted wiring board according to claim 2, wherein the connection part connected to each other via the bump and including the bump is buried in the filling resin.
【請求項4】配線基板の主面近傍に設けた複数のパッド
からなる実装部に各パッドに球面半導体の底部付近の各
バンプを接続して当該球面半導体を実装する工程と、 上記実装部に実装された球面半導体を包囲するように主
面上に充填樹脂を形成する工程と、を含む、 ことを特徴とする球面半導体実装配線基板の製造方法。
4. A step of connecting each bump near the bottom of the spherical semiconductor to each pad to a mounting section comprising a plurality of pads provided near the main surface of the wiring board to mount the spherical semiconductor; Forming a filling resin on the main surface so as to surround the mounted spherical semiconductor.
【請求項5】前記球面半導体が複数の前記実装部に個別
に複数個実装され、 互いに隣接する球面半導体同士が、各周側面から突設す
る各バンプを介して予め互いに接続されている、 ことを特徴とする請求項4に記載の球面半導体実装配線
基板の製造方法。
5. A plurality of said spherical semiconductors are individually mounted on a plurality of said mounting portions, and mutually adjacent spherical semiconductors are connected to each other in advance via respective bumps projecting from respective peripheral side surfaces. 5. The method for manufacturing a spherical semiconductor mounted wiring board according to claim 4, wherein:
【請求項6】前記球面半導体の実装工程と前記充填樹脂
の形成工程とを交互に繰り返すことにより、 前記配線基板の主面上に球面半導体を複数段に渉り実装
すると共に、 各段の球面半導体を包囲するように上記充填樹脂を形成
する、ことを特徴とする請求項4又は5に記載の球面半
導体実装配線基板の製造方法。
6. A process for mounting the spherical semiconductor on the main surface of the wiring board in a plurality of steps by alternately repeating the mounting step of the spherical semiconductor and the forming step of the filling resin, and the spherical surface of each step. The method according to claim 4, wherein the filling resin is formed so as to surround the semiconductor.
JP11201260A 1999-07-15 1999-07-15 Spherical semiconductor packaging wiring board and manufacture thereof Withdrawn JP2001028411A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11201260A JP2001028411A (en) 1999-07-15 1999-07-15 Spherical semiconductor packaging wiring board and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11201260A JP2001028411A (en) 1999-07-15 1999-07-15 Spherical semiconductor packaging wiring board and manufacture thereof

Publications (1)

Publication Number Publication Date
JP2001028411A true JP2001028411A (en) 2001-01-30

Family

ID=16438006

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11201260A Withdrawn JP2001028411A (en) 1999-07-15 1999-07-15 Spherical semiconductor packaging wiring board and manufacture thereof

Country Status (1)

Country Link
JP (1) JP2001028411A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003007958A (en) * 2001-06-22 2003-01-10 Sharp Corp Semiconductor device
JP2003046077A (en) * 2001-08-02 2003-02-14 Hitachi Maxell Ltd Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003007958A (en) * 2001-06-22 2003-01-10 Sharp Corp Semiconductor device
JP2003046077A (en) * 2001-08-02 2003-02-14 Hitachi Maxell Ltd Semiconductor device

Similar Documents

Publication Publication Date Title
US6781224B2 (en) Semiconductor device and package including forming pyramid mount protruding through silicon substrate
US8004089B2 (en) Semiconductor device having wiring line and manufacturing method thereof
US7161242B2 (en) Semiconductor device, semiconductor device substrate, and manufacturing method thereof that can increase reliability in mounting a semiconductor element
JP4380130B2 (en) Semiconductor device
US8294253B2 (en) Semiconductor device, electronic device and method of manufacturing semiconductor device, having electronic component, sealing resin and multilayer wiring structure
US9301391B2 (en) Substrate structure, semiconductor package device, and manufacturing method of substrate structure
JP2017038075A (en) Stackable molded ultra small electronic package including area array unit connector
US6236112B1 (en) Semiconductor device, connecting substrate therefor, and process of manufacturing connecting substrate
TWI647790B (en) Polymer component-based interconnect
JP6606331B2 (en) Electronic equipment
JPH10270592A (en) Semiconductor device and manufacture thereof
US20020070446A1 (en) Semiconductor device and method for the production thereof
KR100907508B1 (en) Package board and its manufacturing method
US7972903B2 (en) Semiconductor device having wiring line and manufacturing method thereof
JP5017872B2 (en) Semiconductor device and manufacturing method thereof
US20130214390A1 (en) Tsv substrate structure and the stacked assembly thereof
US6256207B1 (en) Chip-sized semiconductor device and process for making same
JP4061506B2 (en) Manufacturing method of semiconductor device
US6369331B1 (en) Printed circuit board for semiconductor package and method of making same
JP7302784B2 (en) Interposer and package structure including the same
US7420131B2 (en) Wiring substrate
US6344695B1 (en) Semiconductor device to be mounted on main circuit board and process for manufacturing same device
KR102050011B1 (en) Interconnect structure for semiconductor package and method of fabricating the interconnect structure
US7632707B2 (en) Electronic device package and method of manufacturing the same
JP2001028411A (en) Spherical semiconductor packaging wiring board and manufacture thereof

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20051101

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20060510

A761 Written withdrawal of application

Free format text: JAPANESE INTERMEDIATE CODE: A761

Effective date: 20070405