JP2001028405A - Semiconductor device electrical characteristic evaluation apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor device electrical characteristics evaluation apparatus, which executes analysis of the electrical characteristics of a nonvolatile memory having a three-dimensional form in a two-dimensional simulation. SOLUTION: This evaluation apparatus has a means 11 for reading information on the impurity density in the interior of a semiconductor device, the material and the external shape of the device and the like, which results from two-dimensional process simulation, a means 12 for reading information on the material, the external shape and the like in the direction vertical to the section of the device which is the result of the two-dimensional process simulation, a means 13 for executing a capacity simulation about the shape of the section in the vertical direction of the device, a means 14 for changing the external shape such as the forms of the thickness of an insulating film which are the results of the two-dimensional process simulation from the result of the capacity simulation, a means 15 for specifying the conditions of calculation of a terminal voltage, the time of a voltage application and the like for making device simulation, a means 15 for making a device simulation for calculating potential and electron-hole density distribution in the interior of the device, the current- voltage characteristics of the element and the like and a means 17 for outputting the results through a means desired by users.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of calculating the electrical characteristics of a semiconductor device by numerical calculation, by using a physical quantity representing the electrical characteristics inside the semiconductor device, for example, at a predetermined position of at least one of an electrical potential, an electron density and a hole density. And, more particularly, to an apparatus for evaluating electrical characteristics of a nonvolatile memory.

[0002]

2. Description of the Related Art In recent years, with the increasing complexity and diversification of semiconductor devices, it has become increasingly important to analyze the characteristics of devices using a semiconductor process device simulation apparatus. Also, the use of the results of process device simulation as a guideline for determining a process step that satisfies desired electrical characteristics has been actively performed.

[0003] A conventional semiconductor process simulation apparatus will be described. A process for manufacturing a semiconductor device usually includes a number of steps.
This information is input after being replaced with a language or the like that can be recognized by the process simulation apparatus. This input may be manually input by the user or may be automatically converted from electronic information by some sort of interprinter device. The process simulation apparatus faithfully executes a numerical simulation for all steps of the process, and virtually creates a semiconductor device on an electronic computer. The process simulation method is described in I.E.E.E.E.Transaction on Electron Devices E.D.34 (198
7 years) Pages 2217 to 2219 (IEEE Trans. El
ectron Devices ED-34 pp.2217-2219 (1987)). This process simulation result is usually stored on a database as an electronic file,
The result is appropriately output to a printer or a graphic output on a terminal, and the result analysis is executed in a format desired by the user. The process simulation result file describes the external shape of the element, information on the material constituting the element, information on the impurity concentration, and the like. Hereinafter, a conventional semiconductor device electrical characteristic evaluation apparatus that predicts electrical characteristics of a non-volatile memory using device simulation using process simulation results will be described.

First, a process result input unit reads a file in which the external shape of an element, material information constituting the element, impurity concentration information, and the like, which are created by the above-described known process simulation apparatus, are described. Next, the user input unit reads the information on the terminal voltage specified by the user. Next, the device simulation unit sets a predetermined voltage at the electrode position desired by the user, and analyzes what internal electrical characteristics are and what current-voltage characteristics can be obtained. This is known as device simulation technology and is described in Analysis and Simulation of Semiconductor Devices, 1984, Springer Berlag, author S. Selberherr, A.
nalysis and Simulation of Semiconductor Devices, S
pringer-Verlag, 1984).

According to this technique, grids are drawn in the horizontal and vertical directions for discretization inside a semiconductor device, for example, as shown in FIG. 10, and grid points of their intersections are provided. , The electron current continuous equation, and the hole current continuous equation are solved for unknown potentials, electron densities, and hole densities. It is usually realized on a large computer in the form of a program that solves these equations numerically.

Here, a typical nonvolatile memory structure will be described with reference to FIG. 91 is a first diffusion layer,
92 is a second diffusion layer, 93 is a semiconductor substrate, 94 is a floating gate, 95 is a control gate, 96 is a first insulating film, 97 is a second insulating film, 98 is an element isolation film, and 99 is an erase gate. is there. Non-volatile memory features include a floating gate 94,
It is to determine whether data is "1" or "0" by reading whether or not charges are accumulated inside the floating gate 94.

To accumulate charges in the floating gate 94, a predetermined voltage is applied to the second diffusion layer 92 and the control gate 95, and a high electric field applied near the junction between the second diffusion layer 92 and the semiconductor substrate 93 is applied. Hot carriers generated by the first insulating film 96 are injected into the floating gate 94 through the first insulating film 96. Such an operation is called a writing phenomenon of the nonvolatile memory.

To erase charges from the floating gate 94, a predetermined voltage is applied to the control gate 95 and the second insulating film 9
7, a charge is passed through the second insulating film 97 by a tunnel phenomenon due to a high electric field, and the charge is released from the control gate 95 through the electrode. Alternatively, a predetermined voltage is applied to the second diffusion layer 92, There is a method in which charges are passed through the first insulating film 96 by a tunnel phenomenon due to a high electric field applied to the insulating film 96 to discharge the charges from the second diffusion layer 92 through the electrodes. Such an operation is called an erasing phenomenon of the nonvolatile memory.

In order to read whether the floating gate 94 has accumulated or erased charges, the control gate 9
5 and the second diffusion layer 92, a predetermined voltage is applied to the second diffusion layer 9 from the first diffusion layer 91 through the semiconductor substrate 93.
It is to judge whether or not the electric charge that reaches 2 or the electric current flows. When the charges are electrons, the potential of the floating gate 94 is kept low in the storage state, so that the potential applied to the semiconductor substrate 93 is also low, and the threshold voltage in the memory cell is high, so that no current flows. Conversely, in the erased state, the electric charge inside the floating gate 94 is almost zero, and the potential of the floating gate 94 is high enough to be slightly lower than the potential of the control gate 95. Therefore, the potential applied to the semiconductor substrate 93 increases, and the threshold voltage in the memory cell decreases, so that a current flows.

A method for calculating a write phenomenon in a device simulation apparatus will be described.

[0011] A predetermined voltage is applied to a predetermined terminal, and this is realized by transient analysis. It is assumed that the actual writing time is divided into minute time steps, and a certain amount of the terminal current or the writing current flows in the time step. In the initial state, the voltage of the floating gate is calculated, and the potential inside the memory cell, the electron density, the hole density, the terminal current, and the write current are calculated. Since the value obtained by multiplying the write current by the time step is the amount of charge accumulated in the floating gate during that time, the voltage of the floating gate in the next time step is calculated based on the value. Similarly, the terminal current and the write current are calculated, and similarly, the amount of charge accumulated in the floating gate during the calculation is calculated. This calculation is continuously performed until the time desired by the user is reached. Finally, a temporal change in the shift amount of the threshold voltage is obtained by dividing the time-varying charge amount by the capacitance of the second insulating film 97 measured in advance.

The calculation of the erase phenomenon in the device simulation apparatus is performed in the same way as the write. A predetermined voltage is applied to a predetermined terminal and realized by transient analysis. It is assumed that the actual erase time is divided into minute time steps, and a certain amount of the terminal current or the current for erasure flows in the minute time steps. Calculate the floating gate voltage in the initial state and calculate the potential inside the memory cell,
Calculate electron density, hole density, terminal current and erase current. The value obtained by multiplying the erase current by the time step is the amount of charge released from the floating gate during that time, and the voltage of the floating gate in the next time step is calculated based on the value.
Similarly, the terminal current and the erase current are calculated, and similarly, the amount of charge released from the floating gate during the calculation is calculated. This calculation is continuously performed until the time desired by the user is reached.
Finally, a temporal change in the shift amount of the threshold voltage is obtained by dividing the time-varying charge amount by the capacitance of the second insulating film 97 measured in advance.

In order to calculate the reading phenomenon in the device simulation apparatus, unlike in the case of writing and erasing, a predetermined voltage is applied to a predetermined terminal and realized by steady-state analysis. Calculate the voltage by fixing the charge of the floating gate,
The potential, electron density, hole density, and terminal current inside the memory cell are calculated.

The result of the device simulation is usually stored on a database as an electronic file, output to a printer as appropriate, or output as a graphic on a terminal, and the result is analyzed in a format desired by the user.

[0015]

The non-volatile memory structure shown in the conventional example is a two-dimensional structure. When the nonvolatile memory structure has a uniform shape in a direction perpendicular to the two-dimensional cross section, it is difficult to perform a two-dimensional simulation of the same. No problem with conventional equipment. However, as the first problem, there are many non-volatile memories having a three-dimensional structure. The structure of the non-volatile memory is
As shown in FIG. 9A, it seems that only the floating gate 94 is added to the structure of a normal MOS transistor. However, as can be seen from the structure of FIG. 9B showing a cross section taken along line AB of FIG. 9A, the surface where the floating gate 94 and the semiconductor substrate 93 are in contact with each other via the first insulating film 96. While the width is w1, the surface width at which the floating gate 94 and the control gate 95 are in contact with each other via the second insulating film 97 is w2. Not only the width of the floating gate and the control gate are different, but also the shape of the insulating film is not uniform in the horizontal direction. Even if the basic characteristics (threshold voltage, saturation current amount, etc.) are simulated, the analysis will be different from the actual one. These shapes 3
There is no problem in performing the analysis in the same dimension, but the amount of calculation required for the analysis is enormous, and the analysis by the computer takes a very long time. There is also a problem that the calculation load is large in terms of memory resources.

As a second problem, when a simulation is made to simulate the write characteristics of a nonvolatile memory having a three-dimensional shape, even if a simulation is performed on the original two-dimensional structure, an analysis different from the actual one is performed. . There is no problem in analyzing such a shape as it is in three dimensions, but the amount of calculation required for the analysis is enormous, and analysis with a computer requires a very long time. There is also a problem that the calculation load is large in terms of memory resources.

Further, as a third problem, when simulating the erasing characteristics of a nonvolatile memory having a three-dimensional shape, even if the original two-dimensional structure is simulated, the analysis differs from the actual one. . There is no problem in analyzing such a shape as it is in three dimensions, but the amount of calculation required for the analysis is enormous, and analysis with a computer requires a very long time. There is also a problem that the calculation load is large in terms of memory resources.

As a fourth problem, when trying to simulate the erasing characteristics of a non-volatile memory having a three-dimensional shape, a two-dimensional structure section for calculating a threshold voltage and a two-dimensional structure for performing an erasing calculation are used. When the two-dimensional structure cross section is different from the actual two-dimensional structure cross section, the analysis is different from the actual analysis. There is no problem in analyzing such a shape as it is in three dimensions, but the amount of calculation required for the analysis is enormous, and analysis with a computer requires a very long time. There is also a problem that the calculation load is large in terms of memory resources.

[0019]

In order to solve the above-mentioned problems, a first aspect of the present invention is a semiconductor device electrical characteristic evaluation apparatus which reads a two-dimensional structure which is a result of a process simulation and a two-dimensional structure of the process simulation. Means for capturing the actual shape in the direction perpendicular to the cross section and part 2
Means for performing a capacitance simulation on a two-dimensional cross section, and changing the thickness of a capacitive insulating film on a two-dimensional cross-sectional structure obtained from a process simulation based on the result of the capacitance simulation, and changing the two-dimensional cross-sectional structure obtained from the process simulation Means for receiving simulation conditions such as applied voltage for each electrode terminal of a semiconductor element having a changed two-dimensional cross-sectional structure, and information on the process simulation results such as impurity concentration and electrode position and terminal voltage, and the inside of the device. It has means for calculating the electrical characteristics, terminal current, etc. of the device, and means for analyzing the result of device simulation using a medium desired by the user, such as a terminal and a printer.

According to the present invention, even when the cross-sectional structure to be subjected to the two-dimensional simulation does not have a uniform structure in a direction perpendicular to the cross-section, the capacitance simulation is performed on the two-dimensional cross-section in the vertical direction, and the result is obtained. By performing a structural change such as a change in the thickness of the insulating film in the original two-dimensional cross section, accurate transistor characteristics as a memory cell can be calculated by a two-dimensional simulation.

According to a second aspect of the present invention, in addition to the configuration of the first aspect, the semiconductor device electrical characteristic evaluation apparatus includes means for executing a capacity simulation of a two-dimensional sectional structure changed based on a result of the capacity simulation and a transient. There are provided a means for executing a write calculation by analysis and a means for calculating a threshold voltage shift amount from a change in floating gate charge with time.

According to the present invention, even when the cross-sectional structure to be subjected to the two-dimensional simulation does not have a uniform structure in the direction perpendicular to the cross-section, the capacitance simulation is performed in the two-dimensional cross-section in the vertical direction, and the result is obtained. By performing a structural change such as a change in the thickness of the insulating film in the original two-dimensional cross section, a threshold voltage shift amount as an accurate writing characteristic can be calculated by a two-dimensional simulation.

A semiconductor device electrical characteristic evaluation apparatus according to a third aspect of the present invention is characterized in that, in addition to the configuration of the first aspect, means for executing a capacity simulation of a two-dimensional sectional structure changed based on a result of the capacity simulation and a transient state. There are provided means for performing an erasure calculation by analysis and means for calculating a threshold voltage shift amount from a change in floating gate charge with time.

According to the present invention, even when the cross-sectional structure to be subjected to the two-dimensional simulation does not have a uniform structure in a direction perpendicular to the cross-section, the capacitance simulation is performed on the two-dimensional cross-section in the vertical direction, and the result is obtained. By performing a structural change such as a change in the thickness of the insulating film in the original two-dimensional cross section, a threshold voltage shift amount as an accurate erase characteristic can be calculated by a two-dimensional simulation.

A semiconductor device electrical characteristic evaluation apparatus according to a fourth aspect of the present invention is different from the configuration according to the third aspect in that it is different from a means for executing a capacity simulation of a two-dimensional sectional structure changed based on a result of the capacity simulation. Means for performing an erasure calculation by transient analysis in the two-dimensional cross-sectional structure, means for transferring the voltage of the floating gate in the two two-dimensional cross-sectional structures, and a threshold due to a temporal change in floating gate charge in the modified two-dimensional cross-sectional structure. Means for calculating the value voltage shift amount is provided.

According to the present invention, when the sectional structure to be simulated two-dimensionally does not have a uniform structure in a direction perpendicular to the cross-section, and when the erasing operation is performed in the vertical-direction cross section, the vertical direction The capacitance simulation is performed in the two-dimensional cross section of the above, and the results are used to make structural changes such as a change in the thickness of the insulating film in the original two-dimensional cross section. The shift amount can be calculated.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a configuration diagram of a semiconductor device electrical characteristic evaluation apparatus according to the first embodiment. In FIG. 1, a process simulation result reading unit 11 reads information such as impurity density, material, and outer shape inside a semiconductor device, which is a two-dimensional process simulation result.
12 is a vertical section reader for reading information such as the material and outer shape in the direction perpendicular to the section of the two-dimensional process simulation result obtained in 11, and 13 is a vertical section for executing a capacity simulation on the vertical section obtained in 12 A cross-sectional capacitance simulation unit, 14 is a process simulation result structure changing unit that changes the external shape such as the insulating film thickness of 11 two-dimensional process simulation results using 13 results, 15 is a terminal voltage for device simulation, A simulation condition designating section for designating calculation conditions such as a voltage application time; 16, a device simulation section for calculating potential inside the semiconductor element, electron / hole density distribution, current-voltage characteristics, etc .;
Is a result output unit for outputting the result of 16 by means desired by the user.

With reference to FIG. 2, the semiconductor device electrical characteristic evaluation apparatus of the present embodiment configured as described above will be described.
The operation will be described.

First, the process simulation result reading section 11 reads a process simulation result for a two-dimensional section to be simulated originally, that is, the section shown in FIG. 9A shown in the conventional example. The result includes information such as impurity density information, material information, external shape and dimensions inside the semiconductor element (101).

Next, the vertical section reading unit 12 reads the shape of the section perpendicular to the two-dimensional section to be simulated, that is, the section shown in FIG. 9B shown in the conventional example. The information required here is material information including the outer shape, dimensions, and dielectric constant. Since the impurity density information of the semiconductor element portion is not always necessary, it may or may not be a two-dimensional process simulation result in the cross-sectional direction. If the result is not a two-dimensional process simulation, a cross-sectional photograph and its image information are required (10
2).

Next, the capacitance between the conductors is calculated from the information on the outer shape, dimensions, and dielectric constant of the two-dimensional cross-sectional shape acquired by the vertical cross-sectional capacitance simulation unit 13 in step 102. The capacitance between 93, 94, and 95 in FIG. 9B is calculated simultaneously (103).

Next, the process simulation result structure changing unit 14 performs a process of reflecting the capacitance ratio obtained in 103 on the two-dimensional cross-sectional shape of 101. That is, 101
Assuming that the thickness of the first insulating film 96 and the thickness of the second insulating film 97 in the two-dimensional process simulation result read in are represented by ta and tb, respectively, the capacitance between 93 and 94 calculated in 103 is represented by ca, the capacitance between 94 and 95 is cb, and the film thickness tb1 is given by tb1 = ta · ca / cb.
Is changed to a new film thickness and the structure is changed (104).

Next, the simulation condition specifying unit 15 receives information such as a terminal voltage specified by the user necessary for executing the device simulation (105).

Next, the device simulation unit 16
With respect to the changed process simulation result of 04, a desired voltage of 105 is applied to a predetermined electrode position to analyze the electric characteristics inside the device and the current-voltage characteristics as the transistor characteristics of the memory cell (106). What can be analyzed in the present embodiment is the electrical characteristics as the transistor characteristics of the memory cell. By applying a voltage from the outside to a region where an accurate voltage value is not known in a region that should originally be a floating gate, Only those that can be calculated by steady-state analysis, such as threshold voltage, saturation current, and breakdown voltage, are included. The write and erase characteristics cannot be analyzed for the structure whose shape has been changed in 104 because the capacitance between the floating gate and the control gate is unknown.

Finally, the result output unit 17 outputs the result of 106 in a form desired by the user (107). It is possible to output electrical characteristics inside the device element, such as potential and electron / hole density distribution, to a printer and a terminal. Similarly, terminal current-voltage characteristics can be output to a printer and a terminal. It is also possible to save the above results in a file format and output it as appropriate.

As described above, according to the present embodiment, when the shape is not uniform in the direction perpendicular to the two-dimensional cross section which is the original simulation cross section, for example, the width of the first insulating film and the second insulating film Are different from each other, and even when the thickness of the first insulating film and / or the thickness of the second insulating film are not uniform, the capacitance in the cross section perpendicular to the two-dimensional cross section which is the original simulation cross section Since the simulation is performed and the device simulation is performed by changing the thickness of the second insulating film in the original simulation section based on the capacitance ratio between the floating gate and the semiconductor substrate and the capacitance ratio between the control gate and the floating gate. In addition, it is possible to accurately calculate transistor characteristics that enable steady-state analysis of a memory cell.

Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.

FIG. 3 shows a configuration diagram of a semiconductor device electrical characteristic evaluation apparatus according to the second embodiment. In FIG. 3, reference numeral 31 denotes a process simulation result reading unit for reading information such as impurity density, material, and outer shape inside the semiconductor element, which is a two-dimensional process simulation result;
Reference numeral 32 denotes a vertical section reading unit that reads information such as a material and an outer shape in a direction perpendicular to the section obtained as a result of the two-dimensional process simulation obtained in 31. Reference numeral 33 denotes a vertical section that performs a capacity simulation on the vertical section obtained in 32. The direction cross-section capacitance simulation unit, 34 is a process simulation result structure changing unit that changes the external shape such as the insulating film thickness of the 31-dimensional process simulation result using the result of 33, and 35 is the process simulation result changed in 34. Structure change cross section capacity simulation section for executing capacity simulation on the structure, 36
Is a simulation condition designating section for designating calculation conditions such as terminal voltage and voltage application time for device simulation, and 37 is a microcontroller for transient characteristics such as potential inside the semiconductor element, electron / hole density distribution and current-voltage characteristics. A transient device simulation unit that calculates by dividing into time steps, 38 is a write amount calculation unit that calculates the amount of charge written from the semiconductor substrate to the floating gate at the end of each of 37 time steps, and 39 is a write time and a write operation time. A threshold shift amount calculator 40 for calculating the relationship between the threshold shift amounts as results is a result output unit 40 for outputting the result by means desired by the user.

With reference to FIG. 4, the semiconductor device electrical characteristic evaluation apparatus of the present embodiment configured as described above will be described.
The operation will be described.

First, the process simulation result reading section 31 reads a process simulation result for a two-dimensional section to be simulated originally, that is, the section shown in FIG. 9A shown in the conventional example. The result includes information such as impurity density information, material information, outer shape and dimensions inside the semiconductor element (301).

Next, the vertical section reading section 32 reads the shape of the section perpendicular to the two-dimensional section to be simulated, that is, the section shown in FIG. 9B shown in the conventional example. The information required here is material information including the outer shape, dimensions, and dielectric constant. Since the impurity density information of the semiconductor element portion is not always necessary, it may or may not be a two-dimensional process simulation result in the cross-sectional direction. If the result is not a two-dimensional process simulation, a cross-sectional photograph and its image information are required (30).
2).

Next, the capacitance between the conductors is calculated for the two-dimensional cross-sectional shape acquired in 302 by the vertical cross-sectional capacitance simulation unit 33 from the information on the outer shape, dimensions, and dielectric constant. The capacitance between each of 93, 94, and 95 in FIG. 9B is calculated simultaneously (303).

Next, the process simulation result structure changing unit 34 performs a process of reflecting the capacitance ratio obtained in 303 on the two-dimensional sectional shape of 301. That is, 301
Assuming that the thickness of the first insulating film 96 and the thickness of the second insulating film 97 in the two-dimensional process simulation result read in are represented by ta and tb, respectively, the capacitance between 93 and 94 calculated in 303 is ca, the capacitance between 94 and 95 is cb, and the film thickness tb1 is given by tb1 = ta · ca / cb.
Is changed to a new film thickness, and the structure is changed (304).

Next, the structure-changed cross-section capacitance simulation unit 35 performs a capacitance simulation on the structure changed in 304, and calculates the capacitance between the floating gate and the control gate (305).

Next, the simulation condition designating section 36 receives information such as a terminal voltage designated by the user required for executing the device simulation and a voltage application time required for the write operation (306).

Next, the transient device simulation section 37
Is applied to a predetermined electrode position for a desired period of time 306 with respect to the changed process simulation result of 304, and the electric characteristics inside the device and the current-voltage characteristics as the transistor characteristics of the memory cell are analyzed (30).
7). The analysis target in this embodiment is a write operation of a memory cell. At 306, the write time specified by the user is divided into minute time steps, and the potential, electron / hole density distribution, and terminal current are calculated assuming that the electrical characteristics inside the element are constant during the time steps. Do.

Next, the write amount calculator 38 calculates the amount of current injected from the semiconductor substrate into the floating gate electrode using the potential, electron / hole density, and the like obtained in 307. In an ordinary device simulator, it is often expressed in the form of a complicated function such as potential, electron / hole density, and the like. Since it is assumed in 307 that the current is constant within that time step, the amount of charge injected at that time step is the product of the current at that time and the time step width (308).

Next, the threshold shift amount calculator 39 calculates 308
When the amount of charge obtained in step (3) is divided by the capacitance between the floating gate and the control gate obtained in step (305), the shift amount of the threshold value of the memory cell at that time is obtained (309).

Next, the transient device simulation section 37
Then, the analysis at the time when a new time step is added to the previous time step is executed. At this time, the new time step width may be the same as the previous step width or may be changed. Normally, the analysis cannot be performed unless the analysis is performed with a very small step width in the initial stage of the analysis. Since the normal write operation attempts analysis up to about 1 msec, it is desirable to gradually increase the time step. However, as the time step increases, the charge amount calculated in 308 increases, but at the same time, the potential of the floating gate fluctuates greatly. Therefore, an error may occur if the time step is small. Therefore, instead of simply increasing the time step, it is necessary to take measures such as adjusting the time step so that the calculated charge amount does not exceed a certain value.

307 to 309 are iteratively calculated, and each time at 307, the current time from the beginning of writing and 306
Is compared with the user-specified writing time obtained in step (3), and if the current time is shorter than the user-specified time, 307 to 30
The iterative calculation of No. 9 is continued, and if larger, the iterative calculation is stopped and the process proceeds to the next process (310).

Finally, the result output unit 40 outputs the result of 309 in a form desired by the user (311). It is possible to output electrical characteristics inside the device element, such as potential and electron / hole density distribution, to a printer and a terminal. Similarly, terminal current-voltage characteristics can be output to a printer and a terminal. Similarly, the threshold voltage shift amount-time characteristic can be output to a printer and a terminal. It is also possible to save the above results in a file format and output it as appropriate.

As described above, according to the present embodiment, when the shape is not uniform in the direction perpendicular to the two-dimensional cross section which is the original simulation cross section, for example, the width of the first insulating film and the second insulating film Are different from each other, and even when the thickness of the first insulating film and / or the thickness of the second insulating film are not uniform, the capacitance in the cross section perpendicular to the two-dimensional cross section which is the original simulation cross section The simulation is performed, and the transient device simulation is performed by changing the thickness of the second insulating film in the original simulation section based on the capacitance ratio between the floating gate and the semiconductor substrate and the capacitance ratio between the control gate and the floating gate. Since the amount of charge written to the floating gate at each time step is divided by the changed capacitance between the control gate and the floating gate, the amount of shift of the threshold voltage can be accurately calculated. It is possible.

Hereinafter, a third embodiment of the present invention will be described with reference to the drawings.

FIG. 5 shows a configuration diagram of a semiconductor device electrical characteristic evaluation apparatus according to the third embodiment. In FIG. 5, reference numeral 51 denotes a process simulation result reading unit for reading information such as impurity density, material, and outer shape inside the semiconductor element, which is a two-dimensional process simulation result;
Reference numeral 52 denotes a vertical section reading unit that reads information such as a material and an outer shape in a direction perpendicular to the cross section of the two-dimensional process simulation result obtained in 51. Reference numeral 53 denotes a vertical section that performs a capacity simulation on the vertical section obtained in 52. A cross-section capacitance simulation section 54 is a process simulation result structure changing section that changes the external shape such as the insulating film thickness of the two-dimensional process simulation result 51 using the result 53, and 55 is a process simulation result changed in 54. Structural change cross-section capacitance simulation unit for performing capacitance simulation on the structure, 56
Is a simulation condition designating unit for designating calculation conditions such as terminal voltage and voltage application time for device simulation, and 57 is a device for minimizing transient characteristics such as potential inside the semiconductor element, electron / hole density distribution and current-voltage characteristics. A transient device simulation unit that divides and calculates the time step, and 58 is an erase charge amount calculation unit that calculates the amount of charge released from the floating gate to the semiconductor substrate at the end of each time step 57. 59 is an erase time and erase time. A threshold shift amount calculation unit 60 for calculating the relationship between the threshold shift amounts resulting from the operation, and a result output unit 60 for outputting the result by means desired by the user.

With reference to FIG. 6, the semiconductor device electrical characteristic evaluation apparatus of the present embodiment configured as described above will be described.
The operation will be described.

First, the process simulation result reading section 51 reads a process simulation result for a two-dimensional cross section to be simulated originally, that is, the cross section of FIG. 9A shown in the conventional example. The result includes information such as impurity density information inside the semiconductor element, material information, outer shape and dimensions, and the like (501).

Next, the vertical section reading section 52 reads the shape of the section perpendicular to the two-dimensional section to be simulated, that is, the section of FIG. 9B shown in the conventional example. The information required here is material information including the outer shape, dimensions, and dielectric constant. Since the impurity density information of the semiconductor element portion is not always necessary, it may or may not be a two-dimensional process simulation result in the cross-sectional direction. If the result is not a two-dimensional process simulation, a cross-sectional photograph and its image information are required (50).
2).

Next, the capacitance between the conductors of the two-dimensional cross-sectional shape acquired by the vertical cross-sectional capacitance simulation unit 53 is calculated from the information on the outer shape, dimensions, and dielectric constant of the two-dimensional cross-sectional shape. The capacitance between 93, 94, and 95 in FIG. 9B is calculated simultaneously (503).

Next, the process simulation result structure changing unit 54 performs a process for reflecting the capacitance ratio obtained in 503 on the two-dimensional sectional shape of 501. That is, 501
Assuming that the thickness of the first insulating film 96 and the thickness of the second insulating film 97 of the two-dimensional process simulation result read in at step t are tb and that the capacitance between 93 and 94 calculated at 503 is ca, the capacitance between 94 and 95 is cb, and the film thickness tb1 is given by tb1 = ta · ca / cb.
Is changed to a new film thickness, and the structure is changed (504).

Next, the structure-changed cross-section capacitance simulation unit 55 performs a capacitance simulation on the structure changed in 504, and calculates the capacitance between the floating gate and the control gate (505).

Next, the simulation condition specifying unit 56 receives information such as a terminal voltage specified by the user necessary for executing the device simulation and a voltage application time required for the erase operation (506).

Next, the transient device simulation section 57
Are applied to a predetermined electrode position for a desired time 506 with respect to the changed process simulation result of 504, and the electric characteristics inside the device and the current-voltage characteristics as the transistor characteristics of the memory cell are analyzed (50).
7). The analysis target in the present embodiment is the erase operation of the memory cell. At 506, the erasing time specified by the user is divided into minute time steps, and the potential, electron / hole density distribution, and terminal current are calculated assuming that the electrical characteristics inside the device are constant during the time steps. Do.

Next, the erased charge amount calculator 58 calculates the amount of current emitted from the floating gate electrode to the control gate or the semiconductor substrate using the potential, electron / hole density, and the like obtained in 507. In an ordinary device simulator, it is often expressed in the form of a complicated function such as potential, electron / hole density, and the like. Since it is assumed in 507 that the current is constant within that time step, the amount of charge released in that time step is the product of the current at that time and the time step width (508). The calculation of the erasing operation applicable in the present embodiment is a case where erasing is performed in the two-dimensional cross section 504. In the example of FIG. 9A, the charge is transferred from the floating gate 94 to the control gate 95 or the first diffusion layer 9.
1, the second diffusion layer 92, the semiconductor substrate 93 and the like. If the erase gate 99 shown in FIG. 9C is present, this embodiment is out of scope.

Next, the threshold shift amount calculating section 59 calculates
When the amount of charge obtained in step (5) is divided by the capacitance between the floating gate and the control gate obtained in step 505, the threshold shift amount of the memory cell at that time is obtained (509).

Next, the transient device simulation section 57
Then, the analysis at the time when a new time step is added to the previous time step is executed. At this time, the new time step width may be the same as the previous step width or may be changed. Normally, the analysis cannot be performed unless the analysis is performed with a very small step width in the initial stage of the analysis. Since the normal erase operation attempts analysis up to about 10 msec, it is desirable to gradually increase the time step. However, as the time step increases, the charge amount calculated in 508 increases, but at the same time, the potential of the floating gate fluctuates greatly. Therefore, an error may occur if the time step is small. Therefore, instead of simply increasing the time step, it is necessary to take measures such as adjusting the time step so that the calculated charge amount does not exceed a certain value.

507 to 509 are iteratively calculated, and each time, at 507, the current time from the beginning of erasing is compared with the user-specified erasing time obtained at 506. If the current time is smaller than the user-specified time, 507 To 509, and if larger, stop the iterative calculation and proceed to the next process (510).

Finally, the result output unit 60 outputs the result of 509 as desired by the user (511). It is possible to output electrical characteristics inside the device element, such as potential and electron / hole density distribution, to a printer and a terminal. Similarly, terminal current-voltage characteristics can be output to a printer and a terminal. Similarly, the threshold voltage shift amount-time characteristic can be output to a printer and a terminal. It is also possible to save the above results in a file format and output it as appropriate.

As described above, according to the present embodiment, when the shape is not uniform in the direction perpendicular to the two-dimensional cross section which is the original simulation cross section, for example, the width of the first insulating film and the second insulating film Are different from each other, and even when the thickness of the first insulating film and / or the thickness of the second insulating film are not uniform, the capacitance in the cross section perpendicular to the two-dimensional cross section which is the original simulation cross section The simulation is performed, and the transient device simulation is performed by changing the thickness of the second insulating film in the original simulation section based on the capacitance ratio between the floating gate and the semiconductor substrate and the capacitance ratio between the control gate and the floating gate. Calculates the amount of threshold voltage shift accurately because the amount of charge erased to the floating gate at each time step is divided by the capacitance between the changed control gate and floating gate Bets are possible.

Hereinafter, a fourth embodiment of the present invention will be described with reference to the drawings.

FIG. 7 shows a configuration diagram of a semiconductor device electrical characteristic evaluation apparatus according to the fourth embodiment. In FIG. 7, reference numeral 71 denotes a process simulation result reading unit for reading information such as impurity density, material, and outer shape inside the semiconductor element, which is a two-dimensional process simulation result;
Reference numeral 72 denotes a vertical section process simulation result reading unit for reading a process simulation result of a section perpendicular to the section of the two-dimensional process simulation result obtained at 71, and 73 executes a capacity simulation on the vertical section shape obtained at 72. The vertical section capacitance simulation section 74 uses the result of 73 to calculate
A process simulation result structure changing unit for changing an external shape such as an insulating film thickness of a three-dimensional process simulation result; 75, a structure changing sectional capacity simulation unit for executing a capacity simulation on the process simulation structure changed in 74; Is a simulation condition specification part that specifies calculation conditions such as terminal voltage and voltage application time for device simulation,
77 is a vertical transient device simulation unit for calculating transient characteristics such as potential inside the semiconductor element, electron / hole density distribution and current-voltage characteristics by dividing them into minute time steps with respect to the two-dimensional process simulation results obtained in 72; Reference numeral 78 denotes an erased charge calculator for calculating the amount of charge released from the floating gate to the semiconductor substrate at the end of each of the time steps of 77. 79 denotes a two-dimensional cross section obtained by calculating the erased charge calculated by 78 at 71. , A threshold shift amount calculation unit for calculating the relationship between the erase time and the threshold shift amount as a result of the erase operation, and 81 a result obtained by a means desired by the user. Is a result output unit that outputs

With reference to FIG. 8, the semiconductor device electrical characteristic evaluation apparatus of the present embodiment configured as described above will be described.
The operation will be described.

First, the process simulation result reading section 71 reads a process simulation result for a two-dimensional cross section which should be simulated originally, that is, the cross section of FIG. 9A shown in the conventional example. The result includes information such as impurity density information inside the semiconductor element, material information, outer shape and dimensions, and the like (701).

Next, a section in a direction perpendicular to the two-dimensional section to be simulated by the vertical section process simulation result reading section 72, that is, FIG.
The process simulation result is read for the cross section of FIG. The result includes information such as impurity density information, material information, outer shape and dimensions inside the semiconductor element (702).

Next, the vertical section capacitance simulation section 73 calculates the capacitance between the conductors from the information on the outer shape, dimensions, and dielectric constant of the two-dimensional section obtained at 702. The capacitance between 93, 94, and 95 in FIG. 9B is calculated simultaneously (703).

Next, the process simulation result structure changing unit 74 performs a process for reflecting the capacitance ratio obtained in 703 on the two-dimensional sectional shape of 701. That is, 701
Assuming that the thickness of the first insulating film 96 and the thickness of the second insulating film 97 in the two-dimensional process simulation result read in at step t are tb and that the capacitance between 93 and 94 calculated at 703 is ca, the capacitance between 94 and 95 is cb, and the film thickness tb1 is given by tb1 = ta · ca / cb.
Is changed to a new film thickness, and the structure is changed (704).

Next, the structure-changed cross-section capacitance simulation section 75 performs a capacitance simulation on the structure changed in 704, and calculates the capacitance between the floating gate and the control gate (705).

Next, the simulation condition designating section 76 receives information such as a terminal voltage designated by the user required for executing the device simulation and a voltage application time required for the erase operation (706).

Next, the vertical transient device simulation unit 77 applies the desired time 706 to the predetermined electrode position with respect to the changed process simulation result 702 at the predetermined electrode position.
Analyze the electrical characteristics inside the device by applying voltage (7
07). The analysis target in the present embodiment is the erase operation of the memory cell. At 706, the erasing time specified by the user is divided into minute time steps, and the potential, electron / hole density distribution, and terminal current are calculated assuming that the electrical characteristics inside the device are constant during the time steps. Do.

Next, the erased charge amount calculator 78 uses the potential, electron and hole densities, etc. obtained in 707 to discharge the current amount from the floating gate electrode to other regions on the cross section of the erased gate 702 such as the erased gate. Is calculated. In an ordinary device simulator, it is often expressed in the form of a complicated function such as potential, electron / hole density, and the like. Since it is assumed in 707 that the current is constant within that time step, the amount of charge released in that time step is the product of the current at that time and the time step width (708). The calculation of the erasing operation applicable in the present embodiment is a case where erasing is performed in a two-dimensional section 702. FIG. 9C shows an example in which charges are discharged from the floating gate 94 to the erase gate 99 and the like. This embodiment is not applicable to the case where charges are discharged to the control gate 95, the first diffusion layer 91, the second diffusion layer 92, the semiconductor substrate 93, and the like in FIG. 9A.

Next, the charge amount conversion unit 79 converts the charge amount calculated at 78 into the charge amount in the section 704 (70).
9). Since the charge amount calculated at 78 is the value of the control gate in the two-dimensional section 702, the value cannot be given to the control gate in the two-dimensional section 704 as it is. Therefore, in the section of 702, all terminals are set to 0 volt while the charge amount calculated at 78 is kept inside the floating gate. The voltage value of the floating gate at that time is stored. Next, in the section 704, the voltage value is applied to the floating gate, and the charge amount at that time is obtained. The charge amount conversion is performed as described above.

Next, the threshold shift amount calculating section 80 calculates
Dividing the amount of charge obtained in (1) by the capacitance between the floating gate and the control gate obtained in 705 results in a threshold shift amount of the memory cell at that time (710).

Next, returning to the vertical transient device simulation section 77, the analysis at the time when a new time step is added to the previous time step is executed. At this time, the new time step width may be the same as the previous step width or may be changed. Normally, in the early stage of analysis, calculation becomes impossible unless analysis is performed with a very small step width.
The analysis is started from about ec. Normal erase operation is 10ms
Since the analysis is attempted to about ec, it is desirable to gradually increase the time step. However, as the time step increases, the charge amount calculated in 709 increases,
At the same time, since the potential of the floating gate greatly changes, an error may occur when the time step is small. Therefore, instead of simply increasing the time step, it is necessary to take measures such as adjusting the time step so that the calculated charge amount does not exceed a certain value.

710 is repeatedly calculated from 707, and each time, at 707, the current time from the beginning of erasing is compared with the user-specified erasing time obtained at 706. If the current time is smaller than the user-specified time, 707 710 is repeated, and if larger, the iterative calculation is stopped and the process proceeds to the next process (711).

Finally, the result output unit 81 outputs the result of 710 in a form desired by the user (712). It is possible to output electrical characteristics inside the device element, such as potential and electron / hole density distribution, to a printer and a terminal. Similarly, terminal current-voltage characteristics can be output to a printer and a terminal. Similarly, the threshold voltage shift amount-time characteristic can be output to a printer and a terminal. It is also possible to save the above results in a file format and output it as appropriate.

As described above, according to the present embodiment, when the shape is not uniform in the direction perpendicular to the two-dimensional cross section which is the original simulation cross section, for example, the width of the first insulating film and the second insulating film Are different from each other, and even when the thickness of the first insulating film and / or the thickness of the second insulating film are not uniform, the capacitance in the cross section perpendicular to the two-dimensional cross section which is the original simulation cross section A simulation is performed, and the thickness of the second insulating film is changed in the original simulation section based on the capacitance ratio between the floating gate and the semiconductor substrate and the capacitance ratio between the control gate and the floating gate, and the simulation is performed. A transient device simulation is performed on a vertical two-dimensional cross section to determine the amount of charge erased from the floating gate at each time step. In terms of charge amount, it is possible to perform calculation of the threshold voltage shift amount accurately because dividing the capacity between the charge amount changed control gate and the floating gate.

[0087]

According to the present invention, means for reading information such as impurity density, material and outer shape inside a semiconductor element, which is a result of a two-dimensional process simulation, and information such as material and outer shape in a direction perpendicular to a cross section of the two-dimensional process simulation result. , Means for performing a capacitance simulation on a vertical cross-sectional shape, means for changing an external shape such as an insulating film thickness of a two-dimensional process simulation result from a result of the capacitance simulation, and a terminal voltage for device simulation. Means for specifying calculation conditions such as voltage and time of voltage application, means for device simulation to calculate the potential inside the semiconductor element, electron / hole density distribution, current-voltage characteristics, etc. 2D simulation by having output means Even when the shape is not uniform in the vertical cross section, not in the original cross section, the capacitance simulation is performed in the vertical cross section, and the result is converted into the thickness of the insulating film in the original two-dimensional cross section. Since the three-dimensional shape can be reflected on the original two-dimensional cross section, accurate electrical characteristics can be analyzed, and a semiconductor element electrical characteristics evaluation device that can set optimal manufacturing conditions without repeating trial production is realized. You can do it.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a semiconductor device electrical characteristic evaluation apparatus according to a first embodiment of the present invention.

FIG. 2 is a flowchart of a semiconductor device electrical characteristic evaluation apparatus according to the first embodiment of the present invention.

FIG. 3 is a block diagram showing a schematic configuration of a semiconductor device electrical characteristic evaluation apparatus according to a second embodiment of the present invention.

FIG. 4 is a flowchart of a semiconductor device electrical characteristic evaluation apparatus according to a second embodiment of the present invention.

FIG. 5 is a block diagram showing a schematic configuration of a semiconductor device electrical characteristic evaluation apparatus according to a third embodiment of the present invention.

FIG. 6 is a flowchart of a semiconductor device electrical characteristic evaluation apparatus according to a third embodiment of the present invention.

FIG. 7 is a block diagram showing a schematic configuration of a semiconductor device electrical characteristic evaluation apparatus according to a fourth embodiment of the present invention.

FIG. 8 is a flowchart of a semiconductor device electrical characteristic evaluation apparatus according to a fourth embodiment of the present invention.

FIG. 9 is a schematic diagram showing a two-dimensional cross-sectional structure of a nonvolatile memory;

FIG. 10 is a schematic view showing a grating for discretization in a device simulation.

[Explanation of symbols]

REFERENCE SIGNS LIST 11 process simulation result reading section 12 vertical section reading section 13 vertical section capacity simulation section 14 process simulation result structure changing section 15 simulation condition specifying section 16 device simulation section 17 result output section 31 process simulation result reading section 32 vertical section reading Unit 33 vertical cross-section capacitance simulation unit 34 process simulation result structure change unit 35 structure change cross-section capacitance simulation unit 36 simulation condition specification unit 37 transient device simulation unit 38 write amount calculation unit 39 threshold shift amount calculation unit 40 result output unit 51 Process simulation result reading section 52 Vertical section reading section 53 Vertical section capacity simulation section 54 Process simulation Result structure change unit 55 structure change cross section capacity simulation unit 56 simulation condition specification unit 57 transient device simulation unit 58 erase charge amount calculation unit 59 threshold shift amount calculation unit 60 result output unit 71 process simulation result read unit 72 vertical section Process simulation result reading unit 73 Vertical cross section capacitance simulation unit 74 Process simulation result structure change unit 75 Structure change cross section capacitance simulation unit 76 Simulation condition specification unit 77 Vertical transient device simulation unit 78 Erased charge amount calculation unit 79 Charge amount conversion unit 80 Threshold shift amount calculation section 81 Result output section 91 First diffusion layer 92 Second diffusion layer 93 Semiconductor substrate 94 Floating gate 95 Control gate 96 First insulating film 97 Second insulating layer Edge film 98 Device isolation film 99 Erase gate

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/00 F term (Reference) 5B046 AA08 JA04 5F001 AA01 AB08 AC02 AC30 AE02 AE03 AE08 AG17 5F083 EP02 EP23 ER04 ER14 ER15 ER16 ER17 GA30 ZA30

Claims (4)

[Claims] A means for reading a result of a two-dimensional semiconductor process simulation; a means for reading an element shape having a non-uniform shape in a direction perpendicular to the two-dimensional section; and a means for performing a two-dimensional capacitance simulation on the vertical section. Means for changing the structure of the original process simulation result from the capacity simulation result, means for receiving the input of the electric characteristics and measurement conditions desired by the user, means for calculating the electric characteristics by two-dimensional device simulation,
An apparatus for evaluating electrical characteristics of a semiconductor device, comprising: means for outputting a result on a medium designated by a user. 2. A means for reading a two-dimensional semiconductor process simulation result in an analysis of a write operation for accumulating charges in a floating gate of a nonvolatile memory, and an element shape having a non-uniform shape in a direction perpendicular to the two-dimensional cross section. Reading means, means for performing a two-dimensional capacitance simulation on a vertical cross section, means for changing the structure of the original process simulation result from the capacitance simulation result, and means for performing a two-dimensional capacitance simulation on the changed structure Means for receiving input of electrical characteristics and measurement conditions desired by the user; means for calculating a write operation by two-dimensional transient device simulation; means for calculating a write charge amount; and threshold voltage as a result of the write operation Means for calculating the shift amount, and means for outputting the result on a user-specified medium. An apparatus for evaluating electrical characteristics of a semiconductor device, comprising a step. 3. A means for reading a two-dimensional semiconductor process simulation result in an analysis of an erasing operation for discharging charges from a floating gate of a nonvolatile memory, and an element shape having a non-uniform shape in a direction perpendicular to the two-dimensional cross section. Means for reading, means for performing a two-dimensional capacitance simulation on a vertical cross section, means for changing the structure of the original process simulation result from the capacitance simulation result,
A means for performing a two-dimensional capacitance simulation on the changed structure; a means for receiving input of electrical characteristics and measurement conditions desired by a user; a means for calculating an erasing operation by means of a two-dimensional transient device simulation; , A means for calculating a threshold voltage shift amount as a result of an erase operation, and a means for outputting a result on a medium designated by a user. 4. A means for reading a two-dimensional semiconductor process simulation result, a means for reading a process simulation result in a direction perpendicular to a two-dimensional cross section, and a method for analyzing an erase operation for discharging charges from a floating gate of a nonvolatile memory. A means for performing a two-dimensional capacitance simulation on the cross section, a means for changing the structure of the original process simulation result from the capacitance simulation result, a means for performing a two-dimensional capacitance simulation on the changed structure, and a user desire. A means for receiving input of electrical characteristics and measurement conditions; a means for calculating an erase operation by a two-dimensional transient device simulation with respect to a vertical section; a means for calculating an erased charge; Means for converting to a value in a two-dimensional cross section of A device for evaluating electrical characteristics of a semiconductor device, comprising: means for calculating a low voltage shift amount; and means for outputting a result on a medium designated by a user.