JP2001028189A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize constitution of a semiconductor memory having a word driver which an suppress a through current caused at the time of activating a word line. SOLUTION: This word driver 100 comprises a level conversion circuit 120 which drives a word line WL with amplitude of word line boosting voltage Vpp responding to a row address decoding signal XD having an amplitude of power source voltage Vcc and which has the constitution of a cross amplifier having a latch function, a cut off transistor QP30 which is provided for cutting off a through current caused in the level conversion circuit 120, and a cut off signal generating circuit 110 which generates a cut off signal CTF given to the gate of the transistor QP30. The cut off signal generating circuit 110 sets the voltage level of the cut off signal CTF to Vpp until the voltage level of a word line reaches a Vpp level at the time of activating a word line.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device capable of reducing power consumption.

[0002]

2. Description of the Related Art A random access memory (RAM) which is a semiconductor device capable of rewriting, holding and reading data at any time.
s Memory) is widely used. Among them, a dynamic RAM (Dynamic RAM, DRAM) is being developed as a memory suitable for increasing the capacity because of a simple configuration of a memory cell as a storage element.

FIG. 6 is a circuit diagram showing a configuration of a memory cell of a general dynamic RAM. Referring to FIG.
The memory cell MC includes a MOS transistor QN serving as a switch, and a capacitor C for storing information charges. The memory cell MC stores whether or not the capacitor C has a charge, that is, whether the terminal voltage of the capacitor is high or low, in correspondence with the binary information “1” and “0”, respectively. In general, an N-type MOS transistor is used as the transistor QN. Memory cell MC
When data is read and written between data line DL and data line DL, word line WL connected to the gate of transistor QN is selected by applying a high voltage to set capacitor C and data line DL. And connect.

The transistor QN in the memory cell MC has N
When a type MOS transistor is used, in order to cope with a voltage drop corresponding to a threshold voltage (Vth) generated in the transistor QN, the word line WL is raised from the power supply voltage Vcc level as a high voltage level. It is necessary to apply a voltage. In particular, in the memory cell MC,
In order to write H-level data (Vcc level), the gate voltage of transistor QN needs to be set to a voltage level higher than Vcc + Vth.

For this reason, the dynamic RAM uses Vcc
A voltage generating circuit for generating a word line boosted voltage Vpp set to a voltage higher than + Vth, and a word driver for supplying the word line boosted voltage Vpp to a corresponding word line in response to an address signal are provided.

FIG. 7 shows a conventional word driver 50.
FIG. 3 is a circuit diagram illustrating a configuration of a zero. Word driver 500
Is provided for each word line, and activates by supplying word line boosted voltage Vpp to word line WL in response to a corresponding row address decode signal XD. Row address decode signal XD operates at power supply voltage Vcc level,
Vcc in the active state (H level) and Vcc in the inactive state (L
Level) is a signal having a voltage level of GND (ground voltage).

Address decode circuit 500 includes inverters IV51 and IV52 for transmitting row address decode signal XD to node Na, and inverter IV5 for inverting the voltage level of node Na and transmitting the same to node Nb.
3 is provided. Inverters IV51 to IV53 are driven by power supply voltage Vcc and ground voltage GND.
Accordingly, the signals transmitted to nodes Na and Nb also become signals having a voltage amplitude from GND to Vcc.

Word driver 500 further includes power supply voltage Vcc according to the voltage levels of nodes Na and Nb.
And a level conversion circuit 510 for supplying the word line boosted voltage Vpp, which is the boosted voltage of the word line WL, to the word line WL.

Level conversion circuit 510 has a configuration of a cross amplifier having a latch function, and is provided with word line boosted voltage Vp.
a P-type MOS transistor QP50 connected between power supply line 593 transmitting p and node Nc;
N-type MOS transistor QN50 connected between power supply line 593 and node Nd, and N-type MOS transistor QP51 connected between power supply line 593 and node Nd, and connected between node Nd and ground line 591 N-type MOS
And a transistor QN51. Transistor QN50
Is connected to node Na, and transistor QP5
The gate of 0 is connected to node Nd. Transistor QN51 has a gate connected to node Nb, and transistor QP51 has a gate connected to node Nc. Node Nd is connected to word line WL, and word line boosted voltage Vpp is supplied to word line WL via node Nd.
The word line WL has a parasitic capacitance Cp.

FIG. 8 is a timing chart for explaining the operation of the word driver 500. Referring to FIG. 8, at time t1, row address decode signal XD for activating a corresponding word line is activated, and rises from L level (GND) to H level (Vcc). In response, at time t2, row address decode signal XD is transmitted to Na and node Nb, and the voltage level of each node changes to H level (Vcc) and L level (GND), respectively. When the voltage level of node Na changes to H level, transistor Q
N50 is turned on, a current path is formed between node Nc and ground wiring 591, and the voltage level of node Nc starts to decrease toward L level (GND). As the voltage level of node Nc decreases, transistor QP51 turns on, and connects node Nd and power supply wiring 593. on the other hand,
Since the voltage level of node Nb attains the L level (GND), node Nd and ground line 591 are disconnected from each other. Therefore, the voltage level of node Nd, that is, the voltage level of word line WL starts rising from time t2, Eventually, it reaches the level of word line boosted voltage Vpp. Thereby, the word line WL corresponding to the row address decode signal XD is selected and activated.

[0011]

However, referring to FIG. 6, when transistor QN50 is turned on at time t2 in response to activation of row address decode signal XD, the potential of node Nc corresponding to its drain is reduced. Although the voltage level starts to decrease from the H level (Vpp) to the L level (GND), the word line WL connected to the gate of the transistor QP50 is not activated and is in the non-selected state (L level). Meanwhile, the transistor QP50 remains on.

Therefore, at time t2, both transistors QP50 and QN50 are turned on, and a through current i occurs. After the transistor QP51 is turned on when the voltage level of the node Nc sufficiently approaches the level of the ground voltage GND, the voltage level of the word line WL rises sufficiently to the level of Vpp.
It continues to flow during a period ΔT until time t3 when 50 turns off.

The cause of the through current i is that the word line WL
Transistor QP51 due to the parasitic capacitance CP
Is turned on, the time ΔT from when the word line WL reaches the word line boosted voltage Vpp is determined by the nodes Nc and Nc.
This is because it is longer than the time required for charging and discharging the charge in d.

As described above, when the word line is activated, the through current i flows through the word driver, thereby increasing power consumption.

On the other hand, since the parasitic capacitance of the word line WL is greatly affected by the wiring length, there is a certain limit in suppressing the parasitic capacitance while the memory capacity is increasing. In order to shorten the rise time ΔT of the word line, it is conceivable to improve the charge supply capability of a Vpp generation circuit that generates the word line boosted voltage Vpp, but this also has a limit.

In a dynamic memory, it is necessary to perform a refresh operation at a constant cycle in order to retain charge information stored in a memory cell. In the refresh operation, a plurality of word lines are simultaneously activated. Be transformed into In particular, when the number of word lines to be subjected to one refresh operation is increased in order to shorten the refresh operation time and increase the operation speed, an increase in power consumption due to the presence of the through current as described above. Is a big problem. Further, even when the operating frequency of the dynamic memory is increased, the number of times the word line is activated within a unit time increases, which causes a problem that power consumption is further adversely affected.

An object of the present invention is to solve such a problem. An object of the present invention is to provide a configuration of a semiconductor memory device having a word driver capable of reducing a through current generated when a word line is activated. It is to provide.

[0018]

According to a first aspect of the present invention, a semiconductor memory device includes a plurality of memory cells arranged in a matrix, a plurality of word lines for selecting a row of memory cells, and a selection of a word line. A first power supply line for supplying a first voltage corresponding to the state, a second power supply line for supplying a second voltage corresponding to a non-selected state of the word line, and a plurality of word lines are arranged for each of the plurality of word lines. A third voltage lower than the first voltage in the active state;
A word line drive circuit that drives a corresponding one of the plurality of word lines to a selected state in response to a control signal set to a voltage of the word line, and the word line drive circuit responds to the control signal. A first charge supply circuit for transferring charges between an internal node and a second power supply line, and a first power supply line and a corresponding word line according to the voltage level of the internal node. And a third power supply circuit for transmitting and receiving charges between a corresponding word line and a second power supply line in response to an inverted signal of the control signal. A charge supply circuit, a fourth charge supply circuit for transferring charges between a first power supply line and an internal node according to a voltage level of a corresponding word line, and a first power supply line and an internal Electrically connected in series with the fourth charge supply circuit , And a current cut-off switch circuit for a predetermined period of time off in response to a control signal.

According to a second aspect of the present invention, in the semiconductor memory device according to the first aspect, the voltage level of the word line is changed to the first level after the control signal instructs the selection of the word line for a predetermined period. It is longer than the time required to reach the voltage.

According to a third aspect of the present invention, there is provided the semiconductor memory device according to the first aspect, wherein the second and third charge supply circuits have charge supply capacities of the first and fourth charge supply circuits. It is larger than the charge supply capacity.

According to a fourth aspect of the present invention, there is provided the semiconductor memory device according to the first aspect, wherein the word line drive circuit controls on / off of the current cutoff supply circuit in response to a control signal. The current cutoff control circuit further generates a signal, and the current cutoff control circuit sets the voltage level of the current cutoff control signal to one of a boosted voltage higher than the third voltage and the second voltage.

A semiconductor memory device according to a fifth aspect is the semiconductor memory device according to the fourth aspect, wherein the boosted voltage is set according to the first voltage.

A semiconductor memory device according to a sixth aspect of the present invention is the semiconductor memory device according to the fourth aspect, wherein the current cutoff control circuit is activated for a predetermined period in response to activation of the control signal. One-shot pulse signal generating circuit for outputting the current to the first node, a boost capacitor electrically coupled between the second node and the first node for outputting the current cutoff control signal, and a one-shot pulse signal In response to the active state, the second power supply line and the second node are cut off, and the second power supply line and the second node are connected in response to the inactive state of the one-shot pulse signal. And a capacitance value of the boosting capacitor is larger than a parasitic capacitance existing at the second node.

A semiconductor memory device according to a seventh aspect is the semiconductor memory device according to the fourth aspect, wherein the first charge supply circuit receives the control signal at the gate, and connects the internal node to the second power supply line. A first MOS transistor of a first conductivity type electrically coupled between the first and second charge supply circuits, a second charge supply circuit has a gate connected to an internal node, and has a corresponding word line and a first word line. A second MOS transistor of a second conductivity type electrically coupled to the power supply line, the third charge supply circuit receiving an inverted signal of the control signal at its gate, and A third MOS transistor of the first conductivity type electrically coupled to the second power supply line;
Has a gate connected to a corresponding word line, and has a second conductivity type fourth MOS transistor electrically coupled between the first power supply line and an internal node. , The current cutoff switch circuit receives the current cutoff control signal at the gate, and supplies a current between the first power supply wiring and the internal node.
A fifth MOS transistor of a second conductivity type electrically coupled in series with the fourth MOS transistor, wherein a ratio of a channel width to a channel length in the second and third MOS transistors is equal to the first and third MOS transistors; 4 is larger than the ratio in the MOS transistor.

According to the semiconductor memory device of the present invention, a plurality of memory cells arranged in a matrix, a plurality of word lines for selecting a row of the memory cells, and a first state corresponding to a selected state of the word line. And a second power supply for supplying a second voltage corresponding to a non-selected state of the word line.
A power line, and a word line drive circuit arranged for each of the plurality of word lines, for driving a corresponding one of the plurality of word lines to a selected state in accordance with a control signal; Is a first charge supply circuit for transmitting and receiving charges between a first internal node and a second power supply line in response to a control signal, the charge supply node being connected to a corresponding word line. A second charge supply circuit for transmitting and receiving charges between the second internal node and the first power supply wiring according to a voltage level of the first internal node; In response, a third charge supply circuit for transferring charges between the second internal node and the second power supply line, and a first internal circuit according to a voltage level of the second internal node. A fourth power supply for transferring electric charge between the node and the first power supply wiring. A supply circuit, according to the voltage level of the first internal node, as well as transfer charge between the charge supply node and the first power supply wiring, in response to a control signal,
A fifth charge supply circuit for transferring charges between the charge supply node and the second power supply wiring, wherein the fifth charge supply circuit has a charge supply capability of the first to fourth charge supply circuits Is greater than the charge supply capacity of

A semiconductor memory device according to a ninth aspect is the semiconductor memory device according to the eighth aspect, wherein the first charge supply circuit has a gate for receiving a control signal, and has a first internal node and a second internal node. A first MOS transistor of a first conductivity type electrically coupled to a power supply line of the first type, the second charge supply circuit has a gate connected to a first internal node,
A second MOS transistor of the second conductivity type electrically coupled between the second internal node and the first power supply line, wherein the third charge supply circuit receives an inverted signal of the control signal A third MOS transistor of a first conductivity type having a gate and electrically coupled between the second internal node and the second power supply line; And a fourth MOS transistor of a second conductivity type electrically coupled between the first internal node and the first power supply wiring, A charge supply circuit having a gate connected to the first internal node, a second conductivity type fifth MOS transistor electrically coupled between the charge supply node and the first power supply line; A gate for receiving an inversion signal of the control signal; And a sixth MOS transistor of the first conductivity type electrically coupled to.

According to a tenth aspect of the present invention, in the semiconductor memory device according to the ninth aspect, the ratio of the channel width to the channel length in the fifth and sixth MOS transistors is set to be equal to the first to fourth MOS transistors. It is larger than the ratio in the transistor.

[0028]

Embodiments of the present invention will be described below in detail with reference to the drawings. The same reference numerals in the drawings indicate the same or corresponding parts.

[First Embodiment] FIG. 1 is a schematic block diagram showing an overall configuration of a semiconductor memory device 1000 according to a first embodiment of the present invention.

Referring to FIG. 1, semiconductor memory device 1000
Is an address input terminal 12 for receiving address signals A0 to Ai (i: natural number) and a row address strobe signal /
A control signal input terminal 14 for receiving control signals such as RAS, column address strobe signal / CAS and write enable / WE, a data input / output terminal 16 for transmitting / receiving input / output data, and a power supply terminal 18 for receiving a ground voltage and an external power supply voltage And

Semiconductor memory device 1000 further includes a control circuit 20 receiving a control signal from control signal input terminal 14 and generating an internal control signal for controlling the operation inside semiconductor memory device 1000, and a control circuit 20 arranged in a matrix. And a memory cell array 50 having a plurality of memory cells. Memory cell array 50 includes a word line WL provided for each row of memory cells and a bit line BL provided for each column of memory cells. A memory cell MC is arranged at an intersection between the word line WL and the bit line BL.

Semiconductor memory device 1000 further includes an address buffer 30 receiving an address signal, a row decoder 40 for generating a row address decode signal XD for selectively activating a row of memory cells, and a column of memory cells. Column address decode signal YD for selectively activating
And a column decoder 45 that generates Address buffer 30 transmits the signal levels of address signals A0 to Ai received from the address signal input terminal to row decoder 40 and column decoder 45. Word line WL is selectively activated by word line drive circuit 95 in response to a row address decode signal XD generated by a row decoder.

In response to activation of word line WL, data of a memory cell belonging to the corresponding row is read onto bit line BL. In response to the column address decode signal YD, the data on the bit line BL corresponding to the selected column is amplified by the sense amplifier circuit 60 and transmitted to the input / output circuit 70 via the I / O line 65. Data read from the memory cell is read out from input / output circuit 70 via data input / output terminal 16 to the outside.

On the other hand, when writing data, the write data input from data input / output terminal 16 passes through input / output circuit 70 and sense amplifier circuit 60 and receives row address decode signal XD and column address decode signal Y.
The data is written to the memory cell selected by D via the bit line BL.

Semiconductor memory device 1000 further receives the ground voltage and the internal power supply voltage received from the power supply terminal,
A voltage generation circuit 80 for generating a ground voltage GND, a power supply voltage Vcc, and a word line boosted voltage Vpp is provided. The ground wiring 91 supplies a ground voltage GND. Similarly, power supply line 92 transmits power supply voltage Vcc, and power supply line 93
Transmits word line boosted voltage Vpp.

Word line drive circuit 95 receives supply of word line boosted voltage Vpp from power supply line 93, and activates corresponding word line WL in response to row address decode signal XD. The word line driving circuit 95 includes a word driver arranged for each word line, and the activated word line is supplied with a high voltage (Vp) by a corresponding word driver.
p: H level).

FIG. 2 is a circuit diagram showing a configuration of the word driver 100. Word driver 100 activates corresponding word line WL to a selected state (H level: Vpp) in response to activation of row address decode signal XD.

Referring to FIG. 2, word driver 100
Has a node Ni for receiving a row address decode signal,
It includes four inverters IV20, IV22, IV24 and IV26 connected in series between input node Ni and node Na. The output of inverter IV24 is transmitted to node Nb. Thereby, a signal obtained by delaying row address decode signal XD is output to node Na, and an inverted signal of node Na is output to node Nb.

Word driver 100 further includes a level conversion circuit 120 for supplying one of ground voltage GND and word line boosted voltage Vpp to output node No according to the voltage levels of nodes Na and Nb.

Level conversion circuit 120 has a configuration of a cross amplifier having a latch function, and the configuration and operation are the same as those of level conversion circuit 510 described with reference to FIG. The output node No is connected to the word line WL, and charges are supplied to the word line WL via the node No. The word line WL has a parasitic capacitance Cp.

Level conversion circuit 120 has a gate connected to node Na, an N-type MOS transistor QN20 connected between node Nc and ground line 91, and a gate and power supply connected to output node No. P-type MOS transistor QP having a source connected to wiring 93
20, a P-type MOS transistor QP25 having a gate connected to the node Nc and connecting the power supply line 93 and the output node No, and a gate connected to the node Nb. N type M to connect with
OS transistor QN25. Level conversion circuit 1
20 responds to a row address decode signal XD having an amplitude from the ground voltage GND to the power supply voltage Vcc.
L is driven with an amplitude from the ground voltage GND to the word line boosted voltage Vpp.

Word driver 100 further includes a cutoff transistor QP30 connected between transistor QP20 and node Nc, and a cutoff signal generating circuit 110 for generating cutoff signal CTF applied to the gate of cutoff transistor QP30. And further comprising:

Cutoff signal generating circuit 110 operates upon receiving power supply voltage Vcc and ground voltage GND. Cut-off signal generating circuit 110 generates a one-shot pulse at node N1.
And a signal generation circuit 117 that outputs a cutoff signal CTF in response to the one-shot pulse signal output to the node N1.

One-shot pulse generating circuit 115 includes a delay line DL10 for receiving and delaying row address decode signal XD, an inverter IV10 for inverting the output of delay line DL10, a signal XD and an inverter I
It has a logic gate LG10 that outputs the NAND operation result with the output of V10 as two inputs, and an inverter IV12 that inverts the output of logic gate LG10 and outputs it to node N1.

Signal generation circuit 117 includes inverters IV14 and IV16, which are connected in series between node N1 to which the one-shot pulse is output and node N2 to which cutoff signal CTF is output, and boosting capacitor Cm. Have. The signal generation circuit 117 further includes a node N1
And an inverter IV18 for inverting the output of
It has a gate connected to the output node of V18, and has an N-type MOS transistor QN10 connected between ground wiring 91 and node N2.

The amount of current flowing through cutoff transistor QP30 is determined by cutoff signal CT output to node N2.
It changes according to the voltage level of F.

The word driver 100 uses a cut-off transistor QP30 to suppress the generation of a through current that occurs in the conventional word driver 500.

FIG. 3 is a timing chart for explaining the operation of word driver 100.

Referring to FIG. 3, when row address decode signal XD is activated (H level) at time t1, one time is applied to node N1 at time t2 prior to voltage level changes of nodes Na and Nb. A shot pulse is output.

Before time t2, when the voltage level of node N1 is at L level (GND), transistor QN10 in signal generation circuit 117 is turned on, so that the voltage level of node N2, ie, cut-off signal C
TF is set to L level (GND).

At time t2, when the voltage level of node N1 rises to H level (Vcc), inverter IV
18 goes low, the transistor Q
N10 is turned off. At this time, the output of inverter IV16 attains H level (Vcc), and boost capacitor Cm
Is supplied with a power supply voltage Vcc. At this time, the node N
Assuming that the parasitic capacitance of C2 is C2, capacitors Cm and Cm
The charge of No. 2 is held because no discharge path is formed.
Therefore, assuming that the accumulated charge is Q, Q = Cm × Vm
= C2 × V2 holds (Vm: voltage applied to boost capacitor Cm, C2: voltage applied to parasitic capacitance C2).

At this time, the capacitance of the capacitor is set to Cm >> C
If V2 is set to 2, V2 >> Vm can be satisfied, and a voltage higher than the power supply voltage Vcc can be obtained at the node N2. In word driver 100, the voltage level of cutoff signal CTF in the active state (H level) is set to word line boosted voltage Vpp level by appropriately setting the capacitance value of boosting capacitor Cm.

Therefore, cutoff signal CTF is activated (Vpp level) for a certain period in response to the one-shot pulse signal activated at time t2.

On the other hand, between times t2 and t3, the activation of row address decode signal XD is transmitted to nodes Na and Nb, and the voltage levels of both are at H level (Vcc) and L level (GND), respectively. ). In response, transistor QN20 turns on and transistor QN25 turns off. Transistor Q
In response to the turning on of N20, a current path is formed between node Nc and ground line 91.

However, in the word driver 100, prior to the time t3 when the transistor QN20 is turned on, the cutoff signal CTF is activated to raise the voltage of the node N2 to the Vpp level.

The cutoff signal CTF maintains the active state (Vpp level) ΔT1 during the period when the voltage of the node N1 is at the H level (Vcc) by the one-shot pulse generation circuit 110. Cut-off transistor QP30 is turned off, and no current path is formed between power supply wiring 93 and level conversion circuit 120 and ground wiring 91, through current i flows.

Under the state where the transistor QP30 is kept off, the voltage level of the node Nc changes to the L level (GND) by turning on the transistor QN20, and the transistor QP25 is turned on in response to this. Word line WL is connected to power supply line 93. As a result, the voltage level of the word line WL becomes the parasitic capacitance Cp
After the time required for charging the battery has passed, the non-selected state (GN
D level) to the selected state (Vpp). Period ΔT given by one-shot pulse generation circuit
By setting 1 to be longer than the time required for charging the parasitic capacitance Cp of the word line WL, it is possible to prevent a through current from occurring when the word line WL is activated.

The parasitic capacitance existing at the node Nc is:
Since it is smaller than the parasitic capacitance Cp of the word line, the current driving capabilities of the transistors QP20 and QN20 can be set smaller than those of the transistors QP25 and QN25. In FIG. 2, the notation of W = 7 and W = 24 beside each transistor indicates, for example, that the transistor widths are 24 μm and 7 μm, respectively. When having a common gate length L, transistor size W / L (W: channel width, L: channel length) is set larger in transistors QN25 and QP25 than in transistors QN20 and QP20. The size of each transistor may be determined according to the parasitic capacitance of the node, the margin of the layout area, and the like. By increasing the current driving capability of transistors QP25 and QN25, the word line can be activated at high speed. .

In the word driver 100,
A cut-off transistor is provided on only one side, and a transistor QP25 for directly supplying a charge to the word line WL.
And a cut-off transistor corresponding to QP25 is not provided. For this reason, it is possible to suppress the generation of a through current at the time of activating the word line, and to secure the charge supply capability to the word line WL.

The cut-off transistor QP30
Is an N-type MOS transistor, the voltage level of the node Nc can be set to the Vpp level without causing a voltage drop while the cutoff signal CTF is in an inactive state (L level). is there. For this reason, the transistor QP25 having the gate connected to the node Nc can be completely turned off, and unnecessary current consumption can be prevented.

Further, the cutoff signal generation circuit 110
The H level of the cutoff signal CTF is changed to the word line boosted voltage V
Since the voltage is boosted to the pp level, the cutoff transistor QP30 can be completely turned off during the active period of the cutoff signal CTF, and the generation of a through current can be prevented.

Further, the cutoff signal generation circuit 110
Is configured such that when a one-shot pulse is not generated at node N1, transistor QN10 connects node N2 to ground line 91, so that cut-off signal CTF is in an active state (H level). In other cases, the voltage level of node N2 is reliably set to the ground voltage level, and cutoff transistor QP
30 can be turned on. As a result, malfunction of the word driver 100 can be prevented.

[Second Embodiment] In a second embodiment, similarly, another configuration of a word driver capable of realizing a reduction in through current will be described.

FIG. 4 is a circuit diagram showing a configuration of word driver 200 according to the second embodiment of the present invention.

Referring to FIG. 4, word driver 200
Is input node N receiving row address decode signal XD.
inverter IV30 connected between i and node Na
And IV32, and an inverter IV34 that inverts the voltage level of node Na and outputs it to node Nb.
Inverters IV30, IV32 and IV34 are driven by power supply voltage Vcc and ground voltage GND.
Therefore, a signal having an amplitude voltage from ground voltage GND to power supply voltage Vcc is output to nodes Na and Nb.

Word driver 200 further includes a level conversion circuit 210 for setting the voltage levels of nodes Nc and Nd to one of ground voltage GND and word line boosted voltage Vpp according to the voltage levels of nodes Na and Nb. Prepare. Since the configuration of level conversion circuit 210 is similar to that of level conversion circuit 510 described in the related art, description thereof will not be repeated.

The word driver 200 further includes a node N
c and word line W according to the voltage level of node Nb.
A charge supply circuit 220 for setting the voltage level of L to one of the word line boosted voltage Vpp and the ground voltage GND is further provided.

Charge supply circuit 220 has a gate connected to node Nc, a P-type MOS transistor QP40 connecting power supply line 93 and output node No, and a gate connected to node Nb. N-type MOS transistor Q connected between node No and ground line 91
N40. Output node No is connected to word line WL. The word line WL has a parasitic capacitance Cp.

In word driver 200, transistor QN4 for directly supplying charges to word line WL is provided.
0 and the transistor size of QP40 are determined by transistors QN42, QP4 included in level conversion circuit 210.
2, set larger than QN44 and QP44.
As in FIG. 2, in the drawing, W is next to each transistor.
= 7 and W = 24 indicate that the transistor widths are 24 μm and 7 μm, for example.
When these transistors have a common gate length L, the transistor size W / L is set to be larger in the transistors QN40 and QP40 than in the transistors QN42, QP42, QN44, and QP44. Is done. This corresponds to the node No connected to the word line WL and the internal nodes Nc and Nd of the circuit.
This is for the purpose of promptly charging the word line WL.

FIG. 5 is a timing chart for explaining the operation of word driver 200.

Referring to FIG. 5, at time t1, row address decode signal XD is activated (H level). Accordingly, at time t2, the voltage levels of nodes Na and Nb change to H level (Vcc) and L level (GND), respectively. In response, transistor QN42 turns on, and the voltage level of node Nc starts to change from Vpp level to ground voltage GND level. As the voltage level of node Nc decreases, transistor QP44 turns on, and the voltage level of node Nd becomes
Although the level starts to change from the L level to the H level (Vpp), in the word driver 200, the node Nd and the word line WL having the parasitic capacitance are separated from each other, so that the word driver 200 is compared with the word driver 500 of the related art. , Node Nd
Changes quickly.

In response to the rise of the voltage level of node Nd to H level, at time t3 when transistor QP42 turns off, through current i stops flowing. In response to a change in the voltage level of the node Nc, the charge supply circuit 220
The middle transistor QP40 turns on, and the word line WL
The charge is supplied from the power supply line 93, and the word line WL is activated to the selected state (Vpp level).

The through current in level conversion circuit 210 increases as the voltage level of node Na rises to H level.
After the transistor QN42 is turned on, the transistor QP44 is turned on in response to a change in the voltage level of the node Nc, the voltage level of the node Nd rises to the H level, and this occurs during ΔT2 until the transistor QP42 is turned off.

In the word driver 200, the node Nd connected to the gate of the transistor QP42 is separated from the word line WL having a large parasitic capacitance, so that the transistor QP42 can be quickly turned off when the word line is activated. it can. Therefore, the amount of the through current i can be reduced by shortening the time ΔT2 during which the through current flows.

Transistor QN in charge supply circuit 220
The transistor sizes of the transistors 40 and QP40, that is, the current supply capability may be set according to the parasitic capacitance of the word line WL. Further, the transistor size of the transistor in the level conversion circuit 210 may be determined in consideration of the balance between the parasitic capacitance existing at the nodes Nc and Nd and the layout area of the transistor.

The embodiments disclosed this time are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[0077]

According to the semiconductor memory device of the present invention, the selection of a word line is instructed by a control signal until the voltage level of the word line actually rises to a voltage corresponding to the selected state. During this time, the current cutoff switch circuit is turned off, so that a through current flowing through the first and fourth charge supply circuits when a word line is selected can be cut off, and power consumption can be reduced.

In the semiconductor memory device according to the third aspect, the charge supply capability of the second and third charge supply circuits for supplying the electric charges to the word lines is set large, so that the semiconductor memory device according to the first aspect has the effect. In addition, the word line can be quickly driven to the selected state.

In the semiconductor memory device according to the fourth and fifth aspects, the amplitude voltage of the current cutoff control signal is set to a voltage level by boosting the amplitude voltage of the control signal. In addition, the through current can be sufficiently cut off by the current cutoff switch circuit.

In the semiconductor memory device according to the present invention, when activation of the current cutoff control signal is not instructed, the node for outputting the current cutoff control signal is connected to the second power supply wiring. In addition to the effects of the semiconductor memory device described in Item 1, malfunction of the word line drive circuit can be prevented.

In the semiconductor memory device according to the eighth, ninth and tenth aspects, the charge supply circuit for supplying the electric charge to the first internal node is operated separately from the voltage level of the word line, and supplies the electric charge to the word line. Since the charge supply capability of the current supply circuit is set to be large, it is possible to reduce the time for generating a through current when selecting a word line and quickly drive the word line to the selected state.

[Brief description of the drawings]

FIG. 1 shows a semiconductor memory device 10 according to a first embodiment of the present invention.
FIG. 1 is a schematic block diagram showing the overall configuration of a 00.

FIG. 2 is a circuit diagram showing a configuration of a word driver 100.

FIG. 3 is a timing chart for explaining the operation of the word driver 100.

FIG. 4 is a word driver 20 according to the second embodiment of the present invention.
FIG. 3 is a circuit diagram illustrating a configuration of a zero.

FIG. 5 is a timing chart for explaining the operation of the word driver 200.

FIG. 6 is a circuit diagram showing a configuration of a memory cell of a general dynamic RAM.

FIG. 7 is a circuit diagram showing a configuration of a conventional word driver 500.

FIG. 8 is a timing chart illustrating an operation of the word driver 500.

[Explanation of symbols]

91 ground wiring, 92 power supply wiring (Vcc), 93 power supply wiring (Vpp), 100, 200 word driver,
110 cut-off signal generation circuit, 120, 210
Level conversion circuit, 220 charge supply circuit.

Claims (10)

[Claims] 1. A semiconductor memory device, comprising: a plurality of memory cells arranged in a matrix; a plurality of word lines for selecting a row of the memory cells; and a plurality of word lines corresponding to a selected state of the word lines. A first power supply line for supplying a first voltage, a second power supply line for supplying a second voltage corresponding to a non-selected state of the word line, and an active state arranged for each of the plurality of word lines. A word line driving circuit that drives a corresponding one of the plurality of word lines to a selected state in response to a control signal set to a third voltage lower than the first voltage. A word line drive circuit configured to: in response to the control signal, transfer a charge between an internal node and the second power supply line; And the first power supply wiring and the A second charge supply circuit for exchanging charges with a corresponding word line; and a second charge supply circuit between the corresponding word line and the second power supply line in response to an inverted signal of the control signal. A third charge supply circuit for transmitting and receiving charges; and
A fourth charge supply circuit for transferring charges between the first power supply line and the internal node; and a fourth charge supply circuit for transferring charges between the first power supply line and the internal node. A current cut-off switch circuit electrically coupled to the control signal and turned off for a predetermined period in response to the control signal. 2. The predetermined period is longer than a time required from the time when the selection of a word line is instructed by the control signal to the time when the voltage level of the word line reaches the first voltage. Semiconductor storage device. 3. The semiconductor memory device according to claim 1, wherein said second and third charge supply circuits have a charge supply capability greater than said first and fourth charge supply circuits. 4. The word line drive circuit further includes a current cutoff control circuit that generates a current cutoff control signal for controlling on / off of the current cutoff supply circuit in response to the control signal. And setting the voltage level of the current cutoff control signal to a boosted voltage higher than the third voltage and the second level.
2. The semiconductor memory device according to claim 1, wherein said voltage is set to one of said voltages. 5. The semiconductor memory device according to claim 4, wherein said boosted voltage is set according to said first voltage. 6. The one-shot pulse signal generation circuit that outputs a one-shot pulse signal activated for the predetermined period to a first node in response to activation of the control signal, A boost capacitor electrically coupled between a second node that outputs a current cutoff control signal and the first node; and a second power supply line corresponding to an active state of the one-shot pulse signal. And a switch circuit that cuts off the second node and the second power supply line and the second node in response to the inactive state of the one-shot pulse signal. 5. The semiconductor memory device according to claim 4, wherein a capacitance value of the boosting capacitor is larger than a parasitic capacitance existing at the second node. 7. The first charge supply circuit receives a control signal at a gate, and is electrically coupled between the internal node and the second power supply line. M
An OS transistor, wherein the second charge supply circuit has a gate connected to the internal node, and is electrically coupled between the corresponding word line and the first power supply line. A second MOS transistor of a two-conductivity type, wherein the third charge supply circuit receives an inverted signal of a control signal at a gate, and supplies an electric current between the corresponding word line and the second power supply line. A third MOS transistor of the first conductivity type coupled to each other; the fourth charge supply circuit having a gate connected to the corresponding word line; A fourth MOS transistor of the second conductivity type electrically coupled to the internal node, wherein the current cutoff switch circuit receives the current cutoff control signal at a gate, and receives the first power supply. Between the wiring and the internal node A fifth MOS transistor of the second conductivity type electrically coupled in series with the fourth MOS transistor, wherein a ratio of a channel width to a channel length in the second and third MOS transistors is: 5. The semiconductor memory device according to claim 4, wherein said ratio is greater than said ratio in said first and fourth MOS transistors. 8. A semiconductor memory device, comprising: a plurality of memory cells arranged in a matrix; a plurality of word lines for selecting rows of the memory cells; and a plurality of word lines corresponding to a selected state of the word lines. A first power supply line for supplying a first voltage, a second power supply line for supplying a second voltage corresponding to a non-selected state of the word line, a control signal arranged for each of the plurality of word lines, A word line drive circuit that drives a corresponding one of the plurality of word lines to a selected state, the word line drive circuit comprising: a charge supply node connected to the corresponding word line; A first internal node and a second internal node in response to the control signal.
A first charge supply circuit for transmitting and receiving charges to and from a power supply line, and a first charge supply circuit between a second internal node and the first power supply line according to a voltage level of the first internal node. And a second charge supply circuit for transferring charges between the second internal node and the second power supply line in response to an inverted signal of the control signal. A third charge supply circuit, and the first charge supply circuit according to a voltage level of the second internal node.
A fourth charge supply circuit for transmitting and receiving charges between the internal node of the first power supply line and the first power supply line;
A fifth line for transmitting and receiving charges between the power supply line and the charge supply node and transmitting and receiving charges between the charge supply node and the second power supply line in response to the control signal. And a charge supply circuit, wherein the charge supply capability of the fifth charge supply circuit is larger than the charge supply capability of the first to fourth charge supply circuits. 9. The first charge supply circuit has a gate for receiving the control signal, and is electrically connected between the first internal node and the second power supply line. A first MOS transistor, the second charge supply circuit having a gate connected to the first internal node, and connecting the second internal node to the first power supply line. A second MOS transistor of the second conductivity type electrically coupled therebetween, the third charge supply circuit having a gate for receiving an inverted signal of the control signal, and Node and the second
And a third MOS transistor of the first conductivity type electrically coupled to a power supply line of the second type, and the fourth charge supply circuit has a gate connected to the second internal node. And a fourth MOS transistor of the second conductivity type electrically coupled between the first internal node and the first power supply wiring, wherein the fifth charge supply circuit comprises: A fifth MOS transistor of the second conductivity type having a gate connected to a first internal node and electrically coupled between the charge supply node and the first power supply wiring; 9. A sixth MOS transistor of the first conductivity type, the gate having a gate for receiving an inverted signal of the signal, and electrically coupled between the charge supply node and the second power supply line. 13. The semiconductor memory device according to claim 1. 10. The semiconductor memory device according to claim 9, wherein a ratio of a channel width to a channel length in said fifth and sixth MOS transistors is larger than said ratio in said first to fourth MOS transistors. .